--- /dev/null
+ .xlist\r
+\r
+;;\r
+;; HD64180/Z180 Register Definitions\r
+;;\r
+\r
+\r
+b2m macro name,nr\r
+name equ nr\r
+M_&name equ 1 shl nr\r
+ endm\r
+\r
+; ifndef IOBASE\r
+IOBASE equ 0\r
+; endif\r
+\r
+cntla0 equ IOBASE+00h ;ASCI Control Register A Channel 0\r
+cntla1 equ IOBASE+01h ;ASCI Control Register A Channel 1\r
+ b2m MPE, 7 ;Multi-Processor Mode Enable\r
+ b2m RE, 6 ;Receiver Enable\r
+ b2m TE, 5 ;Transmitter Enable\r
+ b2m RTS0, 4 ;Request to Send Channel 0\r
+ b2m CKA1D, 4 ;\r
+ b2m MPBR, 3 ;Multiprocessor Bit Receive (Read)\r
+ b2m EFR, 3 ;Error Flag Reset (Write)\r
+ b2m MOD2, 2 ;Data Format Mode 1 = 8-Bit data\r
+ b2m MOD1, 1 ;1 = Parity enabled\r
+ b2m MOD0, 0 ;1 = 2 stop bits\r
+\r
+cntlb0 equ IOBASE+02h ;ASCI Control Register B Channel 0\r
+cntlb1 equ IOBASE+03h ;ASCI Control Register B Channel 1\r
+ b2m MPBT,7 ;Multiprocessor Bit Transmit\r
+ b2m MP,6 ;Multiprocessor Mode\r
+ b2m CTS,5 ;Clear to Send\r
+ b2m PS,5 ;Prescale\r
+ b2m PEO,4 ;Parity Even Odd\r
+ b2m DR,3 ;Divede Ratio\r
+ b2m SS2,2 ;Source/Speed Select 2,1,0\r
+ b2m SS1,1 ;\r
+ b2m SS0,0 ;\r
+\r
+stat0 equ IOBASE+04h ;ASCI Status Channel 0\r
+stat1 equ IOBASE+05h ;ASCI Status Channel 1\r
+ b2m RDRF,7 ;Receive Data Register Full\r
+ b2m OVRN,6 ;Overrun Error\r
+ b2m PERR,5 ;Parity Error (M80: PE conflicts with JP/CALL cc)\r
+ b2m FE,4 ;Framing Error\r
+ b2m RIE,3 ;Receive Interrupt Enable\r
+ b2m DCD0,2 ;Data Carrier Detect (Ch 0)\r
+ b2m CTS1E,2 ;Clear To Send (Ch 1)\r
+ b2m TDRE,1 ;Transmit Data Register Empty\r
+ b2m TIE,0 ;Transmit Interrupt Enable\r
+\r
+tdr0 equ IOBASE+06h ;ASCI Transmit Data\r
+tdr1 equ IOBASE+07h ;ASCI Transmit Data\r
+rdr0 equ IOBASE+08h ;ASCI Receive Data\r
+rdr1 equ IOBASE+09h ;ASCI Receive Data\r
+\r
+cntr equ IOBASE+0Ah ;CSI/O Control Register\r
+trdr equ IOBASE+0Bh ;CSI/O Transmit/Receive Data Register\r
+\r
+tmdr0l equ IOBASE+0Ch ;Timer Data Register Channel 0\r
+tmdr0h equ IOBASE+0Dh ;\r
+rldr0l equ IOBASE+0Eh ;Timer Reload Register Channel 0\r
+rldr0h equ IOBASE+0Fh ;\r
+tcr equ IOBASE+10h ;Timer Control Register\r
+ b2m TIF1,7 ;Timer Interrupt Flag\r
+ b2m TIF0,6 ;\r
+ b2m TIE1,5 ;Timer Interrupt Enable\r
+ b2m TIE0,4 ;\r
+ b2m TOC1,3 ;Timer Output Control\r
+ b2m TOC0,2 ;\r
+ b2m TDE1,1 ;Timer Down Count Enable\r
+ b2m TDE0,0 ;\r
+\r
+\r
+asext0 equ IOBASE+12h ;ASCI Extension Control Register\r
+asext1 equ IOBASE+13h ;ASCI Extension Control Register\r
+ b2m DCD0DIS,6 ;DCD0 Disable\r
+ b2m CTS0DIS,5 ;CTS0 Disable\r
+ b2m X1,4 ;CKA * 1 Clock/Samle Rate Divider\r
+ b2m BRGMOD,3 ;BRG Mode (Baud rate generator)\r
+ b2m BREAKEN,2 ;Break Enable\r
+ b2m BREAK,1 ;Break detected\r
+ b2m SENDBREAK,0 ;Send Break\r
+\r
+tmdr1l equ IOBASE+14h ;Timer Data Register Channel 1\r
+tmdr1h equ IOBASE+15h ;\r
+rldr1l equ IOBASE+16h ;Timer Reload Register Channel 1\r
+rldr1h equ IOBASE+17h ;\r
+\r
+frc equ IOBASE+18h ;Free Running Counter\r
+\r
+astc0l equ IOBASE+1Ah ;ASCI Time Constant Register 0\r
+astc0h equ IOBASE+1Bh ;\r
+astc1l equ IOBASE+1Ch ;ASCI Time Constant Register 1\r
+astc1h equ IOBASE+1Dh ;\r
+\r
+cmr equ IOBASE+1Eh ;Clock Mutiplier Register\r
+ b2m X2CM,7 ;X2 Clock Multiplier\r
+ b2m LNC,6 ;Low Noise Crystal\r
+\r
+ccr equ IOBASE+1Fh ;CPU Control Register\r
+ b2m NCD 7 ;No Clock Divide\r
+\r
+sar0l equ IOBASE+20h ;DMA Src Adr Register Channel 0\r
+sar0h equ IOBASE+21h ;\r
+sar0b equ IOBASE+22h ;\r
+dar0l equ IOBASE+23h ;DMA Dst Adr Register Channel 0\r
+dar0h equ IOBASE+24h ;\r
+dar0b equ IOBASE+25h ;\r
+bcr0l equ IOBASE+26h ;DMA Byte Count Register Channel 0\r
+bcr0h equ IOBASE+27h ;\r
+\r
+mar1l equ IOBASE+28h ;DMA Memory Address Register Channel 1\r
+mar1h equ IOBASE+29h ;\r
+mar1b equ IOBASE+2Ah ;\r
+iar1l equ IOBASE+2Bh ;DMA I/O Address Register Channel 1\r
+iar1h equ IOBASE+2Ch ;\r
+iar1b equ IOBASE+2Dh ;\r
+ b2m ALTE,7 ;Alternating Chnnels\r
+ b2m ALTC,6 ;Currently selected DMA Channel when Bit7=1\r
+ b2m REQ1SEL2,2 ;\r
+ b2m REQ1SEL1,1 ;\r
+ b2m REQ1SEL0,0 ;\r
+\r
+bcr1l equ IOBASE+2Eh ;DMA Byte Count Register Channel 1\r
+bcr1h equ IOBASE+2Fh ;\r
+\r
+dstat equ IOBASE+30h ;DMA Status Register\r
+ b2m DE1,7 ;DMA enable ch 1,0\r
+ b2m DE0,6 ;\r
+ b2m NDWE1,5 ;DMA Enable Bit Write Enable 1,0\r
+ b2m NDWE0,4 ;\r
+ b2m DIE1,3 ;DMA Interrupt Enable 1,0\r
+ b2m DIE0,2 ;\r
+ b2m DME,0 ;DMA Master enable\r
+\r
+dmode equ IOBASE+31h ;DMA Mode Register\r
+ b2m DM1,5 ;Ch 0 Destination Mode 1,0\r
+ b2m DM0,4 ;\r
+ b2m SM1,3 ;Ch 0 Source Mode 1,0\r
+ b2m SM0,2 ;\r
+ b2m MMOD,1 ;Memory MODE select (0=cycle steel/1=burst)\r
+\r
+dcntl equ IOBASE+32h ;DMA/WAIT Control\r
+ b2m MWI1,7 ;Memory Wait Insertion\r
+ b2m MWI0,6 ;\r
+ b2m IWI1,5 ;I/O Wait Insertion\r
+ b2m IWI0,4 ;\r
+ b2m DMS1,3 ;DREQi Select (Edge/Level)\r
+ b2m DMS0,2 ;\r
+ b2m DIMA1,1 ;DMA Ch1 I/O Memory Mode Select\r
+ b2m DIMA0,0\r
+M_MWI equ M_MWI1 + M_MWI0\r
+M_IWI equ M_IWI1 + M_IWI0\r
+\r
+il equ IOBASE+33h ;Interrupt Vector Low Register\r
+itc equ IOBASE+34h ;INT/TRAP Control Register\r
+ b2m TRAP,7 ;Trap\r
+ b2m UFO,6 ;Unidentified Fetch Object\r
+ b2m ITE2,2 ;/INT Enable 2,1,0\r
+ b2m ITE1,1 ;\r
+ b2m ITE0,0 ;\r
+\r
+rcr equ IOBASE+36h ;Refresh Control Register\r
+ b2m REFE,7 ;Refresh Enable\r
+ b2m REFW,6 ;Refresh Wait State\r
+ b2m CYC1,1 ;Cycle select\r
+ b2m CYC0,0 ;\r
+\r
+cbr equ IOBASE+38h ;MMU Common Base Register\r
+bbr equ IOBASE+39h ;MMU Bank Base Register\r
+cbar equ IOBASE+3Ah ;MMU Common/Bank Register\r
+\r
+omcr equ IOBASE+3Eh ;Operation Mode Control Register\r
+ b2m M1E,7 ;M1 Enable\r
+ b2m M1TE,6 ;M1 Temporary Enable\r
+ b2m IOC,5 ;I/O Compatibility\r
+\r
+icr equ IOBASE+3Fh ;I/O Control Register\r
+ b2m IOSTP,5 ;I/O Stop\r
+;\r
+; Interrupt Vectors\r
+;\r
+\r
+IV$INT1 equ 0 ;/INT1 (highest priority)\r
+IV$INT2 equ 2 ;/INT2\r
+IV$PRT0 equ 4 ;PRT channel 0\r
+IV$PRT1 equ 6 ;PRT channel 1\r
+IV$DMA0 equ 8 ;DMA channel 0\r
+IV$DMA1 equ 10 ;DMA channel 1\r
+IV$CSIO equ 12 ;CSI/O\r
+IV$ASCI0 equ 14 ;ASCI channel 0\r
+IV$ASCI1 equ 16 ;ASCI channel 1 (lowest priority)\r
+\r
+ .list\r
projects / z180-stamp-cpm3.git / blobdiff