OBJ := $(SRC:.180=.rel)
-$(foreach X,$(subst =,:=,$(filter VCS_%,\
- $(shell autorevision -t sh -o $(CURDIR)/autorevision.cache))),$(eval $X))
+$(foreach X,$(subst =,:=,$(subst ",,$(filter VCS_%,\
+ $(shell autorevision -t sh -o $(CURDIR)/autorevision.cache)))),$(eval $X))
VERS := $(shell echo "$(VCS_TAG)" | sed -e 's/hexrel-/0./g' -e 's/^v//g')
-ifneq ($(VCS_TICK),"0")
- VERS := $(VERS).$(subst ",,$(VCS_TICK))
+ifneq ($(VCS_TICK),0)
+ VERS := $(VERS).$(VCS_TICK)
endif
-ifneq ($(VCS_BRANCH),"master")
- VERS := $(VERS)-$(subst ",,$(VCS_BRANCH))
+ifneq ($(VCS_BRANCH),master)
+ VERS := $(VERS)-$(VCS_BRANCH)
endif
-ifeq ($(VCS_WC_MODIFIED),"1")
+ifeq ($(VCS_WC_MODIFIED),1)
VERS := $(VERS)-dirty
endif
SYSFILE = cpm3_$(VERS).sys
MAPFILE = bnkbios3_$(VERS).map
-ZIPFILE = cpm3_$(VERS).zip
+DIST_NAME = z180-stamp-cpm3_$(VERS).zip
+DIST_NAME_BIN = z180-stamp-cpm3-bin_$(VERS).zip
+PREFIX = z180-stamp-cpm3_$(VERS)
+
+CP = cp
+RM = rm -f
+GIT = git
+ZIP = zip
#CP/M emulator
CPMEMU = zxcc
bios: bnkbios3.spr
map: $(MAPFILE)
-.phony: bin-dist
-bin-dist: $(ZIPFILE)
$(OBJ): $(INC)
boot.rel: version.inc
@$(cpm-asm)
-$(ZIPFILE): $(SYSFILE) $(MAPFILE)
- @rm -f $@
- zip -9 $@ $(SYSFILE) $(MAPFILE)
+.phony: bin-dist
+bin-dist: $(SYSFILE) $(MAPFILE)
+ $(ZIP) -9 $(DIST_NAME_BIN) $(SYSFILE) $(MAPFILE)
+
+.phony: dist
+dist: $(SYSFILE) $(MAPFILE)
+ $(GIT) archive --format=zip --prefix=$(PREFIX)/ -9 -o $(DIST_NAME) HEAD^{tree}
+ @mkdir -p $(PREFIX)
+ @$(CP) autorevision.cache version.inc $(PREFIX)
+ $(ZIP) -r -9 $(DIST_NAME) $(PREFIX) $(SYSFILE) $(MAPFILE)
+ @$(RM) -r $(PREFIX)
.phony: clean realclean
clean:
- rm -f *.rel *.lst *.sym version.inc
+ $(RM) *.rel *.lst *.sym version.inc
realclean: clean
- rm -f *.map *.prn *~
+ $(RM) *.map *.prn *~
#==================================================================
--- /dev/null
+\r
+FALSE equ 0\r
+TRUE equ NOT FALSE\r
+\r
+\r
+DEBUG equ true\r
+\r
+banked equ true\r
+\r
+;-----------------------------------------------------\r
+; CPU and BANKING types\r
+\r
+\r
+CPU_Z180 equ TRUE\r
+CPU_Z80 equ FALSE\r
+\r
+ROMSYS equ FALSE\r
+\r
+AVRCLK equ 18432 ;[KHz]\r
+\r
+ if CPU_Z180\r
+\r
+;-----------------------------------------------------\r
+;FOSC equ AVRCLK/2 ;Oscillator frequency [KHz]\r
+;PHI equ FOSC*2 ;CPU frequency (clock doubler enabled)\r
+\r
+;----------------------------------------------------------------------\r
+; Baudrate Generator for x16 clock mode:\r
+; TC = (f PHI / (32 * baudrate)) - 2\r
+;\r
+; PHI [MHz]: 9.216 18.432\r
+; baudrate TC TC\r
+; ----------------------\r
+; 115200 - 3\r
+; 57600 3 8\r
+; 38400 - 13\r
+; 19200 13 28\r
+; 9600 28 58\r
+\r
+\r
+;-----------------------------------------------------\r
+; Programmable Reload Timer (PRT)\r
+\r
+PRT_PRE equ 20 ;PRT prescaler\r
+\r
+;-----------------------------------------------------\r
+; MMU\r
+\r
+COMMON_SIZE equ 4*1024 ;Common Area size in bytes\r
+ ;must be multiple of 4K\r
+if (COMMON_SIZE mod 1000h)\r
+ .printx COMMON_SIZE not multiple of 4K!\r
+ end ;stop assembly\r
+endif\r
+CMN_SIZE equ COMMON_SIZE/1000h ;4K units\r
+BNK_SIZE equ 64/4 - CMN_SIZE ;bank size (4K units)\r
+BANKS equ (512/4 - CMN_SIZE)/BNK_SIZE ;max nr. of banks\r
+\r
+; Logical address space, CBAR values\r
+\r
+CA equ 10h - CMN_SIZE ;common area start (64K - common size)\r
+BA equ 0 ;banked area start\r
+\r
+ if 0\r
+\r
+SYS$CBR equ 0\r
+SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r
+USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r
+\r
+ endif\r
+ if 1\r
+\r
+SYS$CBR equ BNK_SIZE\r
+SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r
+USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r
+\r
+ endif\r
+\r
+\r
+;-----------------------------------------------------\r
+\r
+CREFSH equ 0 ;Refresh rate register (disable refresh)\r
+CWAITIO equ 3 shl IWI0 ;Max I/O Wait States, 0 Memory Wait States\r
+PHI_X2 equ 0 ;set to M_X2CM to enable the clock doubler\r
+\r
+ endif ;CPU_Z180\r
+ if CPU_Z80\r
+\r
+PHI equ AVRCLK/5 ;CPU frequency [KHz]\r
+BAUDCLCK equ AVRCLK/10 ;Baudrate clock [KHz]\r
+;BDCLK16 equ\r
+\r
+SIOAD EQU 0bch\r
+SIOAC EQU 0bdh\r
+SIOBD EQU 0beh\r
+SIOBC EQU 0bfh\r
+\r
+CTC0 EQU 0f4h\r
+CTC1 EQU 0f5h\r
+CTC2 EQU 0f6h\r
+CTC3 EQU 0f7h\r
+\r
+;\r
+; Init Serial I/O for console input and output (SIO-A)\r
+;\r
+; Baudrate clock: 1843200 Hz (Bus connector pin A17)\r
+;\r
+; Baudrate Divider SIO CTC\r
+; ---------------------------------\r
+; 115200 16 16 1\r
+; 57600 32 16 2\r
+; 38400 48 16 3\r
+; 19200 96 16 6\r
+; 9600 192 16 12\r
+; 4800 384 16 24\r
+; 2400 768 16 48\r
+; 1200 1536 16 96\r
+; 600 3072 16 192\r
+; 300 6144 64 92\r
+\r
+ endif ; CPU_Z80\r
+\r
+ if ROMSYS\r
+c$rom equ 0a5h\r
+ROM_EN equ 0C0h\r
+ROM_DIS equ ROMEN+1\r
+ if CPU_Z180\r
+CWAITROM equ 2 shl MWI0\r
+ endif\r
+ endif\r
+\r
+\r
+DDTZRSTVEC equ 030h ;DDTZ Restart vector (breakpoints)\r
+\r
+INIDONE equ 03Fh ;CP/M skip hw init, if this address\r
+INIDONEVAL equ 080h ; is set to this value.\r
+\r
+mtx.fifo_len equ 64 ;Message transfer fifos\r
+mtx.fifo_id equ 0 ; This *must* have #0\r
+mrx.fifo_len equ 64\r
+mrx.fifo_id equ 1\r
+\r
+ci.fifo_len equ 32 ;AVRCON (USB0) Character I/O via AVR\r
+ci.fifo_id equ 2\r
+co.fifo_len equ 32\r
+co.fifo_id equ 3\r
+\r
+s0.rx_len equ 128 ;Serial 0 (ASCI0) buffers\r
+s0.rx_id equ 4 ;\r
+s0.tx_len equ 128 ;\r
+s0.tx_id equ 5 ;\r
+\r
+s1.rx_len equ 128 ;Serial 1 (ASCI1) buffers\r
+s1.rx_id equ 6 ;\r
+s1.tx_len equ 128 ;\r
+s1.tx_id equ 7 ;\r
+\r
+AVRINT5 equ 4Fh\r
+AVRINT6 equ 5Fh\r
+;PMSG equ 80h\r
+\r
+;-----------------------------------------------------\r
+; Definition of (logical) top 2 memory pages\r
+\r
+sysram_start equ 0FE00h\r
+bs$stack$size equ 80\r
+\r
+isvsw_loc equ 0FEE0h\r
+\r
+ivtab equ 0ffc0h ;int vector table\r
+iv2tab equ ivtab + 2*9\r
+\r
+\r
+\r
+;-----------------------------------------------------\r
+\r
+o.id equ -4\r
+o.mask equ -3\r
+o.in_idx equ -2\r
+o.out_idx equ -1\r
+\r
+ .lall\r
+\r
+mkbuf macro id,name,size\r
+ if ((size AND (size-1)) NE 0) OR (size GT 256)\r
+ .printx Error: buffer ^size must be power of 2 and in range 0..256!\r
+ name&.mask equ ;wrong size error\r
+ else\r
+ db id\r
+ db size-1\r
+ ds 2\r
+ name:: ds size\r
+ name&.mask equ low (size-1)\r
+ if size ne 0\r
+ name&.end equ $-1\r
+ name&.len equ size\r
+ name&.id equ id\r
+ endif\r
+ endif\r
+endm\r
+\r
+;-----------------------------------------------------\r
+\r
+inidat macro\r
+ cseg\r
+??ps.a defl $\r
+ endm\r
+\r
+inidate macro\r
+??ps.len defl $ - ??ps.a\r
+ dseg\r
+ ds ??ps.len\r
+ endm\r
+\r
+;-----------------------------------------------------\r
+\r
+b0call macro address\r
+ call _b0call\r
+ dw address\r
+ endm\r
--- /dev/null
+ .xlist\r
+\r
+;;\r
+;; HD64180/Z180 Register Definitions\r
+;;\r
+\r
+\r
+b2m macro name,nr\r
+name equ nr\r
+M_&name equ 1 shl nr\r
+ endm\r
+\r
+; ifndef IOBASE\r
+IOBASE equ 0\r
+; endif\r
+\r
+cntla0 equ IOBASE+00h ;ASCI Control Register A Channel 0\r
+cntla1 equ IOBASE+01h ;ASCI Control Register A Channel 1\r
+ b2m MPE, 7 ;Multi-Processor Mode Enable\r
+ b2m RE, 6 ;Receiver Enable\r
+ b2m TE, 5 ;Transmitter Enable\r
+ b2m RTS0, 4 ;Request to Send Channel 0\r
+ b2m CKA1D, 4 ;\r
+ b2m MPBR, 3 ;Multiprocessor Bit Receive (Read)\r
+ b2m EFR, 3 ;Error Flag Reset (Write)\r
+ b2m MOD2, 2 ;Data Format Mode 1 = 8-Bit data\r
+ b2m MOD1, 1 ;1 = Parity enabled\r
+ b2m MOD0, 0 ;1 = 2 stop bits\r
+\r
+cntlb0 equ IOBASE+02h ;ASCI Control Register B Channel 0\r
+cntlb1 equ IOBASE+03h ;ASCI Control Register B Channel 1\r
+ b2m MPBT,7 ;Multiprocessor Bit Transmit\r
+ b2m MP,6 ;Multiprocessor Mode\r
+ b2m CTS,5 ;Clear to Send\r
+ b2m PS,5 ;Prescale\r
+ b2m PEO,4 ;Parity Even Odd\r
+ b2m DR,3 ;Divede Ratio\r
+ b2m SS2,2 ;Source/Speed Select 2,1,0\r
+ b2m SS1,1 ;\r
+ b2m SS0,0 ;\r
+\r
+stat0 equ IOBASE+04h ;ASCI Status Channel 0\r
+stat1 equ IOBASE+05h ;ASCI Status Channel 1\r
+ b2m RDRF,7 ;Receive Data Register Full\r
+ b2m OVRN,6 ;Overrun Error\r
+ b2m PERR,5 ;Parity Error (M80: PE conflicts with JP/CALL cc)\r
+ b2m FE,4 ;Framing Error\r
+ b2m RIE,3 ;Receive Interrupt Enable\r
+ b2m DCD0,2 ;Data Carrier Detect (Ch 0)\r
+ b2m CTS1E,2 ;Clear To Send (Ch 1)\r
+ b2m TDRE,1 ;Transmit Data Register Empty\r
+ b2m TIE,0 ;Transmit Interrupt Enable\r
+\r
+tdr0 equ IOBASE+06h ;ASCI Transmit Data\r
+tdr1 equ IOBASE+07h ;ASCI Transmit Data\r
+rdr0 equ IOBASE+08h ;ASCI Receive Data\r
+rdr1 equ IOBASE+09h ;ASCI Receive Data\r
+\r
+cntr equ IOBASE+0Ah ;CSI/O Control Register\r
+trdr equ IOBASE+0Bh ;CSI/O Transmit/Receive Data Register\r
+\r
+tmdr0l equ IOBASE+0Ch ;Timer Data Register Channel 0\r
+tmdr0h equ IOBASE+0Dh ;\r
+rldr0l equ IOBASE+0Eh ;Timer Reload Register Channel 0\r
+rldr0h equ IOBASE+0Fh ;\r
+tcr equ IOBASE+10h ;Timer Control Register\r
+ b2m TIF1,7 ;Timer Interrupt Flag\r
+ b2m TIF0,6 ;\r
+ b2m TIE1,5 ;Timer Interrupt Enable\r
+ b2m TIE0,4 ;\r
+ b2m TOC1,3 ;Timer Output Control\r
+ b2m TOC0,2 ;\r
+ b2m TDE1,1 ;Timer Down Count Enable\r
+ b2m TDE0,0 ;\r
+\r
+\r
+asext0 equ IOBASE+12h ;ASCI Extension Control Register\r
+asext1 equ IOBASE+13h ;ASCI Extension Control Register\r
+ b2m DCD0DIS,6 ;DCD0 Disable\r
+ b2m CTS0DIS,5 ;CTS0 Disable\r
+ b2m X1,4 ;CKA * 1 Clock/Samle Rate Divider\r
+ b2m BRGMOD,3 ;BRG Mode (Baud rate generator)\r
+ b2m BREAKEN,2 ;Break Enable\r
+ b2m BREAK,1 ;Break detected\r
+ b2m SENDBREAK,0 ;Send Break\r
+\r
+tmdr1l equ IOBASE+14h ;Timer Data Register Channel 1\r
+tmdr1h equ IOBASE+15h ;\r
+rldr1l equ IOBASE+16h ;Timer Reload Register Channel 1\r
+rldr1h equ IOBASE+17h ;\r
+\r
+frc equ IOBASE+18h ;Free Running Counter\r
+\r
+astc0l equ IOBASE+1Ah ;ASCI Time Constant Register 0\r
+astc0h equ IOBASE+1Bh ;\r
+astc1l equ IOBASE+1Ch ;ASCI Time Constant Register 1\r
+astc1h equ IOBASE+1Dh ;\r
+\r
+cmr equ IOBASE+1Eh ;Clock Mutiplier Register\r
+ b2m X2CM,7 ;X2 Clock Multiplier\r
+ b2m LNC,6 ;Low Noise Crystal\r
+\r
+ccr equ IOBASE+1Fh ;CPU Control Register\r
+ b2m NCD 7 ;No Clock Divide\r
+\r
+sar0l equ IOBASE+20h ;DMA Src Adr Register Channel 0\r
+sar0h equ IOBASE+21h ;\r
+sar0b equ IOBASE+22h ;\r
+dar0l equ IOBASE+23h ;DMA Dst Adr Register Channel 0\r
+dar0h equ IOBASE+24h ;\r
+dar0b equ IOBASE+25h ;\r
+bcr0l equ IOBASE+26h ;DMA Byte Count Register Channel 0\r
+bcr0h equ IOBASE+27h ;\r
+\r
+mar1l equ IOBASE+28h ;DMA Memory Address Register Channel 1\r
+mar1h equ IOBASE+29h ;\r
+mar1b equ IOBASE+2Ah ;\r
+iar1l equ IOBASE+2Bh ;DMA I/O Address Register Channel 1\r
+iar1h equ IOBASE+2Ch ;\r
+iar1b equ IOBASE+2Dh ;\r
+ b2m ALTE,7 ;Alternating Chnnels\r
+ b2m ALTC,6 ;Currently selected DMA Channel when Bit7=1\r
+ b2m REQ1SEL2,2 ;\r
+ b2m REQ1SEL1,1 ;\r
+ b2m REQ1SEL0,0 ;\r
+\r
+bcr1l equ IOBASE+2Eh ;DMA Byte Count Register Channel 1\r
+bcr1h equ IOBASE+2Fh ;\r
+\r
+dstat equ IOBASE+30h ;DMA Status Register\r
+ b2m DE1,7 ;DMA enable ch 1,0\r
+ b2m DE0,6 ;\r
+ b2m NDWE1,5 ;DMA Enable Bit Write Enable 1,0\r
+ b2m NDWE0,4 ;\r
+ b2m DIE1,3 ;DMA Interrupt Enable 1,0\r
+ b2m DIE0,2 ;\r
+ b2m DME,0 ;DMA Master enable\r
+\r
+dmode equ IOBASE+31h ;DMA Mode Register\r
+ b2m DM1,5 ;Ch 0 Destination Mode 1,0\r
+ b2m DM0,4 ;\r
+ b2m SM1,3 ;Ch 0 Source Mode 1,0\r
+ b2m SM0,2 ;\r
+ b2m MMOD,1 ;Memory MODE select (0=cycle steel/1=burst)\r
+\r
+dcntl equ IOBASE+32h ;DMA/WAIT Control\r
+ b2m MWI1,7 ;Memory Wait Insertion\r
+ b2m MWI0,6 ;\r
+ b2m IWI1,5 ;I/O Wait Insertion\r
+ b2m IWI0,4 ;\r
+ b2m DMS1,3 ;DREQi Select (Edge/Level)\r
+ b2m DMS0,2 ;\r
+ b2m DIMA1,1 ;DMA Ch1 I/O Memory Mode Select\r
+ b2m DIMA0,0\r
+M_MWI equ M_MWI1 + M_MWI0\r
+M_IWI equ M_IWI1 + M_IWI0\r
+\r
+il equ IOBASE+33h ;Interrupt Vector Low Register\r
+itc equ IOBASE+34h ;INT/TRAP Control Register\r
+ b2m TRAP,7 ;Trap\r
+ b2m UFO,6 ;Unidentified Fetch Object\r
+ b2m ITE2,2 ;/INT Enable 2,1,0\r
+ b2m ITE1,1 ;\r
+ b2m ITE0,0 ;\r
+\r
+rcr equ IOBASE+36h ;Refresh Control Register\r
+ b2m REFE,7 ;Refresh Enable\r
+ b2m REFW,6 ;Refresh Wait State\r
+ b2m CYC1,1 ;Cycle select\r
+ b2m CYC0,0 ;\r
+\r
+cbr equ IOBASE+38h ;MMU Common Base Register\r
+bbr equ IOBASE+39h ;MMU Bank Base Register\r
+cbar equ IOBASE+3Ah ;MMU Common/Bank Register\r
+\r
+omcr equ IOBASE+3Eh ;Operation Mode Control Register\r
+ b2m M1E,7 ;M1 Enable\r
+ b2m M1TE,6 ;M1 Temporary Enable\r
+ b2m IOC,5 ;I/O Compatibility\r
+\r
+icr equ IOBASE+3Fh ;I/O Control Register\r
+ b2m IOSTP,5 ;I/O Stop\r
+;\r
+; Interrupt Vectors\r
+;\r
+\r
+IV$INT1 equ 0 ;/INT1 (highest priority)\r
+IV$INT2 equ 2 ;/INT2\r
+IV$PRT0 equ 4 ;PRT channel 0\r
+IV$PRT1 equ 6 ;PRT channel 1\r
+IV$DMA0 equ 8 ;DMA channel 0\r
+IV$DMA1 equ 10 ;DMA channel 1\r
+IV$CSIO equ 12 ;CSI/O\r
+IV$ASCI0 equ 14 ;ASCI channel 0\r
+IV$ASCI1 equ 16 ;ASCI channel 1 (lowest priority)\r
+\r
+ .list\r
projects / z180-stamp-cpm3.git / commitdiff