[z180-stamp.git] / avr / z80-if.c

/**
 *
 * Pin assignments
 *
 * | Z180-Sig	|   AVR-Port	| Dir	|   Special Function	|
 * +------------+---------------+-------+-----------------------+
 * |	A0	| PA 	0	|  O	|			|
 * |	A1	| PA 	1	|  O	|			|
 * |	A2	| PA 	2	|  O	|			|
 * |	A3	| PA 	3	|  O	|			|
 * |	A4	| PA 	4	|  O	|			|
 * |	A5	| PA 	5	|  O	|			|
 * |	A6	| PA 	6	|  O	|			|
 * |	A7	| PA 	7	|  O	|			|
 * |	A8	| PC 	0	|  O	|			|
 * |	A9	| PC 	1	|  O	|			|
 * |	A10	| PC 	2	|  O	|			|
 * |	A11	| PC 	3	|  O	|			|
 * |	A12	| PC 	4	|  O	|			|
 * |	A13	| PC 	5	|  O	|			|
 * |	A14	| PC 	6	|  O	|			|
 * |	A15	| PC 	7	|  O	|			|
 * |	A16	| PE 	2	|  O	|			|
 * |	A17	| PE 	3	|  O	|			|
 * |	A18	| PE 	4	|  O	|			|
 * |	D0	| PF 	0	|  I/O	|			|
 * |	D1	| PF 	1	|  I/O	|			|
 * |	D2	| PF 	2	|  I/O	|			|
 * |	D3	| PF 	3	|  I/O	|			|
 * |	D4	| PF 	4	|  I/O	|			|
 * |	D5	| PF 	5	|  I/O	|			|
 * |	D6	| PF 	6	|  I/O	|			|
 * |	D7	| PF 	7	|  I/O	|			|
 * |	RD	| PD 	3	|  O	|			|
 * |	WR	| PD 	2	|  O	|			|
 * |	MREQ	| PD 	4	|  O	|			|
 * |	RST	| PD 	5	|  O	|			|
 * |	BUSREQ	| PD 	7	|  O	|			|
 * |	BUSACK	| PD 	6	|  I	|			|
 * |	IOCS1	| PE 	5	|  I	|			|
 * |*	HALT	| P 		|	|			|
 * |*	NMI	| P 		|	|			|
 * |		| P 		|  	|			|
 * |		| P 		|  	|  af1	 USART1_TX	|
 * |		| P 		|  	|  af1	 USART1_RX	|
 * |		| P 		|JTDI	|  remap SPI1_NSS'	|
 * |		| P 		|JTDO	|  remap SPI1_SCK'	|
 * |		| P 		|JTRST	|  remap SPI1_MISO'	|
 * |		| P 		|	|  remap SPI1_MOSI'	|
 * |		| P 		|	|  af1	 OSC32		|
 * |		| P 		|	|  af1	 OSC32		|


 */

#include <avr/io.h>
#include <util/delay.h>
#include <util/atomic.h>
#include <stdio.h>
#include "debug.h"
#include "z80-if.h"


/* Number of array elements */
#define NELEMS(x)  (sizeof x/sizeof *x)


#define CONCAT(x,y) x ## y
#define EVALUATOR(x,y)  CONCAT(x,y)

#define GPIO_(X)	CONCAT(GPIO, X)

struct bits {
  uint8_t b0:1;
  uint8_t b1:1;
  uint8_t b2:1;
  uint8_t b3:1;
  uint8_t b4:1;
  uint8_t b5:1;
  uint8_t b6:1;
  uint8_t b7:1;
} __attribute__((__packed__));

#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)


#define P_ZCLK		PORTB
#define ZCLK		7
#define DDR_ZCLK	DDRB
#define P_MREQ		PORTD
#define MREQ		4
#define DDR_MREQ	DDRD
#define P_RD		PORTD
#define RD		3
#define P_WR		PORTD
#define WR		2
#define P_BUSREQ	PORTD
#define BUSREQ		7
#define DDR_BUSREQ	DDRD
#define P_BUSACK	PORTD
#define PIN_BUSACK	PIND
#define BUSACK		6
#define DDR_BUSACK	DDRD
//#define P_HALT		PORTA
//#define HALT		12
#define P_IOCS1		PORTE
#define IOCS1		5
#define DDR_IOCS1		DDRE
//#define P_NMI		PORTB
//#define NMI		7
#define P_RST		PORTD
#define DDR_RST		DDRD
#define RST		5


#define P_DB		PORTF
#define PIN_DB		PINF
#define DDR_DB		DDRF

#define P_ADL		PORTA
#define P_ADH		PORTC
#define P_ADB		PORTE
#define PIN_ADB		PINE
#define DDR_ADL		DDRA
#define DDR_ADH		DDRC
#define DDR_ADB		DDRE

#define ADB_WIDTH	3
#define ADB_SHIFT	2
//#define ADB_PORT	PORTE


#define Z80_O_ZCLK	SBIT(P_ZCLK, 7)
#define	Z80_O_MREQ	SBIT(P_MREQ, 4)
#define Z80_O_RD	SBIT(P_RD, 3)
#define Z80_O_WR	SBIT(P_WR, 2)
#define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI	SBIT(P_NMI, )
#define Z80_O_RST	SBIT(P_RST, 5)
#define Z80_I_BUSACK	SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT	SBIT(P_HALT, )


#define MASK(n)	((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))

#define LOWSPEED	50000


typedef union {
	uint32_t l;
	uint16_t w[2];
	uint8_t b[4];
} addr_t;


static zstate_t zstate;

/*--------------------------------------------------------------------------*/

static
uint8_t is_lowspeed()
{
	return (TCCR1B & 7) < 2 &&
		OCR1A > (F_CPU / 2 / LOWSPEED);
}

static
void z80_setup_clock(void)
{
	/* ZCLK: Output and low */
	DDR_ZCLK |= _BV(ZCLK);
	Z80_O_ZCLK = 0;

	DDRB  |= _BV(6);	/* Debug */
	PORTB |= _BV(6);	/* Debug */

	PRR0 &= ~_BV(PRTIM1);

	/* Timer1: CTC: Toggle OC1C on compare match */
	OCR1A =  0;
	OCR1C =  0;
	TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
	TCCR1B = (0b01 << WGM12)  | (0b001 << CS10);
}


int z80_clock_set(unsigned long freq)
{
	unsigned long ocrval = F_CPU  / freq / 2;
	uint8_t prescale = 0;

	while (ocrval > (1L<<16)) {
		prescale++;
		if (prescale < 3)
			ocrval = ocrval / 8;
		else
			ocrval = ocrval /  4;
	}

	if ((ocrval == 0) || (prescale > 4))
		return -1;

	ocrval -= 1;

	PINB |= _BV(6);		/* Debug */

	/* Stop Timer */
	TCCR1B = (0b01 << WGM12)  | (0b000 << CS10);
	TCNT1 = 0;

	OCR1A =  ocrval;
	OCR1CL =  ocrval;
	TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
	TCCR1B = (0b01 << WGM12)  | ((prescale+1) << CS10);

	if (ocrval == 0)
		ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
			TCNT1 = 0xFFFF;
		}

	PINB |= _BV(6);		/* Debug */

	return 0;
}

uint32_t z80_clock_get(void)
{
	uint32_t count = (OCR1A + 1L) * 2;
	uint8_t pre = (TCCR1B & 7) - 1;

	while (pre) {
		if (pre > 2)
			count *= 4;
		else
			count *= 8;
		pre--;
	}

	return F_CPU/count;
}


static void z80_addrbus_set_tristate(void)
{
	/* /MREQ, /RD, /WR: Input, no pullup */
	DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
	Z80_O_MREQ = 0;
	Z80_O_RD = 0;
	Z80_O_WR = 0;

	P_ADL = 0;
	DDR_ADL = 0;
	P_ADH = 0;
	DDR_ADH = 0;
	PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_addrbus_set_active(void)
{
	/* /MREQ, /RD, /WR: Output and high */
	Z80_O_MREQ = 1;
	Z80_O_RD = 1;
	Z80_O_WR = 1;
	DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);

	DDR_ADL = 0xff;
	DDR_ADH = 0xff;
	DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_dbus_set_in(void)
{
	DDR_DB = 0;
	P_DB = 0;
}


static void z80_dbus_set_out(void)
{
	DDR_DB = 0xff;
}


static void z80_reset_pulse(void)
{
	Z80_O_RST = 0;
	_delay_us(10);
	Z80_O_RST = 1;
}


void z80_setup_bus(void)
{
	z80_setup_clock();

	/* /ZRESET: Output and low */
	Z80_O_RST = 0;
	DDR_RST |= _BV(RST);

	/* /BUSREQ: Output and high */
	Z80_O_BUSREQ = 1;
	DDR_BUSREQ |= _BV(BUSREQ);

	/* /BUSACK: Input, no pullup */
	DDR_BUSACK &= ~_BV(BUSACK);
	P_BUSACK &= ~_BV(BUSACK);

	/* /IOCS1: Input, no pullup */
	DDR_IOCS1 &= ~_BV(IOCS1);
	P_IOCS1 &= ~_BV(IOCS1);

	z80_addrbus_set_tristate();
	z80_dbus_set_in();

	zstate = RESET;
}


zstate_t z80_bus_state(void)
{
	return zstate;
}


static void z80_busreq_hpulse(void)
{
	z80_dbus_set_in();
	z80_addrbus_set_tristate();

	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
		Z80_O_BUSREQ = 1;
		Z80_O_BUSREQ = 1;	/* 2 AVR clock cycles */
		Z80_O_BUSREQ = 0;	/* 2 AVR clock cycles */
	}

	if (zstate & ZST_ACQUIRED) {
		while(Z80_I_BUSACK == 1)
			;
		z80_addrbus_set_active();
	}
}


/*

 +              |		|		|		|		|
    +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
       +        |		|		|		|		|
          +     |	0	|	1	|	2	|	3	|
Event        +  |		|		|		|		|
----------------+---------------+---------------+---------------+---------------+
		|		|		|		|		|
Reset		|	0	|	0	|	0	|	0	|
		|		|		|		|		|
		|		|		|		|		|
Request		|	1	|		|	3	|		|
		|		|		|		|		|
		|		|		|		|		|
Release		|		|	0	|		|	2	|
		|		|		|		|		|
		|		|		|		|		|
Run		|	2	|	3	|		|		|
		|		|		|		|		|
		|		|		|		|		|
Restart		|		|		|	2	|	3	|
		|		|		|		|		|
		|		|		|		|		|
M_Cycle		|		|		|		|	3	|
		|		|		|		|		|
		|		|		|		|		|
*/

zstate_t z80_bus_cmd(bus_cmd_t cmd)
{
	switch (cmd) {

	case Reset:
		z80_dbus_set_in();
		z80_addrbus_set_tristate();
		Z80_O_RST = 0;
		Z80_O_BUSREQ = 1;
		zstate = RESET;
		break;

	case Request:
		switch (zstate) {
		case RESET:
			Z80_O_BUSREQ = 0;
			Z80_O_RST = 1;
			while(Z80_I_BUSACK == 1)
				;
			z80_addrbus_set_active();
			zstate = RESET_AQRD;
			break;

		case RUNNING:
			Z80_O_BUSREQ = 0;
			while(Z80_I_BUSACK == 1)
				;
			z80_addrbus_set_active();
			zstate = RUNNING_AQRD;
			break;

		default:
			break;
		}
		break;

	case Release:
		switch (zstate) {
		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			Z80_O_RST = 0;
			Z80_O_BUSREQ = 1;
			zstate = RESET;
			break;
		case RUNNING_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			Z80_O_BUSREQ = 1;
			zstate = RUNNING;
			break;
		default:
			break;
		}
		break;

	case Run:
		switch (zstate) {
		case RESET:
			Z80_O_RST = 1;
			zstate = RUNNING;
			break;

		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			z80_reset_pulse();
			z80_addrbus_set_active();
			zstate = RUNNING_AQRD;
			break;
		default:
			break;
		}
		break;

	case Restart:
		switch (zstate) {
		case RUNNING:
		case RUNNING_AQRD:
			z80_reset_pulse();
			break;
		default:
			break;
		}
		break;

	case M_Cycle:
		switch (zstate) {
		case RUNNING_AQRD:
			z80_busreq_hpulse();
			break;
		default:
			break;
		}
	}
	return zstate;
}


/*--------------------------------------------------------------------------*/

static
//inline __attribute__ ((always_inline))
void z80_setaddress(uint32_t addr)
{
	addr_t x; x.l = addr;

	P_ADL = x.b[0];
	P_ADH = x.b[1];
	PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
}

void z80_write(uint32_t addr, uint8_t data)
{
	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_out();
	P_DB = data;
	P_DB = data;
	Z80_O_WR = 0;
	Z80_O_WR = 0;
	Z80_O_WR = 1;
	Z80_O_MREQ = 1;
}

uint8_t z80_read(uint32_t addr)
{
	uint8_t data;

	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	data = PIN_DB;
	Z80_O_RD = 1;
	Z80_O_MREQ = 1;

	return data;
}


void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
{
	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(addr++);
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

/*
  0179'                         rx.bs_mask:	ds	1		; (buf_len - 1)
  017A'                         rx.in_idx:	ds	1		;
  017B'                         rx.out_idx:	ds	1		;
  017C'                         rx.buf:		ds	rx.buf_len	;
  018B'                         rx.buf_end	equ	$-1		; last byte (start+len-1)

  018C'                         tx.bs_mask:	ds	1		; (buf_len - 1)
  018D'                         tx.in_idx:	ds	1		;
  018E'                         tx.out_idx:	ds	1		;
  018F'                         tx.buf:		ds	tx.buf_len 	;
  019E'                         tx.buf_end	equ	$-1		; last byte
*/


typedef struct __attribute__((packed)) {
	uint8_t mask;
	uint8_t in_idx;
	uint8_t out_idx;
	uint8_t buf[];
} zfifo_t;


#define FIFO_BUFSIZE_MASK	-3
#define FIFO_INDEX_IN		-2
#define FIFO_INDEX_OUT		-1


static struct {
	uint32_t base;
	uint8_t idx_out,
		idx_in,
		mask;
	} fifo_dsc[NUM_FIFOS];


void z80_memfifo_init(const fifo_t f, uint32_t adr)
{

DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);

	fifo_dsc[f].base = adr;

	z80_bus_cmd(Request);

	fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
	fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
	fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);

	z80_bus_cmd(Release);
}


int z80_memfifo_is_empty(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {

		uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
		uint8_t idx;

		z80_bus_cmd(Request);
		idx = z80_read(adr);
		z80_bus_cmd(Release);
		rc = idx == fifo_dsc[f].idx_out;
	}

	return rc;
}

int z80_memfifo_is_full(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {
		z80_bus_cmd(Request);
		rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
			== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
	return rc;
}

uint8_t z80_memfifo_getc(const fifo_t f)
{
	uint8_t rc, idx;

	while (z80_memfifo_is_empty(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_out;
	rc = z80_read(fifo_dsc[f].base+idx);
	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	z80_bus_cmd(Release);

	return rc;
}


void z80_memfifo_putc(fifo_t f, uint8_t val)
{
	int idx;

	while (z80_memfifo_is_full(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_in;
	z80_write(fifo_dsc[f].base+idx, val);
	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
	z80_bus_cmd(Release);
}

/*--------------------------------------------------------------------------*/
/*
	TODO: Rewrite msg_fifo routines for AVR
*/

static struct {
	uint32_t base;
	//uint8_t  idx_out, idx_in;
	uint16_t count;
	uint8_t  buf[256];
	} msg_fifo;

/*--------------------------------------------------------------------------*/

#if 0

static void tim1_setup(void)
{
	RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
	RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;

	TIM1_CR1 = 0;

	TIM1_SMCR = 0
	/*	| TIM_SMCR_ETP			*/
	/*	| TIM_SMCR_ETF_CK_INT_N_2	*/
		| TIM_SMCR_TS_ETRF
		| TIM_SMCR_SMS_OFF
		;

	TIM1_DIER = TIM_DIER_TDE;


	TIM1_CCMR1 = 0
		| TIM_CCMR1_OC1M_FORCE_LOW
		| TIM_CCMR1_CC1S_OUT;

	TIM1_SMCR |= TIM_SMCR_SMS_TM;
}

#endif

/*--------------------------------------------------------------------------*/

void z80_setup_msg_fifo(void)
{
//	gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
//		GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);

//...

//	msg_fifo.count = NELEMS(msg_fifo.buf);
	msg_fifo.count = 0;
	msg_fifo.base = 0;

}


void z80_init_msg_fifo(uint32_t addr)
{

DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);

	z80_bus_cmd(Request);
	z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
	z80_bus_cmd(Release);
	msg_fifo.base = addr;
}


int z80_msg_fifo_getc(void)
{
	int c = -1;

#if 0
	if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
		c = msg_fifo.buf[msg_fifo.count];
		if (++msg_fifo.count == NELEMS(msg_fifo.buf))
			msg_fifo.count = 0;

		if (msg_fifo.base != 0) {
			z80_bus_cmd(Request);
			z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
			z80_bus_cmd(Release);
		}
	}
#endif

	return c;
}
Commit	Line	Data
0c5890bb L	1	/**
	2	*
	3	* Pin assignments
	4	*
72f58822	5	* \| Z180-Sig \| AVR-Port \| Dir \| Special Function \|
0c5890bb L	6	* +------------+---------------+-------+-----------------------+
	7	* \| A0 \| PA 0 \| O \| \|
	8	* \| A1 \| PA 1 \| O \| \|
	9	* \| A2 \| PA 2 \| O \| \|
	10	* \| A3 \| PA 3 \| O \| \|
	11	* \| A4 \| PA 4 \| O \| \|
	12	* \| A5 \| PA 5 \| O \| \|
	13	* \| A6 \| PA 6 \| O \| \|
	14	* \| A7 \| PA 7 \| O \| \|
	15	* \| A8 \| PC 0 \| O \| \|
	16	* \| A9 \| PC 1 \| O \| \|
	17	* \| A10 \| PC 2 \| O \| \|
	18	* \| A11 \| PC 3 \| O \| \|
	19	* \| A12 \| PC 4 \| O \| \|
	20	* \| A13 \| PC 5 \| O \| \|
	21	* \| A14 \| PC 6 \| O \| \|
	22	* \| A15 \| PC 7 \| O \| \|
	23	* \| A16 \| PE 2 \| O \| \|
	24	* \| A17 \| PE 3 \| O \| \|
	25	* \| A18 \| PE 4 \| O \| \|
	26	* \| D0 \| PF 0 \| I/O \| \|
	27	* \| D1 \| PF 1 \| I/O \| \|
	28	* \| D2 \| PF 2 \| I/O \| \|
	29	* \| D3 \| PF 3 \| I/O \| \|
	30	* \| D4 \| PF 4 \| I/O \| \|
	31	* \| D5 \| PF 5 \| I/O \| \|
	32	* \| D6 \| PF 6 \| I/O \| \|
	33	* \| D7 \| PF 7 \| I/O \| \|
	34	* \| RD \| PD 3 \| O \| \|
	35	* \| WR \| PD 2 \| O \| \|
	36	* \| MREQ \| PD 4 \| O \| \|
	37	* \| RST \| PD 5 \| O \| \|
	38	* \| BUSREQ \| PD 7 \| O \| \|
	39	* \| BUSACK \| PD 6 \| I \| \|
	40	* \| IOCS1 \| PE 5 \| I \| \|
	41	* \|* HALT \| P \| \| \|
	42	* \|* NMI \| P \| \| \|
	43	* \| \| P \| \| \|
	44	* \| \| P \| \| af1 USART1_TX \|
	45	* \| \| P \| \| af1 USART1_RX \|
	46	* \| \| P \|JTDI \| remap SPI1_NSS' \|
	47	* \| \| P \|JTDO \| remap SPI1_SCK' \|
	48	* \| \| P \|JTRST \| remap SPI1_MISO' \|
	49	* \| \| P \| \| remap SPI1_MOSI' \|
	50	* \| \| P \| \| af1 OSC32 \|
	51	* \| \| P \| \| af1 OSC32 \|
	52
	53
	54	*/
	55
	56	#include <avr/io.h>
	57	#include <util/delay.h>
f338df2a	58	#include <util/atomic.h>
0c5890bb L	59	#include <stdio.h>
	60	#include "debug.h"
	61	#include "z80-if.h"
	62
	63
	64	/* Number of array elements */
	65	#define NELEMS(x) (sizeof x/sizeof *x)
	66
	67
	68	#define CONCAT(x,y) x ## y
	69	#define EVALUATOR(x,y) CONCAT(x,y)
	70
	71	#define GPIO_(X) CONCAT(GPIO, X)
	72
	73	struct bits {
	74	uint8_t b0:1;
	75	uint8_t b1:1;
	76	uint8_t b2:1;
	77	uint8_t b3:1;
	78	uint8_t b4:1;
	79	uint8_t b5:1;
	80	uint8_t b6:1;
	81	uint8_t b7:1;
	82	} __attribute__((__packed__));
	83
	84	#define SBIT(port,pin) (((volatile struct bits)&port).b##pin)
	85
	86
54678798 L	87	#define P_ZCLK PORTB
	88	#define ZCLK 7
	89	#define DDR_ZCLK DDRB
0c5890bb L	90	#define P_MREQ PORTD
	91	#define MREQ 4
	92	#define DDR_MREQ DDRD
	93	#define P_RD PORTD
	94	#define RD 3
	95	#define P_WR PORTD
	96	#define WR 2
	97	#define P_BUSREQ PORTD
	98	#define BUSREQ 7
	99	#define DDR_BUSREQ DDRD
	100	#define P_BUSACK PORTD
9b6b4b31	101	#define PIN_BUSACK PIND
0c5890bb L	102	#define BUSACK 6
	103	#define DDR_BUSACK DDRD
	104	//#define P_HALT PORTA
	105	//#define HALT 12
	106	#define P_IOCS1 PORTE
	107	#define IOCS1 5
	108	#define DDR_IOCS1 DDRE
	109	//#define P_NMI PORTB
	110	//#define NMI 7
	111	#define P_RST PORTD
	112	#define DDR_RST DDRD
	113	#define RST 5
	114
	115
	116	#define P_DB PORTF
	117	#define PIN_DB PINF
	118	#define DDR_DB DDRF
	119
	120	#define P_ADL PORTA
	121	#define P_ADH PORTC
	122	#define P_ADB PORTE
	123	#define PIN_ADB PINE
9b6b4b31 L	124	#define DDR_ADL DDRA
9b6b4b31 L	125	#define DDR_ADH DDRC
0c5890bb L	126	#define DDR_ADB DDRE
	127
	128	#define ADB_WIDTH 3
	129	#define ADB_SHIFT 2
	130	//#define ADB_PORT PORTE
	131
	132
54678798	133	#define Z80_O_ZCLK SBIT(P_ZCLK, 7)
0c5890bb L	134	#define Z80_O_MREQ SBIT(P_MREQ, 4)
	135	#define Z80_O_RD SBIT(P_RD, 3)
	136	#define Z80_O_WR SBIT(P_WR, 2)
	137	#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
	138	//#define Z80_O_NMI SBIT(P_NMI, )
	139	#define Z80_O_RST SBIT(P_RST, 5)
9b6b4b31	140	#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
0c5890bb L	141	//#define Z80_I_HALT SBIT(P_HALT, )
0c5890bb L	142
9b6b4b31	143
0c5890bb L	144	#define MASK(n) ((1<<(n))-1)
	145	#define SMASK(w,s) (MASK(w) << (s))
	146
04a63b0d	147	#define LOWSPEED 50000
0c5890bb L	148
0c5890bb L	149
eded7ec4 L	150	typedef union {
	151	uint32_t l;
	152	uint16_t w[2];
	153	uint8_t b[4];
	154	} addr_t;
f338df2a L	155
	156
	157	static zstate_t zstate;
eded7ec4	158
0c5890bb L	159	/--------------------------------------------------------------------------/
0c5890bb L	160
04a63b0d L	161	static
	162	uint8_t is_lowspeed()
	163	{
	164	return (TCCR1B & 7) < 2 &&
	165	OCR1A > (F_CPU / 2 / LOWSPEED);
	166	}
	167
6035a17b L	168	static
	169	void z80_setup_clock(void)
	170	{
	171	/* ZCLK: Output and low */
	172	DDR_ZCLK \|= _BV(ZCLK);
	173	Z80_O_ZCLK = 0;
	174
	175	DDRB \|= _BV(6); /* Debug */
	176	PORTB \|= _BV(6); /* Debug */
	177
	178	PRR0 &= ~_BV(PRTIM1);
	179
	180	/* Timer1: CTC: Toggle OC1C on compare match */
	181	OCR1A = 0;
	182	OCR1C = 0;
	183	TCCR1A = (0b01 << COM1C0) \| (0b00 << WGM10);
	184	TCCR1B = (0b01 << WGM12) \| (0b001 << CS10);
	185	}
0c5890bb	186
6035a17b L	187
	188	int z80_clock_set(unsigned long freq)
	189	{
	190	unsigned long ocrval = F_CPU / freq / 2;
	191	uint8_t prescale = 0;
	192
	193	while (ocrval > (1L<<16)) {
	194	prescale++;
	195	if (prescale < 3)
	196	ocrval = ocrval / 8;
	197	else
	198	ocrval = ocrval / 4;
	199	}
	200
	201	if ((ocrval == 0) \|\| (prescale > 4))
	202	return -1;
	203
	204	ocrval -= 1;
	205
	206	PINB \|= _BV(6); /* Debug */
	207
	208	/* Stop Timer */
	209	TCCR1B = (0b01 << WGM12) \| (0b000 << CS10);
	210	TCNT1 = 0;
	211
	212	OCR1A = ocrval;
	213	OCR1CL = ocrval;
	214	TCCR1A = (0b01 << COM1C0) \| (0b00 << WGM10);
	215	TCCR1B = (0b01 << WGM12) \| ((prescale+1) << CS10);
	216
04a63b0d	217	if (ocrval == 0)
6035a17b L	218	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
	219	TCNT1 = 0xFFFF;
	220	}
6035a17b L	221
	222	PINB \|= _BV(6); /* Debug */
	223
	224	return 0;
	225	}
	226
	227	uint32_t z80_clock_get(void)
	228	{
	229	uint32_t count = (OCR1A + 1L) * 2;
	230	uint8_t pre = (TCCR1B & 7) - 1;
	231
	232	while (pre) {
	233	if (pre > 2)
	234	count *= 4;
	235	else
	236	count *= 8;
	237	pre--;
6035a17b L	238	}
	239
	240	return F_CPU/count;
	241	}
	242
	243
	244
	245	static void z80_addrbus_set_tristate(void)
0c5890bb	246	{
9b6b4b31 L	247	/* /MREQ, /RD, /WR: Input, no pullup */
	248	DDR_MREQ &= ~(_BV(MREQ) \| _BV(RD) \| _BV(WR));
	249	Z80_O_MREQ = 0;
	250	Z80_O_RD = 0;
	251	Z80_O_WR = 0;
	252
0c5890bb L	253	P_ADL = 0;
	254	DDR_ADL = 0;
	255	P_ADH = 0;
	256	DDR_ADH = 0;
9b6b4b31	257	PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
0c5890bb L	258	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
	259	}
	260
54678798	261
6035a17b	262	static void z80_addrbus_set_active(void)
0c5890bb	263	{
9b6b4b31 L	264	/* /MREQ, /RD, /WR: Output and high */
	265	Z80_O_MREQ = 1;
	266	Z80_O_RD = 1;
	267	Z80_O_WR = 1;
	268	DDR_MREQ \|= _BV(MREQ) \| _BV(RD) \| _BV(WR);
	269
0c5890bb L	270	DDR_ADL = 0xff;
	271	DDR_ADH = 0xff;
	272	DDR_ADB = DDR_ADB \| (MASK(ADB_WIDTH) << ADB_SHIFT);
	273	}
	274
	275
6035a17b	276	static void z80_dbus_set_in(void)
0c5890bb L	277	{
	278	DDR_DB = 0;
	279	P_DB = 0;
	280	}
	281
62f624d3	282
6035a17b	283	static void z80_dbus_set_out(void)
0c5890bb L	284	{
	285	DDR_DB = 0xff;
	286	}
	287
62f624d3 L	288
	289	static void z80_reset_pulse(void)
	290	{
	291	Z80_O_RST = 0;
	292	_delay_us(10);
	293	Z80_O_RST = 1;
	294	}
	295
	296
0c5890bb L	297	void z80_setup_bus(void)
0c5890bb L	298	{
54678798 L	299	z80_setup_clock();
54678798 L	300
9b6b4b31	301	/* /ZRESET: Output and low */
0c5890bb L	302	Z80_O_RST = 0;
	303	DDR_RST \|= _BV(RST);
	304
9b6b4b31	305	/* /BUSREQ: Output and high */
0c5890bb L	306	Z80_O_BUSREQ = 1;
	307	DDR_BUSREQ \|= _BV(BUSREQ);
	308
9b6b4b31	309	/* /BUSACK: Input, no pullup */
0c5890bb L	310	DDR_BUSACK &= ~_BV(BUSACK);
	311	P_BUSACK &= ~_BV(BUSACK);
	312
9b6b4b31	313	/* /IOCS1: Input, no pullup */
0c5890bb L	314	DDR_IOCS1 &= ~_BV(IOCS1);
	315	P_IOCS1 &= ~_BV(IOCS1);
	316
6035a17b L	317	z80_addrbus_set_tristate();
6035a17b L	318	z80_dbus_set_in();
72f58822	319
f338df2a	320	zstate = RESET;
0c5890bb L	321	}
0c5890bb L	322
f338df2a	323
62f624d3	324	zstate_t z80_bus_state(void)
f338df2a L	325	{
	326	return zstate;
	327	}
	328
62f624d3 L	329
62f624d3 L	330	static void z80_busreq_hpulse(void)
0c5890bb	331	{
6035a17b L	332	z80_dbus_set_in();
6035a17b L	333	z80_addrbus_set_tristate();
72f58822	334
62f624d3 L	335	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
	336	Z80_O_BUSREQ = 1;
	337	Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
	338	Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
f338df2a	339	}
72f58822	340
62f624d3	341	if (zstate & ZST_ACQUIRED) {
f338df2a L	342	while(Z80_I_BUSACK == 1)
f338df2a L	343	;
6035a17b	344	z80_addrbus_set_active();
f338df2a	345	}
f338df2a L	346	}
f338df2a L	347
f338df2a L	348
f338df2a L	349	/*
f338df2a	350
62f624d3 L	351	+ \| \| \| \| \|
	352	+ State \| RESET \| RESET_AQRD \| RUNNING \| RUNNING_AQRD \|
	353	+ \| \| \| \| \|
	354	+ \| 0 \| 1 \| 2 \| 3 \|
	355	Event + \| \| \| \| \|
	356	----------------+---------------+---------------+---------------+---------------+
	357	\| \| \| \| \|
	358	Reset \| 0 \| 0 \| 0 \| 0 \|
	359	\| \| \| \| \|
	360	\| \| \| \| \|
	361	Request \| 1 \| \| 3 \| \|
	362	\| \| \| \| \|
	363	\| \| \| \| \|
	364	Release \| \| 0 \| \| 2 \|
	365	\| \| \| \| \|
	366	\| \| \| \| \|
	367	Run \| 2 \| 3 \| \| \|
	368	\| \| \| \| \|
	369	\| \| \| \| \|
	370	Restart \| \| \| 2 \| 3 \|
	371	\| \| \| \| \|
	372	\| \| \| \| \|
	373	M_Cycle \| \| \| \| 3 \|
	374	\| \| \| \| \|
	375	\| \| \| \| \|
	376	*/
f338df2a	377
62f624d3	378	zstate_t z80_bus_cmd(bus_cmd_t cmd)
f338df2a	379	{
62f624d3	380	switch (cmd) {
f338df2a	381
62f624d3	382	case Reset:
6035a17b L	383	z80_dbus_set_in();
6035a17b L	384	z80_addrbus_set_tristate();
f338df2a	385	Z80_O_RST = 0;
62f624d3 L	386	Z80_O_BUSREQ = 1;
62f624d3 L	387	zstate = RESET;
f338df2a L	388	break;
f338df2a L	389
62f624d3 L	390	case Request:
	391	switch (zstate) {
	392	case RESET:
	393	Z80_O_BUSREQ = 0;
	394	Z80_O_RST = 1;
	395	while(Z80_I_BUSACK == 1)
	396	;
6035a17b	397	z80_addrbus_set_active();
62f624d3 L	398	zstate = RESET_AQRD;
	399	break;
	400
	401	case RUNNING:
	402	Z80_O_BUSREQ = 0;
	403	while(Z80_I_BUSACK == 1)
	404	;
6035a17b	405	z80_addrbus_set_active();
62f624d3 L	406	zstate = RUNNING_AQRD;
	407	break;
	408
	409	default:
	410	break;
	411	}
f338df2a	412	break;
f338df2a	413
62f624d3 L	414	case Release:
	415	switch (zstate) {
	416	case RESET_AQRD:
6035a17b L	417	z80_dbus_set_in();
6035a17b L	418	z80_addrbus_set_tristate();
62f624d3 L	419	Z80_O_RST = 0;
	420	Z80_O_BUSREQ = 1;
	421	zstate = RESET;
	422	break;
	423	case RUNNING_AQRD:
6035a17b L	424	z80_dbus_set_in();
6035a17b L	425	z80_addrbus_set_tristate();
62f624d3 L	426	Z80_O_BUSREQ = 1;
	427	zstate = RUNNING;
	428	break;
	429	default:
	430	break;
	431	}
	432	break;
f338df2a	433
62f624d3 L	434	case Run:
	435	switch (zstate) {
	436	case RESET:
	437	Z80_O_RST = 1;
	438	zstate = RUNNING;
	439	break;
	440
	441	case RESET_AQRD:
6035a17b L	442	z80_dbus_set_in();
6035a17b L	443	z80_addrbus_set_tristate();
62f624d3	444	z80_reset_pulse();
6035a17b	445	z80_addrbus_set_active();
62f624d3 L	446	zstate = RUNNING_AQRD;
	447	break;
	448	default:
	449	break;
	450	}
	451	break;
f338df2a	452
62f624d3 L	453	case Restart:
	454	switch (zstate) {
	455	case RUNNING:
	456	case RUNNING_AQRD:
	457	z80_reset_pulse();
	458	break;
	459	default:
	460	break;
	461	}
	462	break;
f338df2a	463
62f624d3 L	464	case M_Cycle:
	465	switch (zstate) {
	466	case RUNNING_AQRD:
	467	z80_busreq_hpulse();
	468	break;
	469	default:
	470	break;
	471	}
f338df2a	472	}
62f624d3	473	return zstate;
9b6b4b31 L	474	}
9b6b4b31 L	475
62f624d3	476
9b6b4b31 L	477	/--------------------------------------------------------------------------/
9b6b4b31 L	478
54678798	479	static
9b6b4b31 L	480	//inline __attribute__ ((always_inline))
	481	void z80_setaddress(uint32_t addr)
	482	{
	483	addr_t x; x.l = addr;
	484
	485	P_ADL = x.b[0];
	486	P_ADH = x.b[1];
	487	PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
0c5890bb L	488	}
	489
	490	void z80_write(uint32_t addr, uint8_t data)
	491	{
	492	z80_setaddress(addr);
	493	Z80_O_MREQ = 0;
6035a17b	494	z80_dbus_set_out();
9b6b4b31 L	495	P_DB = data;
	496	P_DB = data;
	497	Z80_O_WR = 0;
0c5890bb L	498	Z80_O_WR = 0;
	499	Z80_O_WR = 1;
	500	Z80_O_MREQ = 1;
	501	}
	502
	503	uint8_t z80_read(uint32_t addr)
	504	{
	505	uint8_t data;
	506
	507	z80_setaddress(addr);
	508	Z80_O_MREQ = 0;
6035a17b	509	z80_dbus_set_in();
0c5890bb L	510	Z80_O_RD = 0;
0c5890bb L	511	Z80_O_RD = 0;
9b6b4b31	512	Z80_O_RD = 0;
0c5890bb L	513	data = PIN_DB;
	514	Z80_O_RD = 1;
	515	Z80_O_MREQ = 1;
	516
	517	return data;
	518	}
	519
	520
	521	void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
	522	{
6035a17b	523	z80_dbus_set_out();
0c5890bb L	524	Z80_O_MREQ = 0;
	525	while(length--) {
	526	z80_setaddress(addr++);
	527	P_DB = data;
9b6b4b31 L	528	P_DB = data;
9b6b4b31 L	529	Z80_O_WR = 0;
0c5890bb L	530	Z80_O_WR = 0;
	531	Z80_O_WR = 1;
	532	}
	533	Z80_O_MREQ = 1;
	534	}
	535
9b6b4b31	536	void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
0c5890bb L	537	{
0c5890bb L	538	uint8_t data;
54678798	539
6035a17b	540	z80_dbus_set_out();
0c5890bb L	541	Z80_O_MREQ = 0;
	542	while(length--) {
	543	z80_setaddress(dest++);
	544	data = *src++;
	545	P_DB = data;
9b6b4b31 L	546	P_DB = data;
9b6b4b31 L	547	Z80_O_WR = 0;
0c5890bb L	548	Z80_O_WR = 0;
	549	Z80_O_WR = 1;
	550	}
	551	Z80_O_MREQ = 1;
	552	}
	553
	554	/*
	555	0179' rx.bs_mask: ds 1 ; (buf_len - 1)
	556	017A' rx.in_idx: ds 1 ;
	557	017B' rx.out_idx: ds 1 ;
	558	017C' rx.buf: ds rx.buf_len ;
	559	018B' rx.buf_end equ $-1 ; last byte (start+len-1)
54678798	560
0c5890bb L	561	018C' tx.bs_mask: ds 1 ; (buf_len - 1)
	562	018D' tx.in_idx: ds 1 ;
	563	018E' tx.out_idx: ds 1 ;
	564	018F' tx.buf: ds tx.buf_len ;
	565	019E' tx.buf_end equ $-1 ; last byte
	566	*/
	567
	568
	569	typedef struct __attribute__((packed)) {
	570	uint8_t mask;
	571	uint8_t in_idx;
	572	uint8_t out_idx;
	573	uint8_t buf[];
	574	} zfifo_t;
	575
	576
	577
	578	#define FIFO_BUFSIZE_MASK -3
	579	#define FIFO_INDEX_IN -2
	580	#define FIFO_INDEX_OUT -1
	581
	582
	583	static struct {
	584	uint32_t base;
	585	uint8_t idx_out,
	586	idx_in,
	587	mask;
	588	} fifo_dsc[NUM_FIFOS];
54678798	589
0c5890bb L	590
	591	void z80_memfifo_init(const fifo_t f, uint32_t adr)
	592	{
	593
	594	DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
	595
	596	fifo_dsc[f].base = adr;
	597
62f624d3	598	z80_bus_cmd(Request);
0c5890bb L	599
	600	fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
	601	fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
	602	fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
	603
62f624d3	604	z80_bus_cmd(Release);
0c5890bb L	605	}
	606
	607
	608	int z80_memfifo_is_empty(const fifo_t f)
	609	{
	610	int rc = 1;
	611
	612	if (fifo_dsc[f].base != 0) {
	613
	614	uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
	615	uint8_t idx;
	616
62f624d3	617	z80_bus_cmd(Request);
0c5890bb	618	idx = z80_read(adr);
62f624d3	619	z80_bus_cmd(Release);
0c5890bb L	620	rc = idx == fifo_dsc[f].idx_out;
	621	}
	622
	623	return rc;
	624	}
	625
	626	int z80_memfifo_is_full(const fifo_t f)
	627	{
	628	int rc = 1;
54678798	629
0c5890bb	630	if (fifo_dsc[f].base != 0) {
62f624d3	631	z80_bus_cmd(Request);
0c5890bb L	632	rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
0c5890bb L	633	== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
62f624d3	634	z80_bus_cmd(Release);
0c5890bb L	635	}
	636	return rc;
	637	}
	638
	639	uint8_t z80_memfifo_getc(const fifo_t f)
	640	{
	641	uint8_t rc, idx;
54678798	642
0c5890bb L	643	while (z80_memfifo_is_empty(f))
	644	;
	645
62f624d3	646	z80_bus_cmd(Request);
0c5890bb L	647	idx = fifo_dsc[f].idx_out;
	648	rc = z80_read(fifo_dsc[f].base+idx);
	649	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	650	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
62f624d3	651	z80_bus_cmd(Release);
54678798	652
0c5890bb L	653	return rc;
	654	}
	655
	656
	657	void z80_memfifo_putc(fifo_t f, uint8_t val)
	658	{
	659	int idx;
54678798	660
0c5890bb L	661	while (z80_memfifo_is_full(f))
	662	;
	663
62f624d3	664	z80_bus_cmd(Request);
0c5890bb L	665	idx = fifo_dsc[f].idx_in;
	666	z80_write(fifo_dsc[f].base+idx, val);
	667	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	668	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
62f624d3	669	z80_bus_cmd(Release);
0c5890bb L	670	}
	671
	672	/--------------------------------------------------------------------------/
72f58822 L	673	/*
	674	TODO: Rewrite msg_fifo routines for AVR
	675	*/
0c5890bb L	676
	677	static struct {
	678	uint32_t base;
	679	//uint8_t idx_out, idx_in;
	680	uint16_t count;
	681	uint8_t buf[256];
	682	} msg_fifo;
	683
	684	/--------------------------------------------------------------------------/
	685
	686	#if 0
	687
	688	static void tim1_setup(void)
	689	{
	690	RCC_APB2RSTR \|= RCC_APB2RSTR_TIM1RST;
	691	RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
	692
	693	TIM1_CR1 = 0;
	694
	695	TIM1_SMCR = 0
	696	/* \| TIM_SMCR_ETP */
	697	/* \| TIM_SMCR_ETF_CK_INT_N_2 */
	698	\| TIM_SMCR_TS_ETRF
	699	\| TIM_SMCR_SMS_OFF
	700	;
	701
	702	TIM1_DIER = TIM_DIER_TDE;
	703
	704
	705	TIM1_CCMR1 = 0
	706	\| TIM_CCMR1_OC1M_FORCE_LOW
	707	\| TIM_CCMR1_CC1S_OUT;
	708
	709	TIM1_SMCR \|= TIM_SMCR_SMS_TM;
	710	}
	711
	712	#endif
	713
	714	/--------------------------------------------------------------------------/
	715
	716	void z80_setup_msg_fifo(void)
	717	{
	718	// gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
	719	// GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK \| GPIO_IOCS1);
	720
	721	//...
	722
	723	// msg_fifo.count = NELEMS(msg_fifo.buf);
	724	msg_fifo.count = 0;
	725	msg_fifo.base = 0;
	726
	727	}
	728
	729
	730	void z80_init_msg_fifo(uint32_t addr)
	731	{
	732
	733	DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
	734
62f624d3	735	z80_bus_cmd(Request);
0c5890bb	736	z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
62f624d3	737	z80_bus_cmd(Release);
0c5890bb L	738	msg_fifo.base = addr;
	739	}
	740
	741
	742	int z80_msg_fifo_getc(void)
	743	{
	744	int c = -1;
54678798	745
9b6b4b31	746	#if 0
0c5890bb L	747	if (msg_fifo.count != (NELEMS(msg_fifo.buf) /- DMA1_CNDTR4 / )) {
	748	c = msg_fifo.buf[msg_fifo.count];
	749	if (++msg_fifo.count == NELEMS(msg_fifo.buf))
	750	msg_fifo.count = 0;
	751
	752	if (msg_fifo.base != 0) {
62f624d3	753	z80_bus_cmd(Request);
0c5890bb	754	z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
62f624d3	755	z80_bus_cmd(Release);
0c5890bb L	756	}
0c5890bb L	757	}
9b6b4b31	758	#endif
0c5890bb L	759
	760	return c;
	761	}