avr/z80-if.c

   1 /**
   2  *
   3  * Pin assignments
   4  *
   5  * | Z180-Sig   |   AVR-Port    | Dir   |   Special Function    |
   6  * +------------+---------------+-------+-----------------------+
   7  * |    A0      | PA    0       |  O    |                       |
   8  * |    A1      | PA    1       |  O    |                       |
   9  * |    A2      | PA    2       |  O    |                       |
  10  * |    A3      | PA    3       |  O    |                       |
  11  * |    A4      | PA    4       |  O    |                       |
  12  * |    A5      | PA    5       |  O    |                       |
  13  * |    A6      | PA    6       |  O    |                       |
  14  * |    A7      | PA    7       |  O    |                       |
  15  * |    A8      | PC    0       |  O    |                       |
  16  * |    A9      | PC    1       |  O    |                       |
  17  * |    A10     | PC    2       |  O    |                       |
  18  * |    A11     | PC    3       |  O    |                       |
  19  * |    A12     | PC    4       |  O    |                       |
  20  * |    A13     | PC    5       |  O    |                       |
  21  * |    A14     | PC    6       |  O    |                       |
  22  * |    A15     | PC    7       |  O    |                       |
  23  * |    A16     | PE    2       |  O    |                       |
  24  * |    A17     | PE    3       |  O    |                       |
  25  * |    A18     | PE    4       |  O    |                       |
  26  * |    D0      | PF    0       |  I/O  |                       |
  27  * |    D1      | PF    1       |  I/O  |                       |
  28  * |    D2      | PF    2       |  I/O  |                       |
  29  * |    D3      | PF    3       |  I/O  |                       |
  30  * |    D4      | PF    4       |  I/O  |                       |
  31  * |    D5      | PF    5       |  I/O  |                       |
  32  * |    D6      | PF    6       |  I/O  |                       |
  33  * |    D7      | PF    7       |  I/O  |                       |
  34  * |    RD      | PD    3       |  O    |                       |
  35  * |    WR      | PD    2       |  O    |                       |
  36  * |    MREQ    | PD    4       |  O    |                       |
  37  * |    RST     | PD    5       |  O    |                       |
  38  * |    BUSREQ  | PD    7       |  O    |                       |
  39  * |    BUSACK  | PD    6       |  I    |                       |
  40  * |    IOCS1   | PE    5       |  I    |                       |
  41  * |*   HALT    | P             |       |                       |
  42  * |*   NMI     | P             |       |                       |
  43  * |            | P             |       |                       |
  44  * |            | P             |       |  af1   USART1_TX      |
  45  * |            | P             |       |  af1   USART1_RX      |
  46  * |            | P             |JTDI   |  remap SPI1_NSS'      |
  47  * |            | P             |JTDO   |  remap SPI1_SCK'      |
  48  * |            | P             |JTRST  |  remap SPI1_MISO'     |
  49  * |            | P             |       |  remap SPI1_MOSI'     |
  50  * |            | P             |       |  af1   OSC32          |
  51  * |            | P             |       |  af1   OSC32          |
  52
  53
  54  */
  55
  56 #include <avr/io.h>
  57 #include <util/delay.h>
  58 #include <util/atomic.h>
  59 #include <stdio.h>
  60 #include "debug.h"
  61 #include "z80-if.h"
  62
  63
  64 /* Number of array elements */
  65 #define NELEMS(x)  (sizeof x/sizeof *x)
  66
  67
  68 #define CONCAT(x,y) x ## y
  69 #define EVALUATOR(x,y)  CONCAT(x,y)
  70
  71 #define GPIO_(X)        CONCAT(GPIO, X)
  72
  73 struct bits {
  74   uint8_t b0:1;
  75   uint8_t b1:1;
  76   uint8_t b2:1;
  77   uint8_t b3:1;
  78   uint8_t b4:1;
  79   uint8_t b5:1;
  80   uint8_t b6:1;
  81   uint8_t b7:1;
  82 } __attribute__((__packed__));
  83
  84 #define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
  85
  86
  87 #define P_ZCLK          PORTB
  88 #define ZCLK            7
  89 #define DDR_ZCLK        DDRB
  90 #define P_MREQ          PORTD
  91 #define MREQ            4
  92 #define DDR_MREQ        DDRD
  93 #define P_RD            PORTD
  94 #define RD              3
  95 #define P_WR            PORTD
  96 #define WR              2
  97 #define P_BUSREQ        PORTD
  98 #define BUSREQ          7
  99 #define DDR_BUSREQ      DDRD
 100 #define P_BUSACK        PORTD
 101 #define PIN_BUSACK      PIND
 102 #define BUSACK          6
 103 #define DDR_BUSACK      DDRD
 104 //#define P_HALT                PORTA
 105 //#define HALT          12
 106 #define P_IOCS1         PORTE
 107 #define IOCS1           5
 108 #define DDR_IOCS1               DDRE
 109 //#define P_NMI         PORTB
 110 //#define NMI           7
 111 #define P_RST           PORTD
 112 #define DDR_RST         DDRD
 113 #define RST             5
 114
 115
 116 #define P_DB            PORTF
 117 #define PIN_DB          PINF
 118 #define DDR_DB          DDRF
 119
 120 #define P_ADL           PORTA
 121 #define P_ADH           PORTC
 122 #define P_ADB           PORTE
 123 #define PIN_ADB         PINE
 124 #define DDR_ADL         DDRA
 125 #define DDR_ADH         DDRC
 126 #define DDR_ADB         DDRE
 127
 128 #define ADB_WIDTH       3
 129 #define ADB_SHIFT       2
 130 //#define ADB_PORT      PORTE
 131
 132
 133 #define Z80_O_ZCLK      SBIT(P_ZCLK, 7)
 134 #define Z80_O_MREQ      SBIT(P_MREQ, 4)
 135 #define Z80_O_RD        SBIT(P_RD, 3)
 136 #define Z80_O_WR        SBIT(P_WR, 2)
 137 #define Z80_O_BUSREQ    SBIT(P_BUSREQ, 7)
 138 //#define Z80_O_NMI     SBIT(P_NMI, )
 139 #define Z80_O_RST       SBIT(P_RST, 5)
 140 #define Z80_I_BUSACK    SBIT(PIN_BUSACK, 6)
 141 //#define Z80_I_HALT    SBIT(P_HALT, )
 142
 143
 144 #define MASK(n) ((1<<(n))-1)
 145 #define SMASK(w,s) (MASK(w) << (s))
 146
 147 #define LOWSPEED        50000
 148
 149
 150 typedef union {
 151         uint32_t l;
 152         uint16_t w[2];
 153         uint8_t b[4];
 154 } addr_t;
 155
 156
 157 static zstate_t zstate;
 158
 159 /*--------------------------------------------------------------------------*/
 160
 161 static
 162 uint8_t is_lowspeed()
 163 {
 164         return (TCCR1B & 7) < 2 &&
 165                 OCR1A > (F_CPU / 2 / LOWSPEED);
 166 }
 167
 168 static
 169 void z80_setup_clock(void)
 170 {
 171         /* ZCLK: Output and low */
 172         DDR_ZCLK |= _BV(ZCLK);
 173         Z80_O_ZCLK = 0;
 174
 175         DDRB  |= _BV(6);        /* Debug */
 176         PORTB |= _BV(6);        /* Debug */
 177
 178         PRR0 &= ~_BV(PRTIM1);
 179
 180         /* Timer1: CTC: Toggle OC1C on compare match */
 181         OCR1A =  0;
 182         OCR1C =  0;
 183         TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
 184         TCCR1B = (0b01 << WGM12)  | (0b001 << CS10);
 185 }
 186
 187
 188 int z80_clock_set(unsigned long freq)
 189 {
 190         unsigned long ocrval = F_CPU  / freq / 2;
 191         uint8_t prescale = 0;
 192
 193         while (ocrval > (1L<<16)) {
 194                 prescale++;
 195                 if (prescale < 3)
 196                         ocrval = ocrval / 8;
 197                 else
 198                         ocrval = ocrval /  4;
 199         }
 200
 201         if ((ocrval == 0) || (prescale > 4))
 202                 return -1;
 203
 204         ocrval -= 1;
 205
 206         PINB |= _BV(6);         /* Debug */
 207
 208         /* Stop Timer */
 209         TCCR1B = (0b01 << WGM12)  | (0b000 << CS10);
 210         TCNT1 = 0;
 211
 212         OCR1A =  ocrval;
 213         OCR1CL =  ocrval;
 214         TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10);
 215         TCCR1B = (0b01 << WGM12)  | ((prescale+1) << CS10);
 216
 217         if (ocrval == 0)
 218                 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 219                         TCNT1 = 0xFFFF;
 220                 }
 221
 222         PINB |= _BV(6);         /* Debug */
 223
 224         return 0;
 225 }
 226
 227 uint32_t z80_clock_get(void)
 228 {
 229         uint32_t count = (OCR1A + 1L) * 2;
 230         uint8_t pre = (TCCR1B & 7) - 1;
 231
 232         while (pre) {
 233                 if (pre > 2)
 234                         count *= 4;
 235                 else
 236                         count *= 8;
 237                 pre--;
 238         }
 239
 240         return F_CPU/count;
 241 }
 242
 243
 244
 245 static void z80_addrbus_set_tristate(void)
 246 {
 247         /* /MREQ, /RD, /WR: Input, no pullup */
 248         DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
 249         Z80_O_MREQ = 0;
 250         Z80_O_RD = 0;
 251         Z80_O_WR = 0;
 252
 253         P_ADL = 0;
 254         DDR_ADL = 0;
 255         P_ADH = 0;
 256         DDR_ADH = 0;
 257         PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
 258         DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
 259 }
 260
 261
 262 static void z80_addrbus_set_active(void)
 263 {
 264         /* /MREQ, /RD, /WR: Output and high */
 265         Z80_O_MREQ = 1;
 266         Z80_O_RD = 1;
 267         Z80_O_WR = 1;
 268         DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);
 269
 270         DDR_ADL = 0xff;
 271         DDR_ADH = 0xff;
 272         DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
 273 }
 274
 275
 276 static void z80_dbus_set_in(void)
 277 {
 278         DDR_DB = 0;
 279         P_DB = 0;
 280 }
 281
 282
 283 static void z80_dbus_set_out(void)
 284 {
 285         DDR_DB = 0xff;
 286 }
 287
 288
 289 static void z80_reset_pulse(void)
 290 {
 291         Z80_O_RST = 0;
 292         _delay_us(10);
 293         Z80_O_RST = 1;
 294 }
 295
 296
 297 void z80_setup_bus(void)
 298 {
 299         z80_setup_clock();
 300
 301         /* /ZRESET: Output and low */
 302         Z80_O_RST = 0;
 303         DDR_RST |= _BV(RST);
 304
 305         /* /BUSREQ: Output and high */
 306         Z80_O_BUSREQ = 1;
 307         DDR_BUSREQ |= _BV(BUSREQ);
 308
 309         /* /BUSACK: Input, no pullup */
 310         DDR_BUSACK &= ~_BV(BUSACK);
 311         P_BUSACK &= ~_BV(BUSACK);
 312
 313         /* /IOCS1: Input, no pullup */
 314         DDR_IOCS1 &= ~_BV(IOCS1);
 315         P_IOCS1 &= ~_BV(IOCS1);
 316
 317         z80_addrbus_set_tristate();
 318         z80_dbus_set_in();
 319
 320         zstate = RESET;
 321 }
 322
 323
 324 zstate_t z80_bus_state(void)
 325 {
 326         return zstate;
 327 }
 328
 329
 330 static void z80_busreq_hpulse(void)
 331 {
 332         z80_dbus_set_in();
 333         z80_addrbus_set_tristate();
 334
 335         ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 336                 Z80_O_BUSREQ = 1;
 337                 Z80_O_BUSREQ = 1;       /* 2 AVR clock cycles */
 338                 Z80_O_BUSREQ = 0;       /* 2 AVR clock cycles */
 339         }
 340
 341         if (zstate & ZST_ACQUIRED) {
 342                 while(Z80_I_BUSACK == 1)
 343                         ;
 344                 z80_addrbus_set_active();
 345         }
 346 }
 347
 348
 349 /*
 350
 351  +              |               |               |               |               |
 352     +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
 353        +        |               |               |               |               |
 354           +     |       0       |       1       |       2       |       3       |
 355 Event        +  |               |               |               |               |
 356 ----------------+---------------+---------------+---------------+---------------+
 357                 |               |               |               |               |
 358 Reset           |       0       |       0       |       0       |       0       |
 359                 |               |               |               |               |
 360                 |               |               |               |               |
 361 Request         |       1       |               |       3       |               |
 362                 |               |               |               |               |
 363                 |               |               |               |               |
 364 Release         |               |       0       |               |       2       |
 365                 |               |               |               |               |
 366                 |               |               |               |               |
 367 Run             |       2       |       3       |               |               |
 368                 |               |               |               |               |
 369                 |               |               |               |               |
 370 Restart         |               |               |       2       |       3       |
 371                 |               |               |               |               |
 372                 |               |               |               |               |
 373 M_Cycle         |               |               |               |       3       |
 374                 |               |               |               |               |
 375                 |               |               |               |               |
 376 */
 377
 378 zstate_t z80_bus_cmd(bus_cmd_t cmd)
 379 {
 380         switch (cmd) {
 381
 382         case Reset:
 383                 z80_dbus_set_in();
 384                 z80_addrbus_set_tristate();
 385                 Z80_O_RST = 0;
 386                 Z80_O_BUSREQ = 1;
 387                 zstate = RESET;
 388                 break;
 389
 390         case Request:
 391                 switch (zstate) {
 392                 case RESET:
 393                         Z80_O_BUSREQ = 0;
 394                         Z80_O_RST = 1;
 395                         while(Z80_I_BUSACK == 1)
 396                                 ;
 397                         z80_addrbus_set_active();
 398                         zstate = RESET_AQRD;
 399                         break;
 400
 401                 case RUNNING:
 402                         Z80_O_BUSREQ = 0;
 403                         while(Z80_I_BUSACK == 1)
 404                                 ;
 405                         z80_addrbus_set_active();
 406                         zstate = RUNNING_AQRD;
 407                         break;
 408
 409                 default:
 410                         break;
 411                 }
 412                 break;
 413
 414         case Release:
 415                 switch (zstate) {
 416                 case RESET_AQRD:
 417                         z80_dbus_set_in();
 418                         z80_addrbus_set_tristate();
 419                         Z80_O_RST = 0;
 420                         Z80_O_BUSREQ = 1;
 421                         zstate = RESET;
 422                         break;
 423                 case RUNNING_AQRD:
 424                         z80_dbus_set_in();
 425                         z80_addrbus_set_tristate();
 426                         Z80_O_BUSREQ = 1;
 427                         zstate = RUNNING;
 428                         break;
 429                 default:
 430                         break;
 431                 }
 432                 break;
 433
 434         case Run:
 435                 switch (zstate) {
 436                 case RESET:
 437                         Z80_O_RST = 1;
 438                         zstate = RUNNING;
 439                         break;
 440
 441                 case RESET_AQRD:
 442                         z80_dbus_set_in();
 443                         z80_addrbus_set_tristate();
 444                         z80_reset_pulse();
 445                         z80_addrbus_set_active();
 446                         zstate = RUNNING_AQRD;
 447                         break;
 448                 default:
 449                         break;
 450                 }
 451                 break;
 452
 453         case Restart:
 454                 switch (zstate) {
 455                 case RUNNING:
 456                 case RUNNING_AQRD:
 457                         z80_reset_pulse();
 458                         break;
 459                 default:
 460                         break;
 461                 }
 462                 break;
 463
 464         case M_Cycle:
 465                 switch (zstate) {
 466                 case RUNNING_AQRD:
 467                         z80_busreq_hpulse();
 468                         break;
 469                 default:
 470                         break;
 471                 }
 472         }
 473         return zstate;
 474 }
 475
 476
 477 /*--------------------------------------------------------------------------*/
 478
 479 static
 480 //inline __attribute__ ((always_inline))
 481 void z80_setaddress(uint32_t addr)
 482 {
 483         addr_t x; x.l = addr;
 484
 485         P_ADL = x.b[0];
 486         P_ADH = x.b[1];
 487         PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
 488 }
 489
 490 void z80_write(uint32_t addr, uint8_t data)
 491 {
 492         z80_setaddress(addr);
 493         Z80_O_MREQ = 0;
 494         z80_dbus_set_out();
 495         P_DB = data;
 496         P_DB = data;
 497         Z80_O_WR = 0;
 498         Z80_O_WR = 0;
 499         Z80_O_WR = 1;
 500         Z80_O_MREQ = 1;
 501 }
 502
 503 uint8_t z80_read(uint32_t addr)
 504 {
 505         uint8_t data;
 506
 507         z80_setaddress(addr);
 508         Z80_O_MREQ = 0;
 509         z80_dbus_set_in();
 510         Z80_O_RD = 0;
 511         Z80_O_RD = 0;
 512         Z80_O_RD = 0;
 513         data = PIN_DB;
 514         Z80_O_RD = 1;
 515         Z80_O_MREQ = 1;
 516
 517         return data;
 518 }
 519
 520
 521 void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
 522 {
 523         z80_dbus_set_out();
 524         Z80_O_MREQ = 0;
 525         while(length--) {
 526                 z80_setaddress(addr++);
 527                 P_DB = data;
 528                 P_DB = data;
 529                 Z80_O_WR = 0;
 530                 Z80_O_WR = 0;
 531                 Z80_O_WR = 1;
 532         }
 533         Z80_O_MREQ = 1;
 534 }
 535
 536 void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
 537 {
 538         uint8_t data;
 539
 540         z80_dbus_set_out();
 541         Z80_O_MREQ = 0;
 542         while(length--) {
 543                 z80_setaddress(dest++);
 544                 data = *src++;
 545                 P_DB = data;
 546                 P_DB = data;
 547                 Z80_O_WR = 0;
 548                 Z80_O_WR = 0;
 549                 Z80_O_WR = 1;
 550         }
 551         Z80_O_MREQ = 1;
 552 }
 553
 554 /*
 555   0179'                         rx.bs_mask:     ds      1               ; (buf_len - 1)
 556   017A'                         rx.in_idx:      ds      1               ;
 557   017B'                         rx.out_idx:     ds      1               ;
 558   017C'                         rx.buf:         ds      rx.buf_len      ;
 559   018B'                         rx.buf_end      equ     $-1             ; last byte (start+len-1)
 560
 561   018C'                         tx.bs_mask:     ds      1               ; (buf_len - 1)
 562   018D'                         tx.in_idx:      ds      1               ;
 563   018E'                         tx.out_idx:     ds      1               ;
 564   018F'                         tx.buf:         ds      tx.buf_len      ;
 565   019E'                         tx.buf_end      equ     $-1             ; last byte
 566 */
 567
 568
 569 typedef struct __attribute__((packed)) {
 570         uint8_t mask;
 571         uint8_t in_idx;
 572         uint8_t out_idx;
 573         uint8_t buf[];
 574 } zfifo_t;
 575
 576
 577
 578 #define FIFO_BUFSIZE_MASK       -3
 579 #define FIFO_INDEX_IN           -2
 580 #define FIFO_INDEX_OUT          -1
 581
 582
 583 static struct {
 584         uint32_t base;
 585         uint8_t idx_out,
 586                 idx_in,
 587                 mask;
 588         } fifo_dsc[NUM_FIFOS];
 589
 590
 591 void z80_memfifo_init(const fifo_t f, uint32_t adr)
 592 {
 593
 594 DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
 595
 596         fifo_dsc[f].base = adr;
 597
 598         z80_bus_cmd(Request);
 599
 600         fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
 601         fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
 602         fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
 603
 604         z80_bus_cmd(Release);
 605 }
 606
 607
 608 int z80_memfifo_is_empty(const fifo_t f)
 609 {
 610         int rc = 1;
 611
 612         if (fifo_dsc[f].base != 0) {
 613
 614                 uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
 615                 uint8_t idx;
 616
 617                 z80_bus_cmd(Request);
 618                 idx = z80_read(adr);
 619                 z80_bus_cmd(Release);
 620                 rc = idx == fifo_dsc[f].idx_out;
 621         }
 622
 623         return rc;
 624 }
 625
 626 int z80_memfifo_is_full(const fifo_t f)
 627 {
 628         int rc = 1;
 629
 630         if (fifo_dsc[f].base != 0) {
 631                 z80_bus_cmd(Request);
 632                 rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
 633                         == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
 634                 z80_bus_cmd(Release);
 635         }
 636         return rc;
 637 }
 638
 639 uint8_t z80_memfifo_getc(const fifo_t f)
 640 {
 641         uint8_t rc, idx;
 642
 643         while (z80_memfifo_is_empty(f))
 644                 ;
 645
 646         z80_bus_cmd(Request);
 647         idx = fifo_dsc[f].idx_out;
 648         rc = z80_read(fifo_dsc[f].base+idx);
 649         fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
 650         z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
 651         z80_bus_cmd(Release);
 652
 653         return rc;
 654 }
 655
 656
 657 void z80_memfifo_putc(fifo_t f, uint8_t val)
 658 {
 659         int idx;
 660
 661         while (z80_memfifo_is_full(f))
 662                 ;
 663
 664         z80_bus_cmd(Request);
 665         idx = fifo_dsc[f].idx_in;
 666         z80_write(fifo_dsc[f].base+idx, val);
 667         fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
 668         z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
 669         z80_bus_cmd(Release);
 670 }
 671
 672 /*--------------------------------------------------------------------------*/
 673 /*
 674         TODO: Rewrite msg_fifo routines for AVR
 675 */
 676
 677 static struct {
 678         uint32_t base;
 679         //uint8_t  idx_out, idx_in;
 680         uint16_t count;
 681         uint8_t  buf[256];
 682         } msg_fifo;
 683
 684 /*--------------------------------------------------------------------------*/
 685
 686 #if 0
 687
 688 static void tim1_setup(void)
 689 {
 690         RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
 691         RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
 692
 693         TIM1_CR1 = 0;
 694
 695         TIM1_SMCR = 0
 696         /*      | TIM_SMCR_ETP                  */
 697         /*      | TIM_SMCR_ETF_CK_INT_N_2       */
 698                 | TIM_SMCR_TS_ETRF
 699                 | TIM_SMCR_SMS_OFF
 700                 ;
 701
 702         TIM1_DIER = TIM_DIER_TDE;
 703
 704
 705         TIM1_CCMR1 = 0
 706                 | TIM_CCMR1_OC1M_FORCE_LOW
 707                 | TIM_CCMR1_CC1S_OUT;
 708
 709         TIM1_SMCR |= TIM_SMCR_SMS_TM;
 710 }
 711
 712 #endif
 713
 714 /*--------------------------------------------------------------------------*/
 715
 716 void z80_setup_msg_fifo(void)
 717 {
 718 //      gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
 719 //              GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
 720
 721 //...
 722
 723 //      msg_fifo.count = NELEMS(msg_fifo.buf);
 724         msg_fifo.count = 0;
 725         msg_fifo.base = 0;
 726
 727 }
 728
 729
 730 void z80_init_msg_fifo(uint32_t addr)
 731 {
 732
 733 DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
 734
 735         z80_bus_cmd(Request);
 736         z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
 737         z80_bus_cmd(Release);
 738         msg_fifo.base = addr;
 739 }
 740
 741
 742 int z80_msg_fifo_getc(void)
 743 {
 744         int c = -1;
 745
 746 #if 0
 747         if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
 748                 c = msg_fifo.buf[msg_fifo.count];
 749                 if (++msg_fifo.count == NELEMS(msg_fifo.buf))
 750                         msg_fifo.count = 0;
 751
 752                 if (msg_fifo.base != 0) {
 753                         z80_bus_cmd(Request);
 754                         z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
 755                         z80_bus_cmd(Release);
 756                 }
 757         }
 758 #endif
 759
 760         return c;
 761 }