[z180-stamp.git] / avr / z80-if.c

/**
 *
 * Pin assignments
 *
 * | Z180-Sig   |   AVR-Port    | Dir   |   Special Function    |
 * +------------+---------------+-------+-----------------------+
 * |    A0      | PA    0       |  O    |                       |
 * |    A1      | PA    1       |  O    |                       |
 * |    A2      | PA    2       |  O    |                       |
 * |    A3      | PA    3       |  O    |                       |
 * |    A4      | PA    4       |  O    |                       |
 * |    A5      | PA    5       |  O    |                       |
 * |    A6      | PA    6       |  O    |                       |
 * |    A7      | PA    7       |  O    |                       |
 * |    A8      | PC    0       |  O    |                       |
 * |    A9      | PC    1       |  O    |                       |
 * |    A10     | PC    2       |  O    |                       |
 * |    A11     | PC    3       |  O    |                       |
 * |    A12     | PC    4       |  O    |                       |
 * |    A13     | PC    5       |  O    |                       |
 * |    A14     | PC    6       |  O    |                       |
 * |    A15     | PC    7       |  O    |                       |
 * |    A16     | PE    2       |  O    |                       |
 * |    A17     | PE    3       |  O    |                       |
 * |    A18     | PE    4       |  O    |                       |
 * |    D0      | PF    0       |  I/O  |                       |
 * |    D1      | PF    1       |  I/O  |                       |
 * |    D2      | PF    2       |  I/O  |                       |
 * |    D3      | PF    3       |  I/O  |                       |
 * |    D4      | PF    4       |  I/O  |                       |
 * |    D5      | PF    5       |  I/O  |                       |
 * |    D6      | PF    6       |  I/O  |                       |
 * |    D7      | PF    7       |  I/O  |                       |
 * |    RD      | PD    3       |  O    |                       |
 * |    WR      | PD    2       |  O    |                       |
 * |    MREQ    | PD    4       |  O    |                       |
 * |    RST     | PD    5       |  O    |                       |
 * |    BUSREQ  | PD    7       |  O    |                       |
 * |    BUSACK  | PD    6       |  I    |                       |
 * |    IOCS1   | PE    5       |  I    |                       |
 * |*   HALT    | P             |       |                       |
 * |*   NMI     | P             |       |                       |
 * |            | P             |       |                       |
 * |            | P             |       |  af1   USART1_TX      |
 * |            | P             |       |  af1   USART1_RX      |
 * |            | P             |JTDI   |  remap SPI1_NSS'      |
 * |            | P             |JTDO   |  remap SPI1_SCK'      |
 * |            | P             |JTRST  |  remap SPI1_MISO'     |
 * |            | P             |       |  remap SPI1_MOSI'     |
 * |            | P             |       |  af1   OSC32          |
 * |            | P             |       |  af1   OSC32          |


 */


#include "common.h"
#include <util/atomic.h>
#include "debug.h"
#include "z80-if.h"


//#define P_ZCLK		PORTB
//#define ZCLK		5
//#define DDR_ZCLK	DDRB
#define P_MREQ		PORTD
#define MREQ		4
#define DDR_MREQ	DDRD
#define P_RD		PORTD
#define RD		3
#define P_WR		PORTD
#define WR		2
#define P_BUSREQ	PORTD
#define BUSREQ		7
#define DDR_BUSREQ	DDRD
#define P_BUSACK	PORTD
#define PIN_BUSACK	PIND
#define BUSACK		6
#define DDR_BUSACK	DDRD
//#define P_HALT		PORTA
//#define HALT		12
#define P_IOCS1		PORTE
#define IOCS1		5
#define DDR_IOCS1		DDRE
//#define P_NMI		PORTB
//#define NMI		7
#define P_RST		PORTD
#define DDR_RST		DDRD
#define RST		5


#define P_DB		PORTF
#define PIN_DB		PINF
#define DDR_DB		DDRF

#define P_ADL		PORTA
#define P_ADH		PORTC
#define P_ADB		PORTE
#define PIN_ADB		PINE
#define DDR_ADL		DDRA
#define DDR_ADH		DDRC
#define DDR_ADB		DDRE

#define ADB_WIDTH	3
#define ADB_SHIFT	2
//#define ADB_PORT	PORTE


//#define Z80_O_ZCLK	SBIT(P_ZCLK, 5)
#define	Z80_O_MREQ	SBIT(P_MREQ, 4)
#define Z80_O_RD	SBIT(P_RD, 3)
#define Z80_O_WR	SBIT(P_WR, 2)
#define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI	SBIT(P_NMI, )
#define Z80_O_RST	SBIT(P_RST, 5)
#define Z80_I_BUSACK	SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT	SBIT(P_HALT, )


#define BUS_TO 20


#define MASK(n)	((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))


typedef union {
	uint32_t l;
	uint16_t w[2];
	uint8_t b[4];
} addr_t;


static zstate_t zstate;
static volatile uint8_t timer;		/* used for bus timeout */

/*---------------------------------------------------------*/
/* 10Hz timer interrupt generated by OC4A                  */
/*---------------------------------------------------------*/

ISR(TIMER4_COMPA_vect)
{

	uint8_t i = timer;

	if (i)
		timer = i - 1;
}

/*--------------------------------------------------------------------------*/


static void z80_addrbus_set_tristate(void)
{
	/* /MREQ, /RD, /WR: Input, no pullup */
	DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
	Z80_O_MREQ = 0;
	Z80_O_RD = 0;
	Z80_O_WR = 0;

	P_ADL = 0;
	DDR_ADL = 0;
	P_ADH = 0;
	DDR_ADH = 0;
	PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_addrbus_set_active(void)
{
	/* /MREQ, /RD, /WR: Output and high */
	Z80_O_MREQ = 1;
	Z80_O_RD = 1;
	Z80_O_WR = 1;
	DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);

	DDR_ADL = 0xff;
	DDR_ADH = 0xff;
	DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
}


static void z80_dbus_set_in(void)
{
	DDR_DB = 0;
	P_DB = 0;
}


static void z80_dbus_set_out(void)
{
	DDR_DB = 0xff;
}


static void z80_reset_pulse(void)
{
	Z80_O_RST = 0;
	_delay_us(10);
	Z80_O_RST = 1;
}


void z80_setup_bus(void)
{
	/* /ZRESET: Output and low */
	Z80_O_RST = 0;
	DDR_RST |= _BV(RST);

	/* /BUSREQ: Output and high */
	Z80_O_BUSREQ = 1;
	DDR_BUSREQ |= _BV(BUSREQ);

	/* /BUSACK: Input, no pullup */
	DDR_BUSACK &= ~_BV(BUSACK);
	P_BUSACK &= ~_BV(BUSACK);

	/* /IOCS1: Input, no pullup */
	DDR_IOCS1 &= ~_BV(IOCS1);
	P_IOCS1 &= ~_BV(IOCS1);

	z80_addrbus_set_tristate();
	z80_dbus_set_in();

	zstate = RESET;

	/* Timer 4 */
	PRR1 &= ~_BV(PRTIM4);
	OCR4A = F_CPU / 1024 / 10 - 1;		  /* Timer: 10Hz interval (OC4A) */
	TCCR4B = (0b01<<WGM42)|(0b101<<CS30); /* CTC Mode, Prescaler 1024 */
	TIMSK4 = _BV(OCIE4A);				  /* Enable oca interrupt */

}


zstate_t z80_bus_state(void)
{
	return zstate;
}


static void z80_busreq_hpulse(void)
{
	z80_dbus_set_in();
	z80_addrbus_set_tristate();

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		Z80_O_BUSREQ = 1;
		Z80_O_BUSREQ = 1;	/* 2 AVR clock cycles */
		Z80_O_BUSREQ = 0;	/* 2 AVR clock cycles */
	}

	if (zstate & ZST_ACQUIRED) {
		timer = BUS_TO;
		while (Z80_I_BUSACK == 1 && timer)
			;
		if (Z80_I_BUSACK == 0)
			z80_addrbus_set_active();
	}
}


/*

 +              |               |               |               |               |
    +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
       +        |               |               |               |               |
          +     |       0       |       1       |       2       |       3       |
Event        +  |               |               |               |               |
----------------+---------------+---------------+---------------+---------------+
                |               |               |               |               |
Reset           |       0       |       0       |       0       |       0       |
                |               |               |               |               |
                |               |               |               |               |
Request         |       1       |               |       3       |               |
                |               |               |               |               |
                |               |               |               |               |
Release         |               |       0       |               |       2       |
                |               |               |               |               |
                |               |               |               |               |
Run             |       2       |       3       |               |               |
                |               |               |               |               |
                |               |               |               |               |
Restart         |               |               |       2       |       3       |
                |               |               |               |               |
                |               |               |               |               |
M_Cycle         |               |               |               |       3       |
                |               |               |               |               |
                |               |               |               |               |
*/

zstate_t z80_bus_cmd(bus_cmd_t cmd)
{
	switch (cmd) {

	case Reset:
		z80_dbus_set_in();
		z80_addrbus_set_tristate();
		Z80_O_RST = 0;
		Z80_O_BUSREQ = 1;
		zstate = RESET;
		break;

	case Request:
		switch (zstate) {
		case RESET:
			Z80_O_BUSREQ = 0;
			Z80_O_RST = 1;
			timer = BUS_TO;
			while (Z80_I_BUSACK == 1 && timer)
				;
			if (Z80_I_BUSACK == 0) {
				z80_addrbus_set_active();
				zstate = RESET_AQRD;
			} else {
				Z80_O_RST = 0;
				Z80_O_BUSREQ = 1;
			}
			break;

		case RUNNING:
			Z80_O_BUSREQ = 0;
			timer = BUS_TO;
			while (Z80_I_BUSACK == 1 && timer)
				;
			if (Z80_I_BUSACK == 0) {
				z80_addrbus_set_active();
				zstate = RUNNING_AQRD;
			} else {
				Z80_O_BUSREQ = 1;
			}
			break;

		default:
			break;
		}
		break;

	case Release:
		switch (zstate) {
		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			Z80_O_RST = 0;
			Z80_O_BUSREQ = 1;
			zstate = RESET;
			break;
		case RUNNING_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			Z80_O_BUSREQ = 1;
			zstate = RUNNING;
			break;
		default:
			break;
		}
		break;

	case Run:
		switch (zstate) {
		case RESET:
			Z80_O_RST = 1;
			zstate = RUNNING;
			break;

		case RESET_AQRD:
			z80_dbus_set_in();
			z80_addrbus_set_tristate();
			z80_reset_pulse();
			z80_addrbus_set_active();
			zstate = RUNNING_AQRD;
			break;
		default:
			break;
		}
		break;

	case Restart:
		switch (zstate) {
		case RUNNING:
		case RUNNING_AQRD:
			z80_reset_pulse();
			break;
		default:
			break;
		}
		break;

	case M_Cycle:
		switch (zstate) {
		case RUNNING_AQRD:
			z80_busreq_hpulse();	/* TODO: */
			break;
		default:
			break;
		}
	}
	return zstate;
}


/*--------------------------------------------------------------------------*/

static
//inline __attribute__ ((always_inline))
void z80_setaddress(uint32_t addr)
{
	addr_t x; x.l = addr;

	P_ADL = x.b[0];
	P_ADH = x.b[1];
	PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
}

void z80_write(uint32_t addr, uint8_t data)
{
	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_out();
	P_DB = data;
	P_DB = data;
	Z80_O_WR = 0;
	Z80_O_WR = 0;
	Z80_O_WR = 1;
	Z80_O_MREQ = 1;
}

uint8_t z80_read(uint32_t addr)
{
	uint8_t data;

	z80_setaddress(addr);
	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	Z80_O_RD = 0;
	data = PIN_DB;
	Z80_O_RD = 1;
	Z80_O_MREQ = 1;

	return data;
}


void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
{
	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	P_DB = data;
	while(length--) {
		z80_setaddress(addr++);
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
{
	uint8_t data;

	z80_dbus_set_out();
	Z80_O_MREQ = 0;
	while(length--) {
		z80_setaddress(dest++);
		data = *src++;
		P_DB = data;
		P_DB = data;
		Z80_O_WR = 0;
		Z80_O_WR = 0;
		Z80_O_WR = 1;
	}
	Z80_O_MREQ = 1;
}

void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
{
	uint8_t data;

	Z80_O_MREQ = 0;
	z80_dbus_set_in();
	while(length--) {
		z80_setaddress(src++);
		Z80_O_RD = 0;
		Z80_O_RD = 0;
		Z80_O_RD = 0;
		data = PIN_DB;
		Z80_O_RD = 1;
		*dest++ = data;
	}
	Z80_O_MREQ = 1;
}


/*
  0179'                         rx.bs_mask:	ds	1		; (buf_len - 1)
  017A'                         rx.in_idx:	ds	1		;
  017B'                         rx.out_idx:	ds	1		;
  017C'                         rx.buf:		ds	rx.buf_len	;
  018B'                         rx.buf_end	equ	$-1		; last byte (start+len-1)

  018C'                         tx.bs_mask:	ds	1		; (buf_len - 1)
  018D'                         tx.in_idx:	ds	1		;
  018E'                         tx.out_idx:	ds	1		;
  018F'                         tx.buf:		ds	tx.buf_len 	;
  019E'                         tx.buf_end	equ	$-1		; last byte
*/


typedef struct __attribute__((packed)) {
	uint8_t mask;
	uint8_t in_idx;
	uint8_t out_idx;
	uint8_t buf[];
} zfifo_t;


#define FIFO_BUFSIZE_MASK	-3
#define FIFO_INDEX_IN		-2
#define FIFO_INDEX_OUT		-1


static struct {
	uint32_t base;
	uint8_t idx_out,
		idx_in,
		mask;
	} fifo_dsc[NUM_FIFOS];


void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
	fifo_dsc[f].base = addr;

	if (addr != 0) {

DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);

		z80_bus_cmd(Request);
		fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
		fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
		fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
}


int z80_memfifo_is_empty(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {

		uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
		uint8_t idx;

		z80_bus_cmd(Request);
		idx = z80_read(adr);
		z80_bus_cmd(Release);
		rc = idx == fifo_dsc[f].idx_out;
	}

	return rc;
}

int z80_memfifo_is_full(const fifo_t f)
{
	int rc = 1;

	if (fifo_dsc[f].base != 0) {
		z80_bus_cmd(Request);
		rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
			== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
		z80_bus_cmd(Release);
	}
	return rc;
}


uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
	uint8_t rc, idx;

	while (z80_memfifo_is_empty(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_out;
	rc = z80_read(fifo_dsc[f].base+idx);
	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	z80_bus_cmd(Release);

	return rc;
}

int z80_memfifo_getc(const fifo_t f)
{
	int rc = -1;

	if (fifo_dsc[f].base != 0) {
		uint8_t idx = fifo_dsc[f].idx_out;
		z80_bus_cmd(Request);
		if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
			rc = z80_read(fifo_dsc[f].base+idx);
			fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
			z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
		}
		z80_bus_cmd(Release);
	}

	return rc;
}


void z80_memfifo_putc(fifo_t f, uint8_t val)
{
	int idx;

	while (z80_memfifo_is_full(f))
		;

	z80_bus_cmd(Request);
	idx = fifo_dsc[f].idx_in;
	z80_write(fifo_dsc[f].base+idx, val);
	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
	z80_bus_cmd(Release);
}
Commit	Line	Data
0c5890bb L	1	/**
	2	*
	3	* Pin assignments
	4	*
ea6971b8	5	* \| Z180-Sig \| AVR-Port \| Dir \| Special Function \|
0c5890bb	6	* +------------+---------------+-------+-----------------------+
ea6971b8 L	7	* \| A0 \| PA 0 \| O \| \|
	8	* \| A1 \| PA 1 \| O \| \|
	9	* \| A2 \| PA 2 \| O \| \|
	10	* \| A3 \| PA 3 \| O \| \|
	11	* \| A4 \| PA 4 \| O \| \|
	12	* \| A5 \| PA 5 \| O \| \|
	13	* \| A6 \| PA 6 \| O \| \|
	14	* \| A7 \| PA 7 \| O \| \|
	15	* \| A8 \| PC 0 \| O \| \|
	16	* \| A9 \| PC 1 \| O \| \|
	17	* \| A10 \| PC 2 \| O \| \|
	18	* \| A11 \| PC 3 \| O \| \|
	19	* \| A12 \| PC 4 \| O \| \|
	20	* \| A13 \| PC 5 \| O \| \|
	21	* \| A14 \| PC 6 \| O \| \|
	22	* \| A15 \| PC 7 \| O \| \|
	23	* \| A16 \| PE 2 \| O \| \|
	24	* \| A17 \| PE 3 \| O \| \|
	25	* \| A18 \| PE 4 \| O \| \|
	26	* \| D0 \| PF 0 \| I/O \| \|
	27	* \| D1 \| PF 1 \| I/O \| \|
	28	* \| D2 \| PF 2 \| I/O \| \|
	29	* \| D3 \| PF 3 \| I/O \| \|
	30	* \| D4 \| PF 4 \| I/O \| \|
	31	* \| D5 \| PF 5 \| I/O \| \|
	32	* \| D6 \| PF 6 \| I/O \| \|
	33	* \| D7 \| PF 7 \| I/O \| \|
	34	* \| RD \| PD 3 \| O \| \|
	35	* \| WR \| PD 2 \| O \| \|
	36	* \| MREQ \| PD 4 \| O \| \|
	37	* \| RST \| PD 5 \| O \| \|
	38	* \| BUSREQ \| PD 7 \| O \| \|
	39	* \| BUSACK \| PD 6 \| I \| \|
	40	* \| IOCS1 \| PE 5 \| I \| \|
	41	* \|* HALT \| P \| \| \|
	42	* \|* NMI \| P \| \| \|
	43	* \| \| P \| \| \|
	44	* \| \| P \| \| af1 USART1_TX \|
	45	* \| \| P \| \| af1 USART1_RX \|
	46	* \| \| P \|JTDI \| remap SPI1_NSS' \|
	47	* \| \| P \|JTDO \| remap SPI1_SCK' \|
	48	* \| \| P \|JTRST \| remap SPI1_MISO' \|
	49	* \| \| P \| \| remap SPI1_MOSI' \|
	50	* \| \| P \| \| af1 OSC32 \|
	51	* \| \| P \| \| af1 OSC32 \|
0c5890bb L	52
	53
	54	*/
	55
ea6971b8	56
26331e24	57	#include "common.h"
f338df2a	58	#include <util/atomic.h>
0c5890bb L	59	#include "debug.h"
	60	#include "z80-if.h"
	61
	62
0c5890bb	63
41d36f28 L	64	//#define P_ZCLK PORTB
	65	//#define ZCLK 5
	66	//#define DDR_ZCLK DDRB
0c5890bb L	67	#define P_MREQ PORTD
	68	#define MREQ 4
	69	#define DDR_MREQ DDRD
	70	#define P_RD PORTD
	71	#define RD 3
	72	#define P_WR PORTD
	73	#define WR 2
	74	#define P_BUSREQ PORTD
	75	#define BUSREQ 7
	76	#define DDR_BUSREQ DDRD
	77	#define P_BUSACK PORTD
9b6b4b31	78	#define PIN_BUSACK PIND
0c5890bb L	79	#define BUSACK 6
	80	#define DDR_BUSACK DDRD
	81	//#define P_HALT PORTA
	82	//#define HALT 12
	83	#define P_IOCS1 PORTE
	84	#define IOCS1 5
	85	#define DDR_IOCS1 DDRE
	86	//#define P_NMI PORTB
	87	//#define NMI 7
	88	#define P_RST PORTD
	89	#define DDR_RST DDRD
	90	#define RST 5
	91
	92
	93	#define P_DB PORTF
	94	#define PIN_DB PINF
	95	#define DDR_DB DDRF
	96
	97	#define P_ADL PORTA
	98	#define P_ADH PORTC
	99	#define P_ADB PORTE
	100	#define PIN_ADB PINE
9b6b4b31 L	101	#define DDR_ADL DDRA
9b6b4b31 L	102	#define DDR_ADH DDRC
0c5890bb L	103	#define DDR_ADB DDRE
	104
	105	#define ADB_WIDTH 3
	106	#define ADB_SHIFT 2
	107	//#define ADB_PORT PORTE
	108
	109
41d36f28	110	//#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
0c5890bb L	111	#define Z80_O_MREQ SBIT(P_MREQ, 4)
	112	#define Z80_O_RD SBIT(P_RD, 3)
	113	#define Z80_O_WR SBIT(P_WR, 2)
	114	#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
	115	//#define Z80_O_NMI SBIT(P_NMI, )
	116	#define Z80_O_RST SBIT(P_RST, 5)
9b6b4b31	117	#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
0c5890bb L	118	//#define Z80_I_HALT SBIT(P_HALT, )
0c5890bb L	119
9b6b4b31	120
ea6971b8 L	121	#define BUS_TO 20
	122
	123
0c5890bb L	124	#define MASK(n) ((1<<(n))-1)
	125	#define SMASK(w,s) (MASK(w) << (s))
	126
0c5890bb	127
eded7ec4 L	128	typedef union {
	129	uint32_t l;
	130	uint16_t w[2];
	131	uint8_t b[4];
	132	} addr_t;
f338df2a L	133
	134
	135	static zstate_t zstate;
ea6971b8 L	136	static volatile uint8_t timer; /* used for bus timeout */
	137
	138	/---------------------------------------------------------/
	139	/* 10Hz timer interrupt generated by OC4A */
	140	/---------------------------------------------------------/
	141
	142	ISR(TIMER4_COMPA_vect)
	143	{
	144
	145	uint8_t i = timer;
	146
	147	if (i)
	148	timer = i - 1;
	149	}
eded7ec4	150
0c5890bb L	151	/--------------------------------------------------------------------------/
0c5890bb L	152
6035a17b L	153
6035a17b L	154	static void z80_addrbus_set_tristate(void)
0c5890bb	155	{
9b6b4b31 L	156	/* /MREQ, /RD, /WR: Input, no pullup */
	157	DDR_MREQ &= ~(_BV(MREQ) \| _BV(RD) \| _BV(WR));
	158	Z80_O_MREQ = 0;
	159	Z80_O_RD = 0;
	160	Z80_O_WR = 0;
	161
0c5890bb L	162	P_ADL = 0;
	163	DDR_ADL = 0;
	164	P_ADH = 0;
	165	DDR_ADH = 0;
9b6b4b31	166	PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
0c5890bb L	167	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
	168	}
	169
54678798	170
6035a17b	171	static void z80_addrbus_set_active(void)
0c5890bb	172	{
9b6b4b31 L	173	/* /MREQ, /RD, /WR: Output and high */
	174	Z80_O_MREQ = 1;
	175	Z80_O_RD = 1;
	176	Z80_O_WR = 1;
	177	DDR_MREQ \|= _BV(MREQ) \| _BV(RD) \| _BV(WR);
	178
0c5890bb L	179	DDR_ADL = 0xff;
	180	DDR_ADH = 0xff;
	181	DDR_ADB = DDR_ADB \| (MASK(ADB_WIDTH) << ADB_SHIFT);
	182	}
	183
	184
6035a17b	185	static void z80_dbus_set_in(void)
0c5890bb L	186	{
	187	DDR_DB = 0;
	188	P_DB = 0;
	189	}
	190
62f624d3	191
6035a17b	192	static void z80_dbus_set_out(void)
0c5890bb L	193	{
	194	DDR_DB = 0xff;
	195	}
	196
62f624d3 L	197
	198	static void z80_reset_pulse(void)
	199	{
	200	Z80_O_RST = 0;
	201	_delay_us(10);
	202	Z80_O_RST = 1;
	203	}
	204
	205
0c5890bb L	206	void z80_setup_bus(void)
0c5890bb L	207	{
9b6b4b31	208	/* /ZRESET: Output and low */
0c5890bb L	209	Z80_O_RST = 0;
	210	DDR_RST \|= _BV(RST);
	211
9b6b4b31	212	/* /BUSREQ: Output and high */
0c5890bb L	213	Z80_O_BUSREQ = 1;
	214	DDR_BUSREQ \|= _BV(BUSREQ);
	215
9b6b4b31	216	/* /BUSACK: Input, no pullup */
0c5890bb L	217	DDR_BUSACK &= ~_BV(BUSACK);
	218	P_BUSACK &= ~_BV(BUSACK);
	219
9b6b4b31	220	/* /IOCS1: Input, no pullup */
0c5890bb L	221	DDR_IOCS1 &= ~_BV(IOCS1);
	222	P_IOCS1 &= ~_BV(IOCS1);
	223
6035a17b L	224	z80_addrbus_set_tristate();
6035a17b L	225	z80_dbus_set_in();
72f58822	226
f338df2a	227	zstate = RESET;
ea6971b8 L	228
	229	/* Timer 4 */
	230	PRR1 &= ~_BV(PRTIM4);
	231	OCR4A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
	232	TCCR4B = (0b01<<WGM42)\|(0b101<<CS30); /* CTC Mode, Prescaler 1024 */
	233	TIMSK4 = _BV(OCIE4A); /* Enable oca interrupt */
	234
0c5890bb L	235	}
0c5890bb L	236
f338df2a	237
62f624d3	238	zstate_t z80_bus_state(void)
f338df2a L	239	{
	240	return zstate;
	241	}
	242
62f624d3 L	243
62f624d3 L	244	static void z80_busreq_hpulse(void)
0c5890bb	245	{
6035a17b L	246	z80_dbus_set_in();
6035a17b L	247	z80_addrbus_set_tristate();
72f58822	248
8a7decea	249	ATOMIC_BLOCK(ATOMIC_FORCEON) {
62f624d3 L	250	Z80_O_BUSREQ = 1;
	251	Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
	252	Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
f338df2a	253	}
72f58822	254
62f624d3	255	if (zstate & ZST_ACQUIRED) {
ea6971b8 L	256	timer = BUS_TO;
ea6971b8 L	257	while (Z80_I_BUSACK == 1 && timer)
f338df2a	258	;
ea6971b8 L	259	if (Z80_I_BUSACK == 0)
ea6971b8 L	260	z80_addrbus_set_active();
f338df2a	261	}
f338df2a L	262	}
f338df2a L	263
f338df2a L	264
f338df2a L	265	/*
f338df2a	266
ea6971b8	267	+ \| \| \| \| \|
62f624d3	268	+ State \| RESET \| RESET_AQRD \| RUNNING \| RUNNING_AQRD \|
ea6971b8 L	269	+ \| \| \| \| \|
	270	+ \| 0 \| 1 \| 2 \| 3 \|
	271	Event + \| \| \| \| \|
62f624d3	272	----------------+---------------+---------------+---------------+---------------+
ea6971b8 L	273	\| \| \| \| \|
	274	Reset \| 0 \| 0 \| 0 \| 0 \|
	275	\| \| \| \| \|
	276	\| \| \| \| \|
	277	Request \| 1 \| \| 3 \| \|
	278	\| \| \| \| \|
	279	\| \| \| \| \|
	280	Release \| \| 0 \| \| 2 \|
	281	\| \| \| \| \|
	282	\| \| \| \| \|
	283	Run \| 2 \| 3 \| \| \|
	284	\| \| \| \| \|
	285	\| \| \| \| \|
	286	Restart \| \| \| 2 \| 3 \|
	287	\| \| \| \| \|
	288	\| \| \| \| \|
	289	M_Cycle \| \| \| \| 3 \|
	290	\| \| \| \| \|
	291	\| \| \| \| \|
62f624d3	292	*/
f338df2a	293
62f624d3	294	zstate_t z80_bus_cmd(bus_cmd_t cmd)
f338df2a	295	{
62f624d3	296	switch (cmd) {
f338df2a	297
62f624d3	298	case Reset:
6035a17b L	299	z80_dbus_set_in();
6035a17b L	300	z80_addrbus_set_tristate();
f338df2a	301	Z80_O_RST = 0;
62f624d3 L	302	Z80_O_BUSREQ = 1;
62f624d3 L	303	zstate = RESET;
f338df2a L	304	break;
f338df2a L	305
62f624d3 L	306	case Request:
	307	switch (zstate) {
	308	case RESET:
	309	Z80_O_BUSREQ = 0;
	310	Z80_O_RST = 1;
ea6971b8 L	311	timer = BUS_TO;
ea6971b8 L	312	while (Z80_I_BUSACK == 1 && timer)
62f624d3	313	;
ea6971b8 L	314	if (Z80_I_BUSACK == 0) {
	315	z80_addrbus_set_active();
	316	zstate = RESET_AQRD;
	317	} else {
	318	Z80_O_RST = 0;
	319	Z80_O_BUSREQ = 1;
	320	}
62f624d3 L	321	break;
	322
	323	case RUNNING:
	324	Z80_O_BUSREQ = 0;
ea6971b8 L	325	timer = BUS_TO;
ea6971b8 L	326	while (Z80_I_BUSACK == 1 && timer)
62f624d3	327	;
ea6971b8 L	328	if (Z80_I_BUSACK == 0) {
	329	z80_addrbus_set_active();
	330	zstate = RUNNING_AQRD;
	331	} else {
	332	Z80_O_BUSREQ = 1;
	333	}
62f624d3 L	334	break;
	335
	336	default:
	337	break;
	338	}
f338df2a	339	break;
f338df2a	340
62f624d3 L	341	case Release:
	342	switch (zstate) {
	343	case RESET_AQRD:
6035a17b L	344	z80_dbus_set_in();
6035a17b L	345	z80_addrbus_set_tristate();
62f624d3 L	346	Z80_O_RST = 0;
	347	Z80_O_BUSREQ = 1;
	348	zstate = RESET;
	349	break;
	350	case RUNNING_AQRD:
6035a17b L	351	z80_dbus_set_in();
6035a17b L	352	z80_addrbus_set_tristate();
62f624d3 L	353	Z80_O_BUSREQ = 1;
	354	zstate = RUNNING;
	355	break;
	356	default:
	357	break;
	358	}
	359	break;
f338df2a	360
62f624d3 L	361	case Run:
	362	switch (zstate) {
	363	case RESET:
	364	Z80_O_RST = 1;
	365	zstate = RUNNING;
	366	break;
	367
	368	case RESET_AQRD:
6035a17b L	369	z80_dbus_set_in();
6035a17b L	370	z80_addrbus_set_tristate();
62f624d3	371	z80_reset_pulse();
6035a17b	372	z80_addrbus_set_active();
62f624d3 L	373	zstate = RUNNING_AQRD;
	374	break;
	375	default:
	376	break;
	377	}
	378	break;
f338df2a	379
62f624d3 L	380	case Restart:
	381	switch (zstate) {
	382	case RUNNING:
	383	case RUNNING_AQRD:
	384	z80_reset_pulse();
	385	break;
	386	default:
	387	break;
	388	}
	389	break;
f338df2a	390
62f624d3 L	391	case M_Cycle:
	392	switch (zstate) {
	393	case RUNNING_AQRD:
ea6971b8	394	z80_busreq_hpulse(); /* TODO: */
62f624d3 L	395	break;
	396	default:
	397	break;
	398	}
f338df2a	399	}
62f624d3	400	return zstate;
9b6b4b31 L	401	}
9b6b4b31 L	402
62f624d3	403
9b6b4b31 L	404	/--------------------------------------------------------------------------/
9b6b4b31 L	405
54678798	406	static
9b6b4b31 L	407	//inline __attribute__ ((always_inline))
	408	void z80_setaddress(uint32_t addr)
	409	{
	410	addr_t x; x.l = addr;
	411
	412	P_ADL = x.b[0];
	413	P_ADH = x.b[1];
	414	PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
0c5890bb L	415	}
	416
	417	void z80_write(uint32_t addr, uint8_t data)
	418	{
	419	z80_setaddress(addr);
	420	Z80_O_MREQ = 0;
6035a17b	421	z80_dbus_set_out();
9b6b4b31 L	422	P_DB = data;
	423	P_DB = data;
	424	Z80_O_WR = 0;
0c5890bb L	425	Z80_O_WR = 0;
	426	Z80_O_WR = 1;
	427	Z80_O_MREQ = 1;
	428	}
	429
	430	uint8_t z80_read(uint32_t addr)
	431	{
	432	uint8_t data;
	433
	434	z80_setaddress(addr);
	435	Z80_O_MREQ = 0;
6035a17b	436	z80_dbus_set_in();
0c5890bb L	437	Z80_O_RD = 0;
0c5890bb L	438	Z80_O_RD = 0;
9b6b4b31	439	Z80_O_RD = 0;
0c5890bb L	440	data = PIN_DB;
	441	Z80_O_RD = 1;
	442	Z80_O_MREQ = 1;
	443
	444	return data;
	445	}
	446
	447
	448	void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
	449	{
6035a17b	450	z80_dbus_set_out();
0c5890bb	451	Z80_O_MREQ = 0;
ea6971b8	452	P_DB = data;
0c5890bb L	453	while(length--) {
0c5890bb L	454	z80_setaddress(addr++);
ea6971b8 L	455	Z80_O_WR = 0;
	456	Z80_O_WR = 0;
	457	Z80_O_WR = 1;
	458	}
	459	Z80_O_MREQ = 1;
	460	}
	461
	462	void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
	463	{
	464	uint8_t data;
	465
	466	z80_dbus_set_out();
	467	Z80_O_MREQ = 0;
	468	while(length--) {
	469	z80_setaddress(dest++);
	470	data = *src++;
0c5890bb	471	P_DB = data;
9b6b4b31 L	472	P_DB = data;
9b6b4b31 L	473	Z80_O_WR = 0;
0c5890bb L	474	Z80_O_WR = 0;
	475	Z80_O_WR = 1;
	476	}
	477	Z80_O_MREQ = 1;
	478	}
	479
ea6971b8	480	void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
0c5890bb L	481	{
0c5890bb L	482	uint8_t data;
54678798	483
6035a17b	484	z80_dbus_set_out();
0c5890bb L	485	Z80_O_MREQ = 0;
	486	while(length--) {
	487	z80_setaddress(dest++);
	488	data = *src++;
	489	P_DB = data;
9b6b4b31 L	490	P_DB = data;
9b6b4b31 L	491	Z80_O_WR = 0;
0c5890bb L	492	Z80_O_WR = 0;
	493	Z80_O_WR = 1;
	494	}
	495	Z80_O_MREQ = 1;
	496	}
	497
ea6971b8 L	498	void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
	499	{
	500	uint8_t data;
	501
	502	Z80_O_MREQ = 0;
	503	z80_dbus_set_in();
	504	while(length--) {
	505	z80_setaddress(src++);
	506	Z80_O_RD = 0;
	507	Z80_O_RD = 0;
	508	Z80_O_RD = 0;
	509	data = PIN_DB;
	510	Z80_O_RD = 1;
	511	*dest++ = data;
	512	}
	513	Z80_O_MREQ = 1;
	514	}
	515
	516
0c5890bb L	517	/*
	518	0179' rx.bs_mask: ds 1 ; (buf_len - 1)
	519	017A' rx.in_idx: ds 1 ;
	520	017B' rx.out_idx: ds 1 ;
	521	017C' rx.buf: ds rx.buf_len ;
	522	018B' rx.buf_end equ $-1 ; last byte (start+len-1)
54678798	523
0c5890bb L	524	018C' tx.bs_mask: ds 1 ; (buf_len - 1)
	525	018D' tx.in_idx: ds 1 ;
	526	018E' tx.out_idx: ds 1 ;
	527	018F' tx.buf: ds tx.buf_len ;
	528	019E' tx.buf_end equ $-1 ; last byte
	529	*/
	530
	531
	532	typedef struct __attribute__((packed)) {
	533	uint8_t mask;
	534	uint8_t in_idx;
	535	uint8_t out_idx;
	536	uint8_t buf[];
	537	} zfifo_t;
	538
	539
	540
	541	#define FIFO_BUFSIZE_MASK -3
	542	#define FIFO_INDEX_IN -2
	543	#define FIFO_INDEX_OUT -1
	544
	545
	546	static struct {
	547	uint32_t base;
	548	uint8_t idx_out,
	549	idx_in,
	550	mask;
	551	} fifo_dsc[NUM_FIFOS];
54678798	552
0c5890bb	553
8a7decea	554	void z80_memfifo_init(const fifo_t f, uint32_t addr)
0c5890bb	555	{
8a7decea	556	fifo_dsc[f].base = addr;
0c5890bb	557
8a7decea	558	if (addr != 0) {
0c5890bb	559
8a7decea	560	DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
0c5890bb	561
8a7decea L	562	z80_bus_cmd(Request);
	563	fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
	564	fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
	565	fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
	566	z80_bus_cmd(Release);
	567	}
0c5890bb L	568	}
	569
	570
	571	int z80_memfifo_is_empty(const fifo_t f)
	572	{
	573	int rc = 1;
	574
89adce76	575	if (fifo_dsc[f].base != 0) {
0c5890bb L	576
	577	uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
	578	uint8_t idx;
	579
62f624d3	580	z80_bus_cmd(Request);
0c5890bb	581	idx = z80_read(adr);
62f624d3	582	z80_bus_cmd(Release);
0c5890bb L	583	rc = idx == fifo_dsc[f].idx_out;
	584	}
	585
	586	return rc;
	587	}
	588
	589	int z80_memfifo_is_full(const fifo_t f)
	590	{
	591	int rc = 1;
54678798	592
0c5890bb	593	if (fifo_dsc[f].base != 0) {
62f624d3	594	z80_bus_cmd(Request);
0c5890bb L	595	rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
0c5890bb L	596	== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
62f624d3	597	z80_bus_cmd(Release);
0c5890bb L	598	}
	599	return rc;
	600	}
	601
89adce76 L	602
89adce76 L	603	uint8_t z80_memfifo_getc_wait(const fifo_t f)
0c5890bb L	604	{
0c5890bb L	605	uint8_t rc, idx;
54678798	606
0c5890bb L	607	while (z80_memfifo_is_empty(f))
	608	;
	609
62f624d3	610	z80_bus_cmd(Request);
0c5890bb L	611	idx = fifo_dsc[f].idx_out;
	612	rc = z80_read(fifo_dsc[f].base+idx);
	613	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	614	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
62f624d3	615	z80_bus_cmd(Release);
54678798	616
0c5890bb L	617	return rc;
	618	}
	619
89adce76 L	620	int z80_memfifo_getc(const fifo_t f)
	621	{
	622	int rc = -1;
	623
	624	if (fifo_dsc[f].base != 0) {
	625	uint8_t idx = fifo_dsc[f].idx_out;
	626	z80_bus_cmd(Request);
	627	if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
	628	rc = z80_read(fifo_dsc[f].base+idx);
	629	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
	630	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
	631	}
	632	z80_bus_cmd(Release);
	633	}
	634
	635	return rc;
	636	}
	637
0c5890bb L	638
	639	void z80_memfifo_putc(fifo_t f, uint8_t val)
	640	{
	641	int idx;
54678798	642
0c5890bb L	643	while (z80_memfifo_is_full(f))
	644	;
	645
62f624d3	646	z80_bus_cmd(Request);
0c5890bb L	647	idx = fifo_dsc[f].idx_in;
	648	z80_write(fifo_dsc[f].base+idx, val);
	649	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
	650	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
62f624d3	651	z80_bus_cmd(Release);
0c5890bb	652	}