[z180-stamp.git] / avr / z180-serv.c

/*
 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "common.h"
#include <stdlib.h>
#include <string.h>
#include <stdbool.h>
#include <util/atomic.h>

#include "background.h"
#include "env.h"
#include "ff.h"
#include "serial.h"
#include "z80-if.h"
#include "debug.h"
#include "print-utils.h"
#include "z180-serv.h"
#include "timer.h"


#define DEBUG_CPM_SDIO	0	/* set to 1 to debug */

#define debug_cpmsd(fmt, args...)		                                            \
	debug_cond(DEBUG_CPM_SDIO, fmt, ##args)


/*--------------------------------------------------------------------------*/


uint8_t z80_get_byte(uint32_t adr)
{
	uint8_t data;

	z80_bus_cmd(Request);
	data = z80_read(adr);
	z80_bus_cmd(Release);

	return data;
}


/*--------------------------------------------------------------------------*/

struct msg_item {
	uint8_t fct;
	uint8_t sub_min, sub_max;
	void (*func)(uint8_t, int, uint8_t *);
};

uint32_t msg_to_addr(uint8_t *msg)
{
	union {
		uint32_t as32;
		uint8_t as8[4];
	} addr;

	addr.as8[0] = msg[0];
	addr.as8[1] = msg[1];
	addr.as8[2] = msg[2];
	addr.as8[3] = 0;

	return addr.as32;
}


static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
{
	z80_memfifo_putc(fifo_msgout, 0xAE);
	z80_memfifo_putc(fifo_msgout, len+2);
	z80_memfifo_putc(fifo_msgout, func);
	z80_memfifo_putc(fifo_msgout, subf);

	return 0;
}

int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
{
	msg_xmit_header(func, subf, len);
	while (len--)
		z80_memfifo_putc(fifo_msgout, *msg++);

	return 0;
}

void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
{
	(void)len;

	z80_memfifo_init(subf, msg_to_addr(msg));
}


void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
{
	(void)subf;

	while (len--)
		putchar(*msg++);
}

/* echo message */
void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
{
	(void)subf;

	/* send re-echo */
	msg_xmit(1, 3, len, msg);
}

/* ---------------------------------------------------------------------------*/

#define MAX_DRIVE	4
#define BLOCK_SIZE	512
#define TPA_BASE	0x10000
#define COMMON_BASE	0xC000

struct cpm_drive_s {
	uint8_t drv;
	uint8_t device;
	char *img_name;
	bool dirty;
	FIL fd;
};

static uint8_t disk_buffer[BLOCK_SIZE];
static struct cpm_drive_s drv_table[MAX_DRIVE];
static int handle_cpm_drv_to;

#define f_dirty(fp) ((fp)->fs->wflag != 0)


int cpm_drv_to(int state)
{
	static uint32_t ts;

	switch(state) {
	case 0:
		break;

	case 1:
		ts = get_timer(0);
		state = 2;
		break;

	case 2:
		if (get_timer(ts) > 1000) {
			for (uint_fast8_t i=0; i < MAX_DRIVE; i++) {
//				if (&drv_table[i].fd && f_dirty(&drv_table[i].fd)) {
				if (drv_table[i].dirty) {
					f_sync(&drv_table[i].fd);
					drv_table[i].dirty = false;
					debug_cpmsd("## %7lu f_sync: %c:\n", get_timer(0), i+'A');
				}
			}
			state = 0;
		}
	}
	return state;
}


void msg_cpm_result(uint8_t subf, uint8_t rc, int res)
{
	uint8_t result_msg[3];

	if (res)
		rc |= 0x80;

	result_msg[0] = rc;
	result_msg[1] = res;
	result_msg[2] = res >> 8;

	if (rc) {
		debug_cpmsd("###%7lu  error rc: %.02x, res: %d\n", get_timer(0), rc, res);
	}

	msg_xmit(2, subf, sizeof(result_msg), result_msg);
}

/*
 	db	2	; disk command
	ds	1	; subcommand (login/read/write)
	ds	1	; @adrv (8 bits)	+0
	ds	1	; @rdrv (8 bits)	+1
	ds	3	; @xdph (24 bits)	+2
*/

void do_msg_cpm_login(uint8_t subf, int len, uint8_t * msg)
{

	FRESULT res = 0;
	uint8_t drv;
	char *np;

	(void)subf;

	if (len != 5) {     /* TODO: check adrv, rdrv */
		return msg_cpm_result(subf, 0x01, res);
	}

	debug_cpmsd("\n## %7lu  login: %c:\n", get_timer(0), msg[0]+'A');


	drv = msg[0];
	if ( drv>= MAX_DRIVE) {
		return msg_cpm_result(subf, 0x02, res);
	}

/*
	uint32_t dph = ((uint32_t)msg[4] << 16) + ((uint16_t)msg[3] << 8) + msg[2];
*/

	if (drv_table[drv].img_name != NULL) {
		debug_cpmsd("## %7lu  close: '%s'\n", get_timer(0), drv_table[drv].img_name);
		f_close(&drv_table[drv].fd);
		drv_table[drv].dirty = false;
		free(drv_table[drv].img_name);
		drv_table[drv].img_name = NULL;
	}

	strcpy_P((char *)disk_buffer, PSTR("dsk0"));
	disk_buffer[3] = msg[0] + '0';
	if (((np = getenv((char*)disk_buffer)) == NULL) ||
			((drv_table[drv].img_name = strdup(np)) == NULL)) {
		return msg_cpm_result(subf, 0x03, res);
	}


	res = f_open(&drv_table[drv].fd, drv_table[drv].img_name,
			FA_WRITE | FA_READ);

    debug_cpmsd("## %7lu   open: '%s', (env: '%s'), res: %d\n", get_timer(0),
			drv_table[drv].img_name, disk_buffer, res);

	/* send  result*/
	msg_cpm_result(subf, 0x00, res);
}


/*
 	db	2	; disk command
	ds	1	; subcommand (login/read/write)
	ds	1	; @adrv (8 bits)		+0
	ds	1	; @rdrv (8 bits)		+1
	ds	2	; @trk (16 bits)		+2
	ds	2	; @sect(16 bits)		+4
	ds	1	; @cnt  (8 bits)		+6
	ds	3	; phys. transfer addr	+7
*/

#define ADRV	0
#define RDRV	1
#define TRK		2
#define SEC		4
#define CNT		6
#define ADDR	7

void do_msg_cpm_rw(uint8_t subf, int len, uint8_t * msg)
{
	uint8_t drv;
	uint32_t addr;
	uint32_t pos;
	uint8_t secs;
	bool dowrite = (subf == 2);
	FRESULT res = 0;
	uint8_t rc = 0;
	bool buserr = 0;

	if (len != 10) {     /* TODO: check adrv, rdrv */
		return msg_cpm_result(subf, 0x01, res);
	}

	drv = msg[ADRV];
	if ( drv>= MAX_DRIVE) {
		return msg_cpm_result(subf, 0x02, res);
	}

	secs = msg[CNT];
	addr = ((uint32_t)msg[ADDR+2] << 16) + ((uint16_t)msg[ADDR+1] << 8) + msg[ADDR];


	/* TODO: tracks per sector from dpb */
	pos = (((uint16_t)(msg[TRK+1] << 8) + msg[TRK]) * 8
			+ ((uint32_t)(msg[SEC+1] << 8) + msg[SEC])) * BLOCK_SIZE;

	debug_cpmsd("## %7lu cpm_rw: %s %c: trk:%4d, sec: %d, pos: %.8lx, secs: %2d, "
			"addr: %.5lx\n", get_timer(0), dowrite ? "write" : " read",
			msg[ADRV]+'A', ((uint16_t)(msg[TRK+1] << 8) + msg[TRK]), msg[SEC],
			pos, msg[CNT], addr);

	res = f_lseek(&drv_table[drv].fd, pos);
	while (!res && secs--) {
		unsigned int cnt, br;

		/* check bank boundary crossing */
		cnt = 0;
		if (addr < (TPA_BASE + COMMON_BASE) &&
					(addr + BLOCK_SIZE) > (TPA_BASE + COMMON_BASE)) {
			cnt = (TPA_BASE + COMMON_BASE) - addr;
		}

		if (cnt) {
			debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr, cnt);
			debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr+cnt-TPA_BASE, BLOCK_SIZE-cnt);
		}

		if (dowrite) {
			if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
				buserr = 1;
				break;
			} else {
				if (cnt) {
					z80_read_block(disk_buffer, addr, cnt);
					addr = addr + cnt - TPA_BASE;
				}
				z80_read_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
				z80_bus_cmd(Release);
			}
			res = f_write(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
		} else {
			res = f_read(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
			if (res == FR_OK && br == BLOCK_SIZE) {
				if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
					buserr = 1;
					break;
				} else {
					if (cnt) {
						z80_write_block(disk_buffer, addr, cnt);
						addr = addr + cnt - TPA_BASE;
					}
					z80_write_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
					z80_bus_cmd(Release);
				}
			}
		}

		if (br != BLOCK_SIZE) {
			debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res, br);
			dump_ram(disk_buffer, 0, 64, "Read Data");
			res = -1;
		}

		addr += BLOCK_SIZE;
	}

	if (dowrite && !res) {
//		res = f_sync(&drv_table[drv].fd);
		drv_table[drv].dirty = true;
		bg_setstat(handle_cpm_drv_to, 1);
	}


	if (buserr) {
		debug_cpmsd("Bus timeout\n");
		rc = 0x03;
	}

	/* send  result*/
	msg_cpm_result(subf, rc, res);
}


const FLASH struct msg_item z80_messages[] =
{
	{ 0,			/* fct nr. */
	  1, 3,			/* sub fct nr. from, to */
	  do_msg_ini_memfifo},
	{ 1,
	  1, 1,
	  do_msg_char_out},
	{ 1,
	  2, 2,
	  do_msg_echo},
	{ 2,
	  0, 0,
	  do_msg_cpm_login},
	{ 2,
	  1, 2,
	  do_msg_cpm_rw},
	{ 0xff,				/* end mark */
	  0, 0,
	  0},

};


void do_message(int len, uint8_t *msg)
{
	uint8_t fct, sub_fct;
	int_fast8_t i = 0;

	if (len >= 2) {
		fct = *msg++;
		sub_fct = *msg++;
		len -= 2;

		while (fct != z80_messages[i].fct) {
			if (z80_messages[i].fct == 0xff) {
				DBG_P(1, "do_message: Unknown function: %i, %i\n",
						fct, sub_fct);
				return; /* TODO: unknown message # */
			}

			++i;
		}

		while (fct == z80_messages[i].fct) {
			if (sub_fct >= z80_messages[i].sub_min &&
					sub_fct <= z80_messages[i].sub_max )
				break;
			++i;
		}

		if (z80_messages[i].fct != fct) {
			DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
					fct, sub_fct);
			return; /* TODO: unknown message sub# */
		}

		(z80_messages[i].func)(sub_fct, len, msg);


	} else {
		/* TODO: error */
		DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
	}
}


#define CTRBUF_LEN 256

void check_msg_fifo(void)
{
	int ch;
	static int_fast8_t state;
	static int msglen,idx;
	static uint8_t buffer[CTRBUF_LEN];

	while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
		switch (state) {
		case 0:		/* wait for start of message */
			if (ch == 0xAE)	{ /* TODO: magic number */
				msglen = 0;
				idx = 0;
				state = 1;
			}
			break;
		case 1:		/* get msg len */
			if (ch > 0 && ch <= CTRBUF_LEN) {
				msglen = ch;
				state = 2;
			} else
				state = 0;
			break;
		case 2: 	/* get message */
			buffer[idx++] = ch;
			if (idx == msglen) {
				do_message(msglen, buffer);
				state = 0;
			}
			break;
		}
	}
}


int msg_handling(int state)
{
	uint8_t pending;

	ATOMIC_BLOCK(ATOMIC_FORCEON) {
		pending = (Stat & S_MSG_PENDING) != 0;
		Stat &= ~S_MSG_PENDING;
	}

	if (pending) {
		switch (state) {
		case 0:			/* need init */
			/* Get address of fifo_list */
			z80_bus_cmd(Request);
			uint32_t fifo_list = z80_read(0x40) +
				((uint16_t) z80_read(0x41) << 8) +
				((uint32_t) z80_read(0x42) << 16);
			z80_bus_cmd(Release);
			if (fifo_list != 0) {
				/* Get address of fifo 0 */
				z80_bus_cmd(Request);
				uint32_t fifo_addr = z80_read(fifo_list) +
					((uint16_t) z80_read(fifo_list+1) << 8) +
					((uint32_t) z80_read(fifo_list+2) << 16);
				z80_bus_cmd(Release);
				if (fifo_addr != 0) {
					z80_memfifo_init(fifo_msgin, fifo_addr);
					state = 1;
				}
			}
			break;
		case 1:			/* awaiting messages */
			check_msg_fifo();
			break;
		}
	}

	return state;
}


static int handle_msg_handling;

void setup_z180_serv(void)
{

	handle_msg_handling = bg_register(msg_handling, 0);
	handle_cpm_drv_to = bg_register(cpm_drv_to, 0);
}

void restart_z180_serv(void)
{
	z80_bus_cmd(Request);
	z80_write(0x40, 0);
	z80_write(0x41, 0);
	z80_write(0x42, 0);
	z80_bus_cmd(Release);

	for (int i = 0; i < NUM_FIFOS; i++)
		z80_memfifo_init(i, 0);
	bg_setstat(handle_msg_handling, 0);

}

/*--------------------------------------------------------------------------*/

const FLASH uint8_t iniprog[] = {
	0xAF,			// xor     a
	0xED, 0x39, 0x36,	// out0    (rcr),a         ;disable  DRAM refresh
	0x3E, 0x30,		// ld      a,030h
	0xED, 0x39, 0x32	//out0    (dcntl),a       ;0 mem, max i/0 wait states
};

const FLASH uint8_t sertest[] = {
	0xAF,              //  	xor	a
	0xED, 0x39, 0x36,  //  	out0	(rcr),a		;disable  DRAM refresh
	0x3E, 0x30,        //  	ld	a,030h
	0xED, 0x39, 0x32,  //  	out0	(dcntl),a	;0 mem, max i/0 wait states
	0x3E, 0x80,        //  	ld	a,M_MPBT		;no MP, PS=10, DR=16, SS=0
	0xED, 0x39, 0x03,  //  	out0	(cntlb1),a
	0x3E, 0x64,        //  	ld	a,M_RE + M_TE + M_MOD2	;
	0xED, 0x39, 0x01,  //  	out0	(cntla1),a
	0x3E, 0x00,        //  	ld	a,0
	0xED, 0x39, 0x05,  //  	out0	(stat1),a	;Enable rx interrupts
	0xED, 0x38, 0x05,  //l0:in0	a,(stat1)
	0xE6, 0x80,        //  	and	80h
	0x28, 0xF9,        //  	jr	z,l0
	0xED, 0x00, 0x09,  //  	in0	b,(rdr1)
	0xED, 0x38, 0x05,  //l1:in0	a,(stat1)
	0xE6, 0x02,        //  	and	02h
	0x28, 0xF9,        //  	jr	z,l1
	0xED, 0x01, 0x07,  //  	out0	(tdr1),b
	0x18, 0xEA,        //  	jr	l0
};

const FLASH uint8_t test1[] = {
	0xAF,              //	xor	a
	0xED, 0x39, 0x36,  //	out0	(rcr),a		;disable  DRAM refresh
	0x3E, 0x30,        //	ld	a,030h
	0xED, 0x39, 0x32,  //	out0	(dcntl),a	;0 mem, max i/0 wait states
	0x21, 0x1E, 0x00,  // 	ld	hl,dmclrt	;load DMA registers
	0x06, 0x08,        //	ld	b,dmct_e-dmclrt
	0x0E, 0x20,        //	ld	c,sar0l
	0xED, 0x93,        //	otimr
	0x3E, 0xC3,        //	ld	a,0c3h		;dst +1, src +1, burst
	0xED, 0x39, 0x31,  //	out0	(dmode),a	;
	0x3E, 0x62,        //	ld	a,062h		;enable dma0,
	0xED, 0x39, 0x30,  //cl_1:	out0	(dstat),a	;copy 64k
	0x18, 0xFB,        //	jr	cl_1		;
	0x00, 0x00,        //dmclrt:	dw	0		;src (inc)
	0x00,              //	db 	0		;src
	0x00, 0x00,        //	dw	0		;dst (inc),
	0x00,              //	db	0		;dst
	0x00, 0x00,        //	dw 	0		;count (64k)
};
Commit	Line	Data
35edb766 L	1	/*
	2	* (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
72f58822	7	#include "common.h"
5f7f3586 L	8	#include <stdlib.h>
	9	#include <string.h>
	10	#include <stdbool.h>
89adce76	11	#include <util/atomic.h>
72f58822	12
89adce76	13	#include "background.h"
5f7f3586 L	14	#include "env.h"
5f7f3586 L	15	#include "ff.h"
72f58822 L	16	#include "serial.h"
72f58822 L	17	#include "z80-if.h"
889202c4	18	#include "debug.h"
5f7f3586	19	#include "print-utils.h"
89adce76	20	#include "z180-serv.h"
daacc6f9	21	#include "timer.h"
72f58822	22
7d60b20b L	23
	24	#define DEBUG_CPM_SDIO 0 /* set to 1 to debug */
	25
	26	#define debug_cpmsd(fmt, args...) \
	27	debug_cond(DEBUG_CPM_SDIO, fmt, ##args)
	28
	29
	30
72f58822 L	31	/--------------------------------------------------------------------------/
72f58822 L	32
72f58822 L	33
	34	uint8_t z80_get_byte(uint32_t adr)
	35	{
	36	uint8_t data;
8a7decea	37
62f624d3	38	z80_bus_cmd(Request);
89adce76	39	data = z80_read(adr);
62f624d3	40	z80_bus_cmd(Release);
8a7decea	41
72f58822 L	42	return data;
	43	}
	44
	45
	46	/--------------------------------------------------------------------------/
	47
	48	struct msg_item {
	49	uint8_t fct;
	50	uint8_t sub_min, sub_max;
	51	void (func)(uint8_t, int, uint8_t );
	52	};
	53
	54	uint32_t msg_to_addr(uint8_t *msg)
	55	{
	56	union {
	57	uint32_t as32;
	58	uint8_t as8[4];
	59	} addr;
	60
	61	addr.as8[0] = msg[0];
	62	addr.as8[1] = msg[1];
	63	addr.as8[2] = msg[2];
	64	addr.as8[3] = 0;
	65
	66	return addr.as32;
	67	}
	68
72f58822	69
1a2460dc L	70	static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
	71	{
	72	z80_memfifo_putc(fifo_msgout, 0xAE);
	73	z80_memfifo_putc(fifo_msgout, len+2);
	74	z80_memfifo_putc(fifo_msgout, func);
	75	z80_memfifo_putc(fifo_msgout, subf);
	76
	77	return 0;
	78	}
	79
	80	int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
	81	{
	82	msg_xmit_header(func, subf, len);
	83	while (len--)
	84	z80_memfifo_putc(fifo_msgout, *msg++);
	85
	86	return 0;
	87	}
	88
72f58822 L	89	void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
	90	{
	91	(void)len;
	92
89adce76	93	z80_memfifo_init(subf, msg_to_addr(msg));
72f58822 L	94	}
	95
	96
	97	void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
	98	{
	99	(void)subf;
	100
	101	while (len--)
	102	putchar(*msg++);
	103	}
	104
1a2460dc L	105	/* echo message */
	106	void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
	107	{
	108	(void)subf;
	109
	110	/* send re-echo */
	111	msg_xmit(1, 3, len, msg);
	112	}
	113
5f7f3586 L	114	/* ---------------------------------------------------------------------------*/
5f7f3586 L	115
01484095	116	#define MAX_DRIVE 4
5f7f3586	117	#define BLOCK_SIZE 512
daacc6f9 L	118	#define TPA_BASE 0x10000
daacc6f9 L	119	#define COMMON_BASE 0xC000
5f7f3586 L	120
	121	struct cpm_drive_s {
	122	uint8_t drv;
	123	uint8_t device;
	124	char *img_name;
393b1897	125	bool dirty;
5f7f3586 L	126	FIL fd;
	127	};
	128
	129	static uint8_t disk_buffer[BLOCK_SIZE];
5f7f3586	130	static struct cpm_drive_s drv_table[MAX_DRIVE];
393b1897 L	131	static int handle_cpm_drv_to;
	132
	133	#define f_dirty(fp) ((fp)->fs->wflag != 0)
	134
	135
	136	int cpm_drv_to(int state)
	137	{
	138	static uint32_t ts;
	139
	140	switch(state) {
	141	case 0:
	142	break;
	143
	144	case 1:
	145	ts = get_timer(0);
	146	state = 2;
	147	break;
	148
	149	case 2:
	150	if (get_timer(ts) > 1000) {
	151	for (uint_fast8_t i=0; i < MAX_DRIVE; i++) {
	152	// if (&drv_table[i].fd && f_dirty(&drv_table[i].fd)) {
	153	if (drv_table[i].dirty) {
	154	f_sync(&drv_table[i].fd);
	155	drv_table[i].dirty = false;
	156	debug_cpmsd("## %7lu f_sync: %c:\n", get_timer(0), i+'A');
	157	}
	158	}
	159	state = 0;
	160	}
	161	}
	162	return state;
	163	}
	164
	165
	166	void msg_cpm_result(uint8_t subf, uint8_t rc, int res)
	167	{
	168	uint8_t result_msg[3];
	169
	170	if (res)
	171	rc \|= 0x80;
	172
	173	result_msg[0] = rc;
	174	result_msg[1] = res;
	175	result_msg[2] = res >> 8;
	176
	177	if (rc) {
	178	debug_cpmsd("###%7lu error rc: %.02x, res: %d\n", get_timer(0), rc, res);
	179	}
	180
	181	msg_xmit(2, subf, sizeof(result_msg), result_msg);
	182	}
5f7f3586 L	183
	184	/*
	185	db 2 ; disk command
	186	ds 1 ; subcommand (login/read/write)
	187	ds 1 ; @adrv (8 bits) +0
	188	ds 1 ; @rdrv (8 bits) +1
	189	ds 3 ; @xdph (24 bits) +2
	190	*/
	191
	192	void do_msg_cpm_login(uint8_t subf, int len, uint8_t * msg)
	193	{
	194
	195	FRESULT res = 0;
5f7f3586 L	196	uint8_t drv;
5f7f3586 L	197	char *np;
5f7f3586 L	198
	199	(void)subf;
	200
	201	if (len != 5) { /* TODO: check adrv, rdrv */
393b1897	202	return msg_cpm_result(subf, 0x01, res);
5f7f3586 L	203	}
5f7f3586 L	204
7d60b20b	205	debug_cpmsd("\n## %7lu login: %c:\n", get_timer(0), msg[0]+'A');
5f7f3586 L	206
	207
	208	drv = msg[0];
	209	if ( drv>= MAX_DRIVE) {
393b1897	210	return msg_cpm_result(subf, 0x02, res);
5f7f3586 L	211	}
5f7f3586 L	212
5f7f3586 L	213	/*
	214	uint32_t dph = ((uint32_t)msg[4] << 16) + ((uint16_t)msg[3] << 8) + msg[2];
	215	*/
	216
	217	if (drv_table[drv].img_name != NULL) {
7d60b20b	218	debug_cpmsd("## %7lu close: '%s'\n", get_timer(0), drv_table[drv].img_name);
5f7f3586	219	f_close(&drv_table[drv].fd);
393b1897	220	drv_table[drv].dirty = false;
5f7f3586 L	221	free(drv_table[drv].img_name);
	222	drv_table[drv].img_name = NULL;
	223	}
	224
	225	strcpy_P((char *)disk_buffer, PSTR("dsk0"));
	226	disk_buffer[3] = msg[0] + '0';
	227	if (((np = getenv((char*)disk_buffer)) == NULL) \|\|
	228	((drv_table[drv].img_name = strdup(np)) == NULL)) {
393b1897	229	return msg_cpm_result(subf, 0x03, res);
5f7f3586 L	230	}
	231
	232
	233	res = f_open(&drv_table[drv].fd, drv_table[drv].img_name,
	234	FA_WRITE \| FA_READ);
	235
7d60b20b	236	debug_cpmsd("## %7lu open: '%s', (env: '%s'), res: %d\n", get_timer(0),
5f7f3586 L	237	drv_table[drv].img_name, disk_buffer, res);
5f7f3586 L	238
5f7f3586	239	/* send result*/
393b1897	240	msg_cpm_result(subf, 0x00, res);
5f7f3586 L	241	}
	242
	243
	244	/*
	245	db 2 ; disk command
	246	ds 1 ; subcommand (login/read/write)
daacc6f9 L	247	ds 1 ; @adrv (8 bits) +0
	248	ds 1 ; @rdrv (8 bits) +1
	249	ds 2 ; @trk (16 bits) +2
	250	ds 2 ; @sect(16 bits) +4
	251	ds 1 ; @cnt (8 bits) +6
5f7f3586 L	252	ds 3 ; phys. transfer addr +7
	253	*/
	254
daacc6f9 L	255	#define ADRV 0
	256	#define RDRV 1
	257	#define TRK 2
	258	#define SEC 4
	259	#define CNT 6
	260	#define ADDR 7
	261
5f7f3586 L	262	void do_msg_cpm_rw(uint8_t subf, int len, uint8_t * msg)
	263	{
	264	uint8_t drv;
	265	uint32_t addr;
	266	uint32_t pos;
7d60b20b	267	uint8_t secs;
5f7f3586 L	268	bool dowrite = (subf == 2);
	269	FRESULT res = 0;
	270	uint8_t rc = 0;
	271	bool buserr = 0;
5f7f3586 L	272
5f7f3586 L	273	if (len != 10) { /* TODO: check adrv, rdrv */
393b1897	274	return msg_cpm_result(subf, 0x01, res);
5f7f3586 L	275	}
5f7f3586 L	276
daacc6f9	277	drv = msg[ADRV];
5f7f3586	278	if ( drv>= MAX_DRIVE) {
393b1897	279	return msg_cpm_result(subf, 0x02, res);
5f7f3586 L	280	}
5f7f3586 L	281
7d60b20b	282	secs = msg[CNT];
daacc6f9	283	addr = ((uint32_t)msg[ADDR+2] << 16) + ((uint16_t)msg[ADDR+1] << 8) + msg[ADDR];
5f7f3586	284
5f7f3586	285
daacc6f9 L	286	/* TODO: tracks per sector from dpb */
	287	pos = (((uint16_t)(msg[TRK+1] << 8) + msg[TRK]) * 8
	288	+ ((uint32_t)(msg[SEC+1] << 8) + msg[SEC])) * BLOCK_SIZE;
5f7f3586	289
7d60b20b L	290	debug_cpmsd("## %7lu cpm_rw: %s %c: trk:%4d, sec: %d, pos: %.8lx, secs: %2d, "
	291	"addr: %.5lx\n", get_timer(0), dowrite ? "write" : " read",
	292	msg[ADRV]+'A', ((uint16_t)(msg[TRK+1] << 8) + msg[TRK]), msg[SEC],
	293	pos, msg[CNT], addr);
5f7f3586 L	294
5f7f3586 L	295	res = f_lseek(&drv_table[drv].fd, pos);
7d60b20b	296	while (!res && secs--) {
daacc6f9 L	297	unsigned int cnt, br;
daacc6f9 L	298
7d60b20b L	299	/* check bank boundary crossing */
7d60b20b L	300	cnt = 0;
daacc6f9	301	if (addr < (TPA_BASE + COMMON_BASE) &&
7d60b20b	302	(addr + BLOCK_SIZE) > (TPA_BASE + COMMON_BASE)) {
daacc6f9	303	cnt = (TPA_BASE + COMMON_BASE) - addr;
daacc6f9 L	304	}
daacc6f9 L	305
7d60b20b L	306	if (cnt) {
	307	debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr, cnt);
	308	debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr+cnt-TPA_BASE, BLOCK_SIZE-cnt);
	309	}
5f7f3586 L	310
	311	if (dowrite) {
	312	if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
	313	buserr = 1;
7d60b20b	314	break;
5f7f3586	315	} else {
7d60b20b L	316	if (cnt) {
	317	z80_read_block(disk_buffer, addr, cnt);
	318	addr = addr + cnt - TPA_BASE;
	319	}
	320	z80_read_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
5f7f3586	321	z80_bus_cmd(Release);
5f7f3586	322	}
7d60b20b	323	res = f_write(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
5f7f3586	324	} else {
7d60b20b L	325	res = f_read(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
7d60b20b L	326	if (res == FR_OK && br == BLOCK_SIZE) {
5f7f3586 L	327	if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
5f7f3586 L	328	buserr = 1;
7d60b20b	329	break;
5f7f3586	330	} else {
7d60b20b L	331	if (cnt) {
	332	z80_write_block(disk_buffer, addr, cnt);
	333	addr = addr + cnt - TPA_BASE;
	334	}
	335	z80_write_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
5f7f3586 L	336	z80_bus_cmd(Release);
	337	}
	338	}
	339	}
	340
7d60b20b L	341	if (br != BLOCK_SIZE) {
7d60b20b L	342	debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res, br);
5f7f3586 L	343	dump_ram(disk_buffer, 0, 64, "Read Data");
	344	res = -1;
	345	}
daacc6f9	346
7d60b20b	347	addr += BLOCK_SIZE;
5f7f3586 L	348	}
5f7f3586 L	349
393b1897 L	350	if (dowrite && !res) {
	351	// res = f_sync(&drv_table[drv].fd);
	352	drv_table[drv].dirty = true;
	353	bg_setstat(handle_cpm_drv_to, 1);
	354	}
	355
daacc6f9	356
5f7f3586	357	if (buserr) {
7d60b20b	358	debug_cpmsd("Bus timeout\n");
5f7f3586 L	359	rc = 0x03;
5f7f3586 L	360	}
5f7f3586 L	361
5f7f3586 L	362	/* send result*/
393b1897	363	msg_cpm_result(subf, rc, res);
5f7f3586 L	364	}
5f7f3586 L	365
72f58822 L	366
	367	const FLASH struct msg_item z80_messages[] =
	368	{
	369	{ 0, /* fct nr. */
89adce76	370	1, 3, /* sub fct nr. from, to */
72f58822 L	371	do_msg_ini_memfifo},
	372	{ 1,
	373	1, 1,
	374	do_msg_char_out},
1a2460dc L	375	{ 1,
	376	2, 2,
	377	do_msg_echo},
5f7f3586 L	378	{ 2,
	379	0, 0,
	380	do_msg_cpm_login},
	381	{ 2,
	382	1, 2,
	383	do_msg_cpm_rw},
72f58822 L	384	{ 0xff, /* end mark */
	385	0, 0,
	386	0},
	387
	388	};
	389
	390
	391
	392
	393	void do_message(int len, uint8_t *msg)
	394	{
	395	uint8_t fct, sub_fct;
	396	int_fast8_t i = 0;
	397
	398	if (len >= 2) {
	399	fct = *msg++;
	400	sub_fct = *msg++;
	401	len -= 2;
	402
89adce76 L	403	while (fct != z80_messages[i].fct) {
	404	if (z80_messages[i].fct == 0xff) {
	405	DBG_P(1, "do_message: Unknown function: %i, %i\n",
	406	fct, sub_fct);
	407	return; /* TODO: unknown message # */
	408	}
8a7decea	409
72f58822	410	++i;
72f58822 L	411	}
	412
	413	while (fct == z80_messages[i].fct) {
8a7decea	414	if (sub_fct >= z80_messages[i].sub_min &&
89adce76	415	sub_fct <= z80_messages[i].sub_max )
72f58822 L	416	break;
	417	++i;
	418	}
	419
	420	if (z80_messages[i].fct != fct) {
	421	DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
	422	fct, sub_fct);
	423	return; /* TODO: unknown message sub# */
	424	}
	425
	426	(z80_messages[i].func)(sub_fct, len, msg);
	427
	428
	429	} else {
	430	/* TODO: error */
	431	DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
	432	}
	433	}
	434
	435
	436
	437	#define CTRBUF_LEN 256
	438
	439	void check_msg_fifo(void)
	440	{
	441	int ch;
	442	static int_fast8_t state;
	443	static int msglen,idx;
	444	static uint8_t buffer[CTRBUF_LEN];
	445
89adce76	446	while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
72f58822 L	447	switch (state) {
72f58822 L	448	case 0: /* wait for start of message */
3531528e	449	if (ch == 0xAE) { /* TODO: magic number */
72f58822 L	450	msglen = 0;
	451	idx = 0;
	452	state = 1;
	453	}
	454	break;
	455	case 1: /* get msg len */
	456	if (ch > 0 && ch <= CTRBUF_LEN) {
	457	msglen = ch;
	458	state = 2;
	459	} else
	460	state = 0;
	461	break;
	462	case 2: /* get message */
	463	buffer[idx++] = ch;
89adce76 L	464	if (idx == msglen) {
	465	do_message(msglen, buffer);
	466	state = 0;
	467	}
	468	break;
	469	}
	470	}
	471	}
	472
	473
	474	int msg_handling(int state)
	475	{
	476	uint8_t pending;
8a7decea L	477
8a7decea L	478	ATOMIC_BLOCK(ATOMIC_FORCEON) {
89adce76 L	479	pending = (Stat & S_MSG_PENDING) != 0;
	480	Stat &= ~S_MSG_PENDING;
	481	}
8a7decea	482
89adce76 L	483	if (pending) {
89adce76 L	484	switch (state) {
1a2460dc	485	case 0: /* need init */
cdc4625b	486	/* Get address of fifo_list */
89adce76	487	z80_bus_cmd(Request);
cdc4625b	488	uint32_t fifo_list = z80_read(0x40) +
89adce76 L	489	((uint16_t) z80_read(0x41) << 8) +
	490	((uint32_t) z80_read(0x42) << 16);
	491	z80_bus_cmd(Release);
cdc4625b L	492	if (fifo_list != 0) {
	493	/* Get address of fifo 0 */
	494	z80_bus_cmd(Request);
	495	uint32_t fifo_addr = z80_read(fifo_list) +
	496	((uint16_t) z80_read(fifo_list+1) << 8) +
	497	((uint32_t) z80_read(fifo_list+2) << 16);
	498	z80_bus_cmd(Release);
	499	if (fifo_addr != 0) {
	500	z80_memfifo_init(fifo_msgin, fifo_addr);
	501	state = 1;
	502	}
89adce76 L	503	}
89adce76 L	504	break;
1a2460dc	505	case 1: /* awaiting messages */
89adce76	506	check_msg_fifo();
72f58822 L	507	break;
	508	}
	509	}
	510
89adce76 L	511	return state;
89adce76 L	512	}
89adce76 L	513
	514
	515	static int handle_msg_handling;
	516
	517	void setup_z180_serv(void)
	518	{
8a7decea	519
89adce76	520	handle_msg_handling = bg_register(msg_handling, 0);
393b1897	521	handle_cpm_drv_to = bg_register(cpm_drv_to, 0);
72f58822 L	522	}
72f58822 L	523
89adce76 L	524	void restart_z180_serv(void)
	525	{
	526	z80_bus_cmd(Request);
	527	z80_write(0x40, 0);
	528	z80_write(0x41, 0);
	529	z80_write(0x42, 0);
	530	z80_bus_cmd(Release);
8a7decea L	531
	532	for (int i = 0; i < NUM_FIFOS; i++)
	533	z80_memfifo_init(i, 0);
89adce76	534	bg_setstat(handle_msg_handling, 0);
5f7f3586	535
89adce76	536	}
72f58822 L	537
	538	/--------------------------------------------------------------------------/
	539
72f58822 L	540	const FLASH uint8_t iniprog[] = {
	541	0xAF, // xor a
	542	0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
	543	0x3E, 0x30, // ld a,030h
	544	0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states
	545	};
	546
	547	const FLASH uint8_t sertest[] = {
	548	0xAF, // xor a
	549	0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
	550	0x3E, 0x30, // ld a,030h
	551	0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
	552	0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0
	553	0xED, 0x39, 0x03, // out0 (cntlb1),a
	554	0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ;
	555	0xED, 0x39, 0x01, // out0 (cntla1),a
	556	0x3E, 0x00, // ld a,0
	557	0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts
	558	0xED, 0x38, 0x05, //l0:in0 a,(stat1)
	559	0xE6, 0x80, // and 80h
	560	0x28, 0xF9, // jr z,l0
	561	0xED, 0x00, 0x09, // in0 b,(rdr1)
	562	0xED, 0x38, 0x05, //l1:in0 a,(stat1)
	563	0xE6, 0x02, // and 02h
	564	0x28, 0xF9, // jr z,l1
	565	0xED, 0x01, 0x07, // out0 (tdr1),b
	566	0x18, 0xEA, // jr l0
	567	};
	568
	569	const FLASH uint8_t test1[] = {
	570	0xAF, // xor a
	571	0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
	572	0x3E, 0x30, // ld a,030h
	573	0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
	574	0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers
	575	0x06, 0x08, // ld b,dmct_e-dmclrt
	576	0x0E, 0x20, // ld c,sar0l
8a7decea	577	0xED, 0x93, // otimr
72f58822 L	578	0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst
72f58822 L	579	0xED, 0x39, 0x31, // out0 (dmode),a ;
8a7decea	580	0x3E, 0x62, // ld a,062h ;enable dma0,
72f58822 L	581	0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k
72f58822 L	582	0x18, 0xFB, // jr cl_1 ;
8a7decea	583	0x00, 0x00, //dmclrt: dw 0 ;src (inc)
72f58822 L	584	0x00, // db 0 ;src
	585	0x00, 0x00, // dw 0 ;dst (inc),
	586	0x00, // db 0 ;dst
	587	0x00, 0x00, // dw 0 ;count (64k)
	588	};