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Commit | Line | Data |
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1 | page 255\r | |
2 | .z80\r | |
3 | \r | |
4 | extrn ddtz,bpent\r | |
5 | extrn $stack\r | |
6 | extrn charini,?const,?conin\r | |
7 | extrn ?cono,?conos\r | |
8 | extrn romend\r | |
9 | \r | |
10 | \r | |
11 | global iobyte\r | |
12 | global isv_sw\r | |
13 | \r | |
14 | include config.inc\r | |
15 | if CPU_Z180\r | |
16 | include z180reg.inc\r | |
17 | include z180.lib\r | |
18 | endif\r | |
19 | \r | |
20 | \r | |
21 | \r | |
22 | \r | |
23 | ;----------------------------------------------------------------------\r | |
24 | \r | |
25 | cseg\r | |
26 | romstart equ $\r | |
27 | \r | |
28 | org romstart+0\r | |
29 | jp start\r | |
30 | \r | |
31 | iobyte: db 2\r | |
32 | \r | |
33 | ; restart vectors\r | |
34 | \r | |
35 | rsti defl 1\r | |
36 | rept 7\r | |
37 | org 8*rsti + romstart\r | |
38 | jp bpent\r | |
39 | rsti defl rsti+1\r | |
40 | endm\r | |
41 | \r | |
42 | ;----------------------------------------------------------------------\r | |
43 | ; Config space\r | |
44 | ;\r | |
45 | \r | |
46 | org romstart+40h\r | |
47 | \r | |
48 | dw 0\r | |
49 | db 0\r | |
50 | \r | |
51 | \r | |
52 | if ROMSYS\r | |
53 | $crom: defb c$rom ;\r | |
54 | else\r | |
55 | db 0 ;\r | |
56 | endif\r | |
57 | \r | |
58 | INIWAITS defl CWAITIO\r | |
59 | if ROMSYS\r | |
60 | INIWAITS defl INIWAITS+CWAITROM\r | |
61 | endif\r | |
62 | \r | |
63 | ;----------------------------------------------------------------------\r | |
64 | \r | |
65 | org romstart+50h\r | |
66 | start:\r | |
67 | jp cstart\r | |
68 | jp wstart\r | |
69 | jp ?const\r | |
70 | jp ?conin\r | |
71 | jp ?cono\r | |
72 | jp ?conos\r | |
73 | jp charini\r | |
74 | \r | |
75 | ;----------------------------------------------------------------------\r | |
76 | \r | |
77 | hwini0:\r | |
78 | if CPU_Z180\r | |
79 | db 3 ;count\r | |
80 | db rcr,CREFSH ;configure DRAM refresh\r | |
81 | db dcntl,INIWAITS ;wait states\r | |
82 | db cbr,SYS$CBR\r | |
83 | db cbar,SYS$CBAR\r | |
84 | endif\r | |
85 | db 0\r | |
86 | \r | |
87 | if CPU_Z180\r | |
88 | dmclrt: ;clear ram per dma\r | |
89 | db dmct_e-dmclrt-2 ;\r | |
90 | db sar0l ;first port\r | |
91 | dw nullbyte ;src (fixed)\r | |
92 | nullbyte:\r | |
93 | db 000h ;src\r | |
94 | dw romend ;dst (inc), start after "rom" code\r | |
95 | db 00h ;dst\r | |
96 | dw 0-romend ;count (64k)\r | |
97 | dmct_e:\r | |
98 | db 0\r | |
99 | endif\r | |
100 | \r | |
101 | \r | |
102 | cstart:\r | |
103 | if CPU_Z180\r | |
104 | \r | |
105 | push af\r | |
106 | in0 a,(itc) ;Illegal opcode trap?\r | |
107 | jp m,??st01\r | |
108 | ld a,i ;I register == 0 ?\r | |
109 | jr z,hw_reset ; yes, harware reset\r | |
110 | \r | |
111 | ??st01:\r | |
112 | ; TODO: SYS$CBR\r | |
113 | ld a,(syscbr)\r | |
114 | out0 (cbr),a\r | |
115 | pop af ;restore registers\r | |
116 | jp bpent ;\r | |
117 | \r | |
118 | hw_reset:\r | |
119 | di ;0058\r | |
120 | ld a,CREFSH\r | |
121 | out0 (rcr),a ; configure DRAM refresh\r | |
122 | ld a,CWAITIO\r | |
123 | out0 (dcntl),a ; wait states\r | |
124 | \r | |
125 | ld a,M_NCD ;No Clock Divide\r | |
126 | out0 (ccr),a\r | |
127 | ; ld a,M_X2CM ;X2 Clock Multiplier\r | |
128 | ; out0 (cmr),a\r | |
129 | else\r | |
130 | di\r | |
131 | xor a\r | |
132 | ld (@cbnk),a\r | |
133 | endif\r | |
134 | \r | |
135 | ; check warm start mark\r | |
136 | \r | |
137 | ld ix,mark_55AA ; top of common area\r | |
138 | ld a,0aah ;\r | |
139 | cp (ix+000h) ;\r | |
140 | jr nz,kstart ;\r | |
141 | cp (ix+002h) ;\r | |
142 | jr nz,kstart ;\r | |
143 | cpl ;\r | |
144 | cp (ix+001h) ;\r | |
145 | jr nz,kstart ;\r | |
146 | cp (ix+003h) ;\r | |
147 | jr nz,kstart ;\r | |
148 | ld sp,$stack ; mark found, check\r | |
149 | jp z,wstart ; check ok,\r | |
150 | \r | |
151 | ; ram not ok, initialize -- kstart --\r | |
152 | \r | |
153 | kstart:\r | |
154 | if CPU_Z180\r | |
155 | ld a,SYS$CBR\r | |
156 | out0 (cbr),a\r | |
157 | ld a,SYS$CBAR\r | |
158 | out0 (cbar),a\r | |
159 | endif\r | |
160 | \r | |
161 | ld sp,$stack ;01e1\r | |
162 | \r | |
163 | ; Clear RAM using DMA0\r | |
164 | \r | |
165 | if CPU_Z180\r | |
166 | if 0\r | |
167 | \r | |
168 | ld hl,dmclrt ;load DMA registers\r | |
169 | call ioiniml\r | |
170 | ld a,0cbh ;01ef dst +1, src fixed, burst\r | |
171 | out0 (dmode),a ;01f1\r | |
172 | \r | |
173 | ld b,512/64\r | |
174 | ld a,062h ;01f4 enable dma0,\r | |
175 | ??cl_1:\r | |
176 | out0 (dstat),a ;01f9 clear (up to) 64k\r | |
177 | djnz ??cl_1 ; end of RAM?\r | |
178 | \r | |
179 | endif\r | |
180 | endif\r | |
181 | \r | |
182 | ld hl,055AAh ;set warm start mark\r | |
183 | ld (mark_55AA),hl\r | |
184 | ld (mark_55AA+2),hl\r | |
185 | \r | |
186 | ; -- wstart --\r | |
187 | \r | |
188 | wstart:\r | |
189 | call sysram_init\r | |
190 | call ivtab_init\r | |
191 | if CPU_Z180\r | |
192 | ; call prt0_init\r | |
193 | endif\r | |
194 | \r | |
195 | call charini\r | |
196 | call bufferinit\r | |
197 | \r | |
198 | if CPU_Z80\r | |
199 | ld a,0\r | |
200 | call selbnk\r | |
201 | endif\r | |
202 | \r | |
203 | ld a,INIDONEVAL ;tell others (CP/M) that hardware and fifos\r | |
204 | ld (INIDONE),a ; are allready initialized\r | |
205 | \r | |
206 | im 2\r | |
207 | ei\r | |
208 | \r | |
209 | call ?const\r | |
210 | call ?const\r | |
211 | or a\r | |
212 | call nz,?conin\r | |
213 | \r | |
214 | if CPU_Z180\r | |
215 | ld e,0 ;Sys$Bank\r | |
216 | else\r | |
217 | ; TODO:\r | |
218 | endif\r | |
219 | jp ddtz\r | |
220 | \r | |
221 | \r | |
222 | if CPU_Z180\r | |
223 | ; TODO: SYS$CBR\r | |
224 | syscbr: db 0\r | |
225 | endif\r | |
226 | \r | |
227 | ;\r | |
228 | ;----------------------------------------------------------------------\r | |
229 | ;\r | |
230 | \r | |
231 | global buf.init\r | |
232 | \r | |
233 | buf.init:\r | |
234 | ld (ix+o.in_idx),0\r | |
235 | ld (ix+o.out_idx),0\r | |
236 | ld (ix+o.mask),a\r | |
237 | \r | |
238 | ld a,(ix+o.id)\r | |
239 | cp 4\r | |
240 | ret nc\r | |
241 | \r | |
242 | push de\r | |
243 | push hl\r | |
244 | ld hl,fifo_list\r | |
245 | push hl ;save fifo_list\r | |
246 | ld e,a\r | |
247 | ld d,0\r | |
248 | add hl,de\r | |
249 | add hl,de\r | |
250 | add hl,de\r | |
251 | push ix\r | |
252 | pop de\r | |
253 | ; TODO: address translation\r | |
254 | ld (hl),e\r | |
255 | inc hl\r | |
256 | ld (hl),d\r | |
257 | pop hl ;get fifo_list back\r | |
258 | or a\r | |
259 | jr nz,bufi_ex\r | |
260 | \r | |
261 | ld (040h),hl\r | |
262 | ld (040h+2),a\r | |
263 | bufi_ex:\r | |
264 | pop hl\r | |
265 | pop de\r | |
266 | \r | |
267 | ret\r | |
268 | \r | |
269 | \r | |
270 | fifo_list:\r | |
271 | rept 4\r | |
272 | dw 0\r | |
273 | db 0\r | |
274 | endm\r | |
275 | \r | |
276 | ;----------------------------------------------------------------------\r | |
277 | \r | |
278 | extrn msginit,msg.sout\r | |
279 | extrn mtx.fifo,mrx.fifo\r | |
280 | extrn co.fifo,ci.fifo\r | |
281 | \r | |
282 | \r | |
283 | bufferinit:\r | |
284 | if CPU_Z180\r | |
285 | call msginit\r | |
286 | \r | |
287 | ld hl,buffers\r | |
288 | ld b,buftablen\r | |
289 | bfi_1:\r | |
290 | ld a,(hl)\r | |
291 | inc hl\r | |
292 | ld (bufdat+0),a\r | |
293 | ld e,(hl)\r | |
294 | inc hl\r | |
295 | ld d,(hl)\r | |
296 | inc hl\r | |
297 | ex de,hl\r | |
298 | \r | |
299 | or a\r | |
300 | jr nz,bfi_2\r | |
301 | ; call hwl2phy\r | |
302 | ; ld (40h+0),hl\r | |
303 | ; ld (40h+2),a\r | |
304 | out (AVRINT5),a\r | |
305 | jr bfi_3\r | |
306 | bfi_2:\r | |
307 | call hwl2phy\r | |
308 | ld (bufdat+1),hl\r | |
309 | ld (bufdat+3),a\r | |
310 | ld hl,inimsg\r | |
311 | call msg.sout\r | |
312 | bfi_3:\r | |
313 | ex de,hl\r | |
314 | djnz bfi_1\r | |
315 | ret\r | |
316 | \r | |
317 | else ;CPU_Z180\r | |
318 | \r | |
319 | call msginit\r | |
320 | \r | |
321 | ld hl,buffers\r | |
322 | ld b,buftablen\r | |
323 | bfi_1:\r | |
324 | ld a,(hl)\r | |
325 | inc hl\r | |
326 | ld (bufdat+0),a\r | |
327 | ld e,(hl)\r | |
328 | inc hl\r | |
329 | ld d,(hl)\r | |
330 | inc hl\r | |
331 | ex de,hl\r | |
332 | \r | |
333 | or a\r | |
334 | jr nz,bfi_2\r | |
335 | \r | |
336 | ld a,(@cbnk)\r | |
337 | call bnk2phy\r | |
338 | \r | |
339 | ld (40h+0),hl\r | |
340 | ld (40h+2),a\r | |
341 | out (AVRINT5),a\r | |
342 | jr bfi_3\r | |
343 | bfi_2:\r | |
344 | \r | |
345 | ld a,(@cbnk)\r | |
346 | call bnk2phy\r | |
347 | \r | |
348 | ld (bufdat+1),hl\r | |
349 | ld (bufdat+3),a\r | |
350 | ld hl,inimsg\r | |
351 | call msg.sout\r | |
352 | bfi_3:\r | |
353 | ex de,hl\r | |
354 | djnz bfi_1\r | |
355 | ret\r | |
356 | endif\r | |
357 | \r | |
358 | buffers:\r | |
359 | db 0\r | |
360 | dw mtx.fifo\r | |
361 | db 1\r | |
362 | dw mrx.fifo\r | |
363 | db 2\r | |
364 | dw ci.fifo\r | |
365 | db 3\r | |
366 | dw co.fifo\r | |
367 | buftablen equ ($ - buffers)/3\r | |
368 | \r | |
369 | inimsg:\r | |
370 | db inimsg_e - $ -1\r | |
371 | db 0AEh\r | |
372 | db inimsg_e - $ -1\r | |
373 | db 0\r | |
374 | bufdat:\r | |
375 | db 0\r | |
376 | dw 0\r | |
377 | db 0\r | |
378 | inimsg_e:\r | |
379 | \r | |
380 | \r | |
381 | ;\r | |
382 | ;----------------------------------------------------------------------\r | |
383 | ;\r | |
384 | \r | |
385 | sysram_init:\r | |
386 | ld hl,sysramw\r | |
387 | ld de,topcodsys\r | |
388 | ld bc,sysrame-sysramw\r | |
389 | ldir\r | |
390 | \r | |
391 | ret\r | |
392 | \r | |
393 | ;----------------------------------------------------------------------\r | |
394 | \r | |
395 | ivtab_init:\r | |
396 | ld hl,ivtab ;\r | |
397 | ld a,h ;\r | |
398 | ld i,a ;\r | |
399 | if CPU_Z180\r | |
400 | out0 (il),l ;\r | |
401 | endif\r | |
402 | \r | |
403 | ; Let all vectors point to spurious int routines.\r | |
404 | \r | |
405 | ld d,high sp.int0\r | |
406 | ld a,low sp.int0\r | |
407 | ld b,9\r | |
408 | ivt_i1:\r | |
409 | ld (hl),a\r | |
410 | inc l\r | |
411 | ld (hl),d\r | |
412 | inc l\r | |
413 | add a,sp.int.len\r | |
414 | djnz ivt_i1\r | |
415 | ret\r | |
416 | \r | |
417 | ;----------------------------------------------------------------------\r | |
418 | \r | |
419 | ; Reload value for 10 ms Int. (0.1KHz):\r | |
420 | ; tc10ms = phi/prescale/0.1KHz = phi / (prescale/10)\r | |
421 | \r | |
422 | PRT_TC10MS equ 18432 / (PRT_PRE/10)\r | |
423 | \r | |
424 | \r | |
425 | if CPU_Z180\r | |
426 | prt0_init:\r | |
427 | ld a,i\r | |
428 | ld h,a\r | |
429 | in0 a,(il)\r | |
430 | and 0E0h\r | |
431 | or IV$PRT0\r | |
432 | ld l,a\r | |
433 | ld (hl),low iprt0\r | |
434 | inc hl\r | |
435 | ld (hl),high iprt0\r | |
436 | ld hl,prt0itab\r | |
437 | call ioiniml\r | |
438 | ret\r | |
439 | \r | |
440 | prt0itab:\r | |
441 | db prt0it_e-prt0itab-2\r | |
442 | db tmdr0l\r | |
443 | dw PRT_TC10MS\r | |
444 | dw PRT_TC10MS\r | |
445 | db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.\r | |
446 | prt0it_e:\r | |
447 | db 0\r | |
448 | endif\r | |
449 | \r | |
450 | \r | |
451 | ;\r | |
452 | ;----------------------------------------------------------------------\r | |
453 | ;\r | |
454 | \r | |
455 | if CPU_Z180\r | |
456 | io.ini:\r | |
457 | if 0\r | |
458 | push bc\r | |
459 | ld b,0 ;high byte port adress\r | |
460 | ioi_nxt:\r | |
461 | ld a,(hl) ;count\r | |
462 | inc hl\r | |
463 | or a\r | |
464 | jr z,ioi_e\r | |
465 | \r | |
466 | ld c,(hl) ;port address\r | |
467 | inc hl\r | |
468 | ioi_r:\r | |
469 | outi\r | |
470 | inc b ;outi decrements b\r | |
471 | dec a\r | |
472 | jr nz,ioi_r\r | |
473 | jr ioi_nxt\r | |
474 | ioi_e:\r | |
475 | pop bc\r | |
476 | ret\r | |
477 | \r | |
478 | else ;(if 1/0)\r | |
479 | \r | |
480 | push bc\r | |
481 | jr ioi_nxt\r | |
482 | ioi_l:\r | |
483 | ld c,(hl) ;port address\r | |
484 | inc hl\r | |
485 | inc c\r | |
486 | ioi_r:\r | |
487 | dec c ;otim increments c\r | |
488 | otim\r | |
489 | jr z,ioi_r\r | |
490 | ioi_nxt:\r | |
491 | ld b,(hl) ;count\r | |
492 | inc hl\r | |
493 | inc b ;stop if count == 0\r | |
494 | djnz ioi_l\r | |
495 | pop bc\r | |
496 | ret\r | |
497 | \r | |
498 | endif ;(1/0)\r | |
499 | \r | |
500 | else\r | |
501 | \r | |
502 | io.ini:\r | |
503 | push bc\r | |
504 | jr ioi_nxt\r | |
505 | ioi_l:\r | |
506 | ld c,(hl) ;port address\r | |
507 | inc hl\r | |
508 | otir\r | |
509 | ioi_nxt:\r | |
510 | ld b,(hl) ;count\r | |
511 | inc hl\r | |
512 | inc b\r | |
513 | djnz ioi_l\r | |
514 | endif\r | |
515 | pop bc\r | |
516 | ret\r | |
517 | \r | |
518 | ;----------------------------------------------------------------------\r | |
519 | \r | |
520 | if CPU_Z180\r | |
521 | \r | |
522 | global ioiniml\r | |
523 | \r | |
524 | ioiniml:\r | |
525 | push bc\r | |
526 | xor a\r | |
527 | ioml_lp:\r | |
528 | ld b,(hl)\r | |
529 | inc hl\r | |
530 | cp b\r | |
531 | jr z,ioml_e\r | |
532 | \r | |
533 | ld c,(hl)\r | |
534 | inc hl\r | |
535 | otimr\r | |
536 | jr ioml_lp\r | |
537 | ioml_e:\r | |
538 | pop bc\r | |
539 | ret z\r | |
540 | endif\r | |
541 | \r | |
542 | io.ini.l:\r | |
543 | ;\r | |
544 | \r | |
545 | \r | |
546 | \r | |
547 | ;----------------------------------------------------------------------\r | |
548 | ;\r | |
549 | if CPU_Z180\r | |
550 | \r | |
551 | ;--------------------------------------------------------------------\r | |
552 | ; Return the BBR value for the given bank number\r | |
553 | ;\r | |
554 | ; in a: Bank number\r | |
555 | ; out a: bbr value\r | |
556 | \r | |
557 | bnk2log:\r | |
558 | or a ;\r | |
559 | ret z ; Bank 0 is at physical address 0\r | |
560 | \r | |
561 | push bc ;\r | |
562 | ld b,a ;\r | |
563 | ld c,CA ;\r | |
564 | mlt bc ;\r | |
565 | ld a,c ;\r | |
566 | add a,10h ;\r | |
567 | pop bc ;\r | |
568 | ret ;\r | |
569 | \r | |
570 | ;--------------------------------------------------------------\r | |
571 | \r | |
572 | ;in hl: Log. Address\r | |
573 | ; a: Bank number\r | |
574 | ;\r | |
575 | ;out ahl: Phys. (linear) Address\r | |
576 | \r | |
577 | \r | |
578 | bnk2phy:\r | |
579 | call bnk2log\r | |
580 | ; fall thru\r | |
581 | \r | |
582 | ;--------------------------------------------------------------\r | |
583 | ;\r | |
584 | ; hl: Log. Address\r | |
585 | ; a: Bank base (bbr)\r | |
586 | ;\r | |
587 | ; 2 0 0\r | |
588 | ; 0 6 8 0\r | |
589 | ; hl hhhhhhhhllllllll\r | |
590 | ; a + bbbbbbbb\r | |
591 | ;\r | |
592 | ; OP: ahl = (a<<12) + (h<<8) + l\r | |
593 | ;\r | |
594 | ;out ahl: Phys. (linear) Address\r | |
595 | \r | |
596 | log2phy:\r | |
597 | push bc ;\r | |
598 | l2p_i:\r | |
599 | ld c,a ;\r | |
600 | ld b,16 ;\r | |
601 | mlt bc ; bc = a<<4\r | |
602 | ld a,c ;\r | |
603 | add a,h ;\r | |
604 | ld h,a ;\r | |
605 | ld a,b ;\r | |
606 | adc a,0 ;\r | |
607 | pop bc ;\r | |
608 | ret ;\r | |
609 | \r | |
610 | ;--------------------------------------------------------------\r | |
611 | ;\r | |
612 | ; hl: Log. Address\r | |
613 | ;\r | |
614 | ;\r | |
615 | ; OP: ahl = (bankbase<<12) + (d<<8) + e\r | |
616 | ;\r | |
617 | ;out ahl: Phys. (linear) Address\r | |
618 | \r | |
619 | \r | |
620 | hwl2phy:\r | |
621 | push bc ;\r | |
622 | in0 c,(cbar) ;\r | |
623 | ld a,h ;\r | |
624 | or 00fh ; log. addr in common1?\r | |
625 | cp c\r | |
626 | jr c,hlp_1\r | |
627 | \r | |
628 | in0 a,(cbr) ; yes, cbr is address base\r | |
629 | jr hl2p_x\r | |
630 | hlp_1:\r | |
631 | ld b,16 ; log. address in baked area?\r | |
632 | mlt bc\r | |
633 | ld a,h\r | |
634 | cp c\r | |
635 | jr c,hlp_2\r | |
636 | in0 a,(bbr) ; yes, bbr is address base\r | |
637 | jr hl2p_x\r | |
638 | hlp_2:\r | |
639 | xor a ; common1\r | |
640 | hl2p_x:\r | |
641 | jr nz,l2p_i\r | |
642 | \r | |
643 | pop bc ; bank part is 0, no translation\r | |
644 | ret ;\r | |
645 | \r | |
646 | \r | |
647 | \r | |
648 | else ;CPU_Z180\r | |
649 | \r | |
650 | ;----------------------------------------------------------------------\r | |
651 | ;\r | |
652 | \r | |
653 | bnk2phy:\r | |
654 | sla h\r | |
655 | jr nc,b2p_1 ;A15=1 --> common\r | |
656 | ld a,3\r | |
657 | b2p_1:\r | |
658 | srl a\r | |
659 | rr h\r | |
660 | ret\r | |
661 | \r | |
662 | endif\r | |
663 | \r | |
664 | ;--------------------------------------------------------------\r | |
665 | ;\r | |
666 | ;return:\r | |
667 | ; hl = hl + a\r | |
668 | ; Flags undefined\r | |
669 | ;\r | |
670 | \r | |
671 | add_hl_a:\r | |
672 | add a,l\r | |
673 | ld l,a\r | |
674 | ret nc\r | |
675 | inc h\r | |
676 | ret\r | |
677 | \r | |
678 | ; ---------------------------------------------------------\r | |
679 | \r | |
680 | sysramw:\r | |
681 | \r | |
682 | .phase isvsw_loc\r | |
683 | topcodsys:\r | |
684 | \r | |
685 | ; Trampoline for interrupt routines in banked ram.\r | |
686 | ; Switch stack pointer to "system" stack in top ram\r | |
687 | ; Save cbar\r | |
688 | \r | |
689 | isv_sw: ;\r | |
690 | ex (sp),hl ;save hl, 'return adr' in hl\r | |
691 | push de ;\r | |
692 | push af ;\r | |
693 | ex de,hl ;'return address' in de\r | |
694 | ld hl,0 ;\r | |
695 | add hl,sp ;\r | |
696 | ld a,h ;\r | |
697 | cp 0f8h ;\r | |
698 | jr nc,isw_1 ;stack allready in top ram\r | |
699 | ld sp,$stack ;\r | |
700 | isw_1:\r | |
701 | push hl ;save user stack pointer\r | |
702 | in0 h,(cbar) ;\r | |
703 | push hl ;\r | |
704 | ld a,SYS$CBAR ;\r | |
705 | out0 (cbar),a ;\r | |
706 | ex de,hl ;\r | |
707 | ld e,(hl) ;\r | |
708 | inc hl ;\r | |
709 | ld d,(hl) ;\r | |
710 | ex de,hl ;\r | |
711 | push bc ;\r | |
712 | call jphl ;\r | |
713 | \r | |
714 | pop bc ;\r | |
715 | pop hl ;\r | |
716 | out0 (cbar),h ;\r | |
717 | pop hl ;\r | |
718 | ld sp,hl ;\r | |
719 | pop af ;\r | |
720 | pop de ;\r | |
721 | pop hl ;\r | |
722 | ei ;\r | |
723 | ret ;\r | |
724 | jphl:\r | |
725 | jp (hl) ;\r | |
726 | \r | |
727 | ; ---------------------------------------------------------\r | |
728 | \r | |
729 | if CPU_Z180\r | |
730 | \r | |
731 | iprt0:\r | |
732 | push af\r | |
733 | push hl\r | |
734 | in0 a,(tcr)\r | |
735 | in0 a,(tmdr0l)\r | |
736 | in0 a,(tmdr0h)\r | |
737 | ld a,(tim_ms)\r | |
738 | inc a\r | |
739 | cp 100\r | |
740 | jr nz,iprt_1\r | |
741 | xor a\r | |
742 | ld hl,(tim_s)\r | |
743 | inc hl\r | |
744 | ld (tim_s),hl\r | |
745 | iprt_1:\r | |
746 | ld (tim_ms),a\r | |
747 | pop hl\r | |
748 | pop af\r | |
749 | ei\r | |
750 | ret\r | |
751 | \r | |
752 | endif\r | |
753 | \r | |
754 | ; ---------------------------------------------------------\r | |
755 | \r | |
756 | sp.int0:\r | |
757 | ld a,0d0h\r | |
758 | jr sp.i.1\r | |
759 | sp.int.len equ $-sp.int0\r | |
760 | ld a,0d1h\r | |
761 | jr sp.i.1\r | |
762 | ld a,0d2h\r | |
763 | jr sp.i.1\r | |
764 | ld a,0d3h\r | |
765 | jr sp.i.1\r | |
766 | ld a,0d4h\r | |
767 | jr sp.i.1\r | |
768 | ld a,0d5h\r | |
769 | jr sp.i.1\r | |
770 | ld a,0d6h\r | |
771 | jr sp.i.1\r | |
772 | ld a,0d7h\r | |
773 | jr sp.i.1\r | |
774 | ld a,0d8h\r | |
775 | sp.i.1:\r | |
776 | ; out (80h),a\r | |
777 | halt\r | |
778 | \r | |
779 | ; ---------------------------------------------------------\r | |
780 | \r | |
781 | if CPU_Z80\r | |
782 | \r | |
783 | ; Get IFF2\r | |
784 | ; This routine may not be loaded in page zero\r | |
785 | ;\r | |
786 | ; return Carry clear, if INTs are enabled.\r | |
787 | ;\r | |
788 | global getiff\r | |
789 | getiff:\r | |
790 | xor a ;clear accu and carry\r | |
791 | push af ;stack bottom := 00xxh\r | |
792 | pop af\r | |
793 | ld a,i ;P flag := IFF2\r | |
794 | ret pe ;exit carry clear, if enabled\r | |
795 | dec sp\r | |
796 | dec sp ;has stack bottom been overwritten?\r | |
797 | pop af\r | |
798 | and a ;if not 00xxh, INTs were\r | |
799 | ret nz ;actually enabled\r | |
800 | scf ;Otherwise, they really are disabled\r | |
801 | ret\r | |
802 | \r | |
803 | ;----------------------------------------------------------------------\r | |
804 | \r | |
805 | global selbnk\r | |
806 | \r | |
807 | ; a: bank (0..2)\r | |
808 | \r | |
809 | selbnk:\r | |
810 | push bc\r | |
811 | ld c,a\r | |
812 | call getiff\r | |
813 | push af\r | |
814 | \r | |
815 | ld a,c\r | |
816 | di\r | |
817 | ld (@cbnk),a\r | |
818 | ld a,5\r | |
819 | out (SIOAC),a\r | |
820 | ld a,(mm_sio0)\r | |
821 | rla\r | |
822 | srl c\r | |
823 | rra\r | |
824 | out (SIOAC),a\r | |
825 | ld (mm_sio0),a\r | |
826 | \r | |
827 | ld a,5\r | |
828 | out (SIOBC),a\r | |
829 | ld a,(mm_sio1)\r | |
830 | rla\r | |
831 | srl c\r | |
832 | rra\r | |
833 | out (SIOBC),a\r | |
834 | ld (mm_sio1),a\r | |
835 | pop af\r | |
836 | pop bc\r | |
837 | ret c ;INTs were disabled\r | |
838 | ei\r | |
839 | ret\r | |
840 | \r | |
841 | ;----------------------------------------------------------------------\r | |
842 | \r | |
843 | ; c: bank (0..2)\r | |
844 | \r | |
845 | if 0\r | |
846 | \r | |
847 | selbnk:\r | |
848 | ld a,(@cbnk)\r | |
849 | xor c\r | |
850 | and 3\r | |
851 | ret z ;no change\r | |
852 | \r | |
853 | call getiff\r | |
854 | push af\r | |
855 | ld a,c\r | |
856 | di\r | |
857 | ld (@cbnk),a\r | |
858 | ld a,5\r | |
859 | out (SIOAC),a\r | |
860 | ld a,(mm_sio0)\r | |
861 | rla\r | |
862 | srl c\r | |
863 | rra\r | |
864 | out (SIOAC),a\r | |
865 | ld (mm_sio0),a\r | |
866 | \r | |
867 | ld a,5\r | |
868 | out (SIOBC),a\r | |
869 | ld a,(mm_sio1)\r | |
870 | rla\r | |
871 | srl c\r | |
872 | rra\r | |
873 | out (SIOBC),a\r | |
874 | ld (mm_sio1),a\r | |
875 | pop af\r | |
876 | ret nc ;INTs were disabled\r | |
877 | ei\r | |
878 | ret\r | |
879 | \r | |
880 | endif\r | |
881 | \r | |
882 | ;----------------------------------------------------------------------\r | |
883 | \r | |
884 | if 0\r | |
885 | ex af,af'\r | |
886 | push af\r | |
887 | ex af,af'\r | |
888 | \r | |
889 | rra\r | |
890 | jr nc,stbk1\r | |
891 | ex af,af'\r | |
892 | ld a,5\r | |
893 | out (SIOAC),a\r | |
894 | ld a,(mm_sio0)\r | |
895 | rla\r | |
896 | srl c\r | |
897 | rra\r | |
898 | out (SIOAC),a\r | |
899 | ld (mm_sio1),a\r | |
900 | ex af,af'\r | |
901 | \r | |
902 | stbk1:\r | |
903 | rra\r | |
904 | jr nc,stbk2\r | |
905 | ex af,af'\r | |
906 | ld a,5\r | |
907 | out (SIOBC),a\r | |
908 | ld a,(mm_sio1)\r | |
909 | rla\r | |
910 | srl c\r | |
911 | rra\r | |
912 | out (SIOBC),a\r | |
913 | ld (mm_sio1),a\r | |
914 | ex af,af'\r | |
915 | \r | |
916 | stbk2:\r | |
917 | endif\r | |
918 | \r | |
919 | global @cbnk\r | |
920 | global mm_sio0, mm_sio1\r | |
921 | \r | |
922 | @cbnk: db 0 ; current bank (0..2)\r | |
923 | mm_sio0:\r | |
924 | ds 1\r | |
925 | mm_sio1:\r | |
926 | ds 1\r | |
927 | \r | |
928 | \r | |
929 | endif\r | |
930 | \r | |
931 | ;----------------------------------------------------------------------\r | |
932 | \r | |
933 | curph defl $\r | |
934 | .dephase\r | |
935 | sysrame:\r | |
936 | .phase curph\r | |
937 | tim_ms: db 0\r | |
938 | tim_s: dw 0\r | |
939 | .dephase\r | |
940 | \r | |
941 | ;-----------------------------------------------------\r | |
942 | \r | |
943 | \r | |
944 | cseg\r | |
945 | \r | |
946 | ;.phase 0ffc0h\r | |
947 | ;ivtab equ 0ffc0h ; 0ffc0h ;int vector table\r | |
948 | ;.dephase\r | |
949 | \r | |
950 | ;.phase 0fffah\r | |
951 | mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack\r | |
952 | ;ds 4\r | |
953 | ;.dephase\r | |
954 | \r | |
955 | \r | |
956 | end\r |