]> cloudbase.mooo.com Git - z180-stamp.git/blob - z180/init.180
projects / z180-stamp.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Server: Time and Date support
[z180-stamp.git] / z180 / init.180
1 page 255
2 .z80
3
4 extrn ddtz,bpent
5 extrn $stack
6 extrn charini,?const,?conin
7 extrn ?cono,?conos
8 extrn romend
9
10
11 global iobyte
12 global isv_sw
13
14 include config.inc
15 if CPU_Z180
16 include z180reg.inc
17 include z180.lib
18 endif
19
20
21
22
23 ;----------------------------------------------------------------------
24
25 cseg
26 romstart equ $
27
28 org romstart+0
29 jp start
30
31 iobyte: db 2
32
33 ; restart vectors
34
35 rsti defl 1
36 rept 7
37 org 8*rsti + romstart
38 jp bpent
39 rsti defl rsti+1
40 endm
41
42 ;----------------------------------------------------------------------
43 ; Config space
44 ;
45
46 org romstart+40h
47
48 dw 0
49 db 0
50
51
52 if ROMSYS
53 $crom: defb c$rom ;
54 else
55 db 0 ;
56 endif
57
58 INIWAITS defl CWAITIO
59 if ROMSYS
60 INIWAITS defl INIWAITS+CWAITROM
61 endif
62
63 ;----------------------------------------------------------------------
64
65 org romstart+50h
66 start:
67 jp cstart
68 jp wstart
69 jp ?const
70 jp ?conin
71 jp ?cono
72 jp ?conos
73 jp charini
74
75 ;----------------------------------------------------------------------
76
77 hwini0:
78 if CPU_Z180
79 db 3 ;count
80 db rcr,CREFSH ;configure DRAM refresh
81 db dcntl,INIWAITS ;wait states
82 db cbr,SYS$CBR
83 db cbar,SYS$CBAR
84 endif
85 db 0
86
87 if CPU_Z180
88 dmclrt: ;clear ram per dma
89 db dmct_e-dmclrt-2 ;
90 db sar0l ;first port
91 dw nullbyte ;src (fixed)
92 nullbyte:
93 db 000h ;src
94 dw romend ;dst (inc), start after "rom" code
95 db 00h ;dst
96 dw 0-romend ;count (64k)
97 dmct_e:
98 db 0
99 endif
100
101
102 cstart:
103 if CPU_Z180
104
105 push af
106 in0 a,(itc) ;Illegal opcode trap?
107 jp m,??st01
108 ld a,i ;I register == 0 ?
109 jr z,hw_reset ; yes, harware reset
110
111 ??st01:
112 ; TODO: SYS$CBR
113 ld a,(syscbr)
114 out0 (cbr),a
115 pop af ;restore registers
116 jp bpent ;
117
118 hw_reset:
119 di ;0058
120 ld a,CREFSH
121 out0 (rcr),a ; configure DRAM refresh
122 ld a,CWAITIO
123 out0 (dcntl),a ; wait states
124
125 ld a,M_NCD ;No Clock Divide
126 out0 (ccr),a
127 ; ld a,M_X2CM ;X2 Clock Multiplier
128 ; out0 (cmr),a
129 else
130 di
131 xor a
132 ld (@cbnk),a
133 endif
134
135 ; check warm start mark
136
137 ld ix,mark_55AA ; top of common area
138 ld a,0aah ;
139 cp (ix+000h) ;
140 jr nz,kstart ;
141 cp (ix+002h) ;
142 jr nz,kstart ;
143 cpl ;
144 cp (ix+001h) ;
145 jr nz,kstart ;
146 cp (ix+003h) ;
147 jr nz,kstart ;
148 ld sp,$stack ; mark found, check
149 jp z,wstart ; check ok,
150
151 ; ram not ok, initialize -- kstart --
152
153 kstart:
154 if CPU_Z180
155 ld a,SYS$CBR
156 out0 (cbr),a
157 ld a,SYS$CBAR
158 out0 (cbar),a
159 endif
160
161 ld sp,$stack ;01e1
162
163 ; Clear RAM using DMA0
164
165 if CPU_Z180
166 if 0
167
168 ld hl,dmclrt ;load DMA registers
169 call ioiniml
170 ld a,0cbh ;01ef dst +1, src fixed, burst
171 out0 (dmode),a ;01f1
172
173 ld b,512/64
174 ld a,062h ;01f4 enable dma0,
175 ??cl_1:
176 out0 (dstat),a ;01f9 clear (up to) 64k
177 djnz ??cl_1 ; end of RAM?
178
179 endif
180 endif
181
182 ld hl,055AAh ;set warm start mark
183 ld (mark_55AA),hl
184 ld (mark_55AA+2),hl
185
186 ; -- wstart --
187
188 wstart:
189 call sysram_init
190 call ivtab_init
191 if CPU_Z180
192 ; call prt0_init
193 endif
194
195 call charini
196 call bufferinit
197
198 if CPU_Z80
199 ld a,0
200 call selbnk
201 endif
202
203 ld a,INIDONEVAL ;tell others (CP/M) that hardware and fifos
204 ld (INIDONE),a ; are allready initialized
205
206 im 2
207 ei
208
209 call ?const
210 call ?const
211 or a
212 call nz,?conin
213
214 if CPU_Z180
215 ld e,0 ;Sys$Bank
216 else
217 ; TODO:
218 endif
219 jp ddtz
220
221
222 if CPU_Z180
223 ; TODO: SYS$CBR
224 syscbr: db 0
225 endif
226
227 ;
228 ;----------------------------------------------------------------------
229 ;
230
231 global buf.init
232
233 buf.init:
234 ld (ix+o.in_idx),0
235 ld (ix+o.out_idx),0
236 ld (ix+o.mask),a
237
238 ld a,(ix+o.id)
239 cp 4
240 ret nc
241
242 push de
243 push hl
244 ld hl,fifo_list
245 push hl ;save fifo_list
246 ld e,a
247 ld d,0
248 add hl,de
249 add hl,de
250 add hl,de
251 push ix
252 pop de
253 ; TODO: address translation
254 ld (hl),e
255 inc hl
256 ld (hl),d
257 pop hl ;get fifo_list back
258 or a
259 jr nz,bufi_ex
260
261 ld (040h),hl
262 ld (040h+2),a
263 bufi_ex:
264 pop hl
265 pop de
266
267 ret
268
269
270 fifo_list:
271 rept 4
272 dw 0
273 db 0
274 endm
275
276 ;----------------------------------------------------------------------
277
278 extrn msginit,msg.sout
279 extrn mtx.fifo,mrx.fifo
280 extrn co.fifo,ci.fifo
281
282
283 bufferinit:
284 if CPU_Z180
285 call msginit
286
287 ld hl,buffers
288 ld b,buftablen
289 bfi_1:
290 ld a,(hl)
291 inc hl
292 ld (bufdat+0),a
293 ld e,(hl)
294 inc hl
295 ld d,(hl)
296 inc hl
297 ex de,hl
298
299 or a
300 jr nz,bfi_2
301 ; call hwl2phy
302 ; ld (40h+0),hl
303 ; ld (40h+2),a
304 out (AVRINT5),a
305 jr bfi_3
306 bfi_2:
307 call hwl2phy
308 ld (bufdat+1),hl
309 ld (bufdat+3),a
310 ld hl,inimsg
311 call msg.sout
312 bfi_3:
313 ex de,hl
314 djnz bfi_1
315 ret
316
317 else ;CPU_Z180
318
319 call msginit
320
321 ld hl,buffers
322 ld b,buftablen
323 bfi_1:
324 ld a,(hl)
325 inc hl
326 ld (bufdat+0),a
327 ld e,(hl)
328 inc hl
329 ld d,(hl)
330 inc hl
331 ex de,hl
332
333 or a
334 jr nz,bfi_2
335
336 ld a,(@cbnk)
337 call bnk2phy
338
339 ld (40h+0),hl
340 ld (40h+2),a
341 out (AVRINT5),a
342 jr bfi_3
343 bfi_2:
344
345 ld a,(@cbnk)
346 call bnk2phy
347
348 ld (bufdat+1),hl
349 ld (bufdat+3),a
350 ld hl,inimsg
351 call msg.sout
352 bfi_3:
353 ex de,hl
354 djnz bfi_1
355 ret
356 endif
357
358 buffers:
359 db 0
360 dw mtx.fifo
361 db 1
362 dw mrx.fifo
363 db 2
364 dw ci.fifo
365 db 3
366 dw co.fifo
367 buftablen equ ($ - buffers)/3
368
369 inimsg:
370 db inimsg_e - $ -1
371 db 0AEh
372 db inimsg_e - $ -1
373 db 0
374 bufdat:
375 db 0
376 dw 0
377 db 0
378 inimsg_e:
379
380
381 ;
382 ;----------------------------------------------------------------------
383 ;
384
385 sysram_init:
386 ld hl,sysramw
387 ld de,topcodsys
388 ld bc,sysrame-sysramw
389 ldir
390
391 ret
392
393 ;----------------------------------------------------------------------
394
395 ivtab_init:
396 ld hl,ivtab ;
397 ld a,h ;
398 ld i,a ;
399 if CPU_Z180
400 out0 (il),l ;
401 endif
402
403 ; Let all vectors point to spurious int routines.
404
405 ld d,high sp.int0
406 ld a,low sp.int0
407 ld b,9
408 ivt_i1:
409 ld (hl),a
410 inc l
411 ld (hl),d
412 inc l
413 add a,sp.int.len
414 djnz ivt_i1
415 ret
416
417 ;----------------------------------------------------------------------
418
419 ; Reload value for 10 ms Int. (0.1KHz):
420 ; tc10ms = phi/prescale/0.1KHz = phi / (prescale/10)
421
422 PRT_TC10MS equ 18432 / (PRT_PRE/10)
423
424
425 if CPU_Z180
426 prt0_init:
427 ld a,i
428 ld h,a
429 in0 a,(il)
430 and 0E0h
431 or IV$PRT0
432 ld l,a
433 ld (hl),low iprt0
434 inc hl
435 ld (hl),high iprt0
436 ld hl,prt0itab
437 call ioiniml
438 ret
439
440 prt0itab:
441 db prt0it_e-prt0itab-2
442 db tmdr0l
443 dw PRT_TC10MS
444 dw PRT_TC10MS
445 db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.
446 prt0it_e:
447 db 0
448 endif
449
450
451 ;
452 ;----------------------------------------------------------------------
453 ;
454
455 if CPU_Z180
456 io.ini:
457 if 0
458 push bc
459 ld b,0 ;high byte port adress
460 ioi_nxt:
461 ld a,(hl) ;count
462 inc hl
463 or a
464 jr z,ioi_e
465
466 ld c,(hl) ;port address
467 inc hl
468 ioi_r:
469 outi
470 inc b ;outi decrements b
471 dec a
472 jr nz,ioi_r
473 jr ioi_nxt
474 ioi_e:
475 pop bc
476 ret
477
478 else ;(if 1/0)
479
480 push bc
481 jr ioi_nxt
482 ioi_l:
483 ld c,(hl) ;port address
484 inc hl
485 inc c
486 ioi_r:
487 dec c ;otim increments c
488 otim
489 jr z,ioi_r
490 ioi_nxt:
491 ld b,(hl) ;count
492 inc hl
493 inc b ;stop if count == 0
494 djnz ioi_l
495 pop bc
496 ret
497
498 endif ;(1/0)
499
500 else
501
502 io.ini:
503 push bc
504 jr ioi_nxt
505 ioi_l:
506 ld c,(hl) ;port address
507 inc hl
508 otir
509 ioi_nxt:
510 ld b,(hl) ;count
511 inc hl
512 inc b
513 djnz ioi_l
514 endif
515 pop bc
516 ret
517
518 ;----------------------------------------------------------------------
519
520 if CPU_Z180
521
522 global ioiniml
523
524 ioiniml:
525 push bc
526 xor a
527 ioml_lp:
528 ld b,(hl)
529 inc hl
530 cp b
531 jr z,ioml_e
532
533 ld c,(hl)
534 inc hl
535 otimr
536 jr ioml_lp
537 ioml_e:
538 pop bc
539 ret z
540 endif
541
542 io.ini.l:
543 ;
544
545
546
547 ;----------------------------------------------------------------------
548 ;
549 if CPU_Z180
550
551 ;--------------------------------------------------------------------
552 ; Return the BBR value for the given bank number
553 ;
554 ; in a: Bank number
555 ; out a: bbr value
556
557 bnk2log:
558 or a ;
559 ret z ; Bank 0 is at physical address 0
560
561 push bc ;
562 ld b,a ;
563 ld c,CA ;
564 mlt bc ;
565 ld a,c ;
566 add a,10h ;
567 pop bc ;
568 ret ;
569
570 ;--------------------------------------------------------------
571
572 ;in hl: Log. Address
573 ; a: Bank number
574 ;
575 ;out ahl: Phys. (linear) Address
576
577
578 bnk2phy:
579 call bnk2log
580 ; fall thru
581
582 ;--------------------------------------------------------------
583 ;
584 ; hl: Log. Address
585 ; a: Bank base (bbr)
586 ;
587 ; 2 0 0
588 ; 0 6 8 0
589 ; hl hhhhhhhhllllllll
590 ; a + bbbbbbbb
591 ;
592 ; OP: ahl = (a<<12) + (h<<8) + l
593 ;
594 ;out ahl: Phys. (linear) Address
595
596 log2phy:
597 push bc ;
598 l2p_i:
599 ld c,a ;
600 ld b,16 ;
601 mlt bc ; bc = a<<4
602 ld a,c ;
603 add a,h ;
604 ld h,a ;
605 ld a,b ;
606 adc a,0 ;
607 pop bc ;
608 ret ;
609
610 ;--------------------------------------------------------------
611 ;
612 ; hl: Log. Address
613 ;
614 ;
615 ; OP: ahl = (bankbase<<12) + (d<<8) + e
616 ;
617 ;out ahl: Phys. (linear) Address
618
619
620 hwl2phy:
621 push bc ;
622 in0 c,(cbar) ;
623 ld a,h ;
624 or 00fh ; log. addr in common1?
625 cp c
626 jr c,hlp_1
627
628 in0 a,(cbr) ; yes, cbr is address base
629 jr hl2p_x
630 hlp_1:
631 ld b,16 ; log. address in baked area?
632 mlt bc
633 ld a,h
634 cp c
635 jr c,hlp_2
636 in0 a,(bbr) ; yes, bbr is address base
637 jr hl2p_x
638 hlp_2:
639 xor a ; common1
640 hl2p_x:
641 jr nz,l2p_i
642
643 pop bc ; bank part is 0, no translation
644 ret ;
645
646
647
648 else ;CPU_Z180
649
650 ;----------------------------------------------------------------------
651 ;
652
653 bnk2phy:
654 sla h
655 jr nc,b2p_1 ;A15=1 --> common
656 ld a,3
657 b2p_1:
658 srl a
659 rr h
660 ret
661
662 endif
663
664 ;--------------------------------------------------------------
665 ;
666 ;return:
667 ; hl = hl + a
668 ; Flags undefined
669 ;
670
671 add_hl_a:
672 add a,l
673 ld l,a
674 ret nc
675 inc h
676 ret
677
678 ; ---------------------------------------------------------
679
680 sysramw:
681
682 .phase isvsw_loc
683 topcodsys:
684
685 ; Trampoline for interrupt routines in banked ram.
686 ; Switch stack pointer to "system" stack in top ram
687 ; Save cbar
688
689 isv_sw: ;
690 ex (sp),hl ;save hl, 'return adr' in hl
691 push de ;
692 push af ;
693 ex de,hl ;'return address' in de
694 ld hl,0 ;
695 add hl,sp ;
696 ld a,h ;
697 cp 0f8h ;
698 jr nc,isw_1 ;stack allready in top ram
699 ld sp,$stack ;
700 isw_1:
701 push hl ;save user stack pointer
702 in0 h,(cbar) ;
703 push hl ;
704 ld a,SYS$CBAR ;
705 out0 (cbar),a ;
706 ex de,hl ;
707 ld e,(hl) ;
708 inc hl ;
709 ld d,(hl) ;
710 ex de,hl ;
711 push bc ;
712 call jphl ;
713
714 pop bc ;
715 pop hl ;
716 out0 (cbar),h ;
717 pop hl ;
718 ld sp,hl ;
719 pop af ;
720 pop de ;
721 pop hl ;
722 ei ;
723 ret ;
724 jphl:
725 jp (hl) ;
726
727 ; ---------------------------------------------------------
728
729 if CPU_Z180
730
731 iprt0:
732 push af
733 push hl
734 in0 a,(tcr)
735 in0 a,(tmdr0l)
736 in0 a,(tmdr0h)
737 ld a,(tim_ms)
738 inc a
739 cp 100
740 jr nz,iprt_1
741 xor a
742 ld hl,(tim_s)
743 inc hl
744 ld (tim_s),hl
745 iprt_1:
746 ld (tim_ms),a
747 pop hl
748 pop af
749 ei
750 ret
751
752 endif
753
754 ; ---------------------------------------------------------
755
756 sp.int0:
757 ld a,0d0h
758 jr sp.i.1
759 sp.int.len equ $-sp.int0
760 ld a,0d1h
761 jr sp.i.1
762 ld a,0d2h
763 jr sp.i.1
764 ld a,0d3h
765 jr sp.i.1
766 ld a,0d4h
767 jr sp.i.1
768 ld a,0d5h
769 jr sp.i.1
770 ld a,0d6h
771 jr sp.i.1
772 ld a,0d7h
773 jr sp.i.1
774 ld a,0d8h
775 sp.i.1:
776 ; out (80h),a
777 halt
778
779 ; ---------------------------------------------------------
780
781 if CPU_Z80
782
783 ; Get IFF2
784 ; This routine may not be loaded in page zero
785 ;
786 ; return Carry clear, if INTs are enabled.
787 ;
788 global getiff
789 getiff:
790 xor a ;clear accu and carry
791 push af ;stack bottom := 00xxh
792 pop af
793 ld a,i ;P flag := IFF2
794 ret pe ;exit carry clear, if enabled
795 dec sp
796 dec sp ;has stack bottom been overwritten?
797 pop af
798 and a ;if not 00xxh, INTs were
799 ret nz ;actually enabled
800 scf ;Otherwise, they really are disabled
801 ret
802
803 ;----------------------------------------------------------------------
804
805 global selbnk
806
807 ; a: bank (0..2)
808
809 selbnk:
810 push bc
811 ld c,a
812 call getiff
813 push af
814
815 ld a,c
816 di
817 ld (@cbnk),a
818 ld a,5
819 out (SIOAC),a
820 ld a,(mm_sio0)
821 rla
822 srl c
823 rra
824 out (SIOAC),a
825 ld (mm_sio0),a
826
827 ld a,5
828 out (SIOBC),a
829 ld a,(mm_sio1)
830 rla
831 srl c
832 rra
833 out (SIOBC),a
834 ld (mm_sio1),a
835 pop af
836 pop bc
837 ret c ;INTs were disabled
838 ei
839 ret
840
841 ;----------------------------------------------------------------------
842
843 ; c: bank (0..2)
844
845 if 0
846
847 selbnk:
848 ld a,(@cbnk)
849 xor c
850 and 3
851 ret z ;no change
852
853 call getiff
854 push af
855 ld a,c
856 di
857 ld (@cbnk),a
858 ld a,5
859 out (SIOAC),a
860 ld a,(mm_sio0)
861 rla
862 srl c
863 rra
864 out (SIOAC),a
865 ld (mm_sio0),a
866
867 ld a,5
868 out (SIOBC),a
869 ld a,(mm_sio1)
870 rla
871 srl c
872 rra
873 out (SIOBC),a
874 ld (mm_sio1),a
875 pop af
876 ret nc ;INTs were disabled
877 ei
878 ret
879
880 endif
881
882 ;----------------------------------------------------------------------
883
884 if 0
885 ex af,af'
886 push af
887 ex af,af'
888
889 rra
890 jr nc,stbk1
891 ex af,af'
892 ld a,5
893 out (SIOAC),a
894 ld a,(mm_sio0)
895 rla
896 srl c
897 rra
898 out (SIOAC),a
899 ld (mm_sio1),a
900 ex af,af'
901
902 stbk1:
903 rra
904 jr nc,stbk2
905 ex af,af'
906 ld a,5
907 out (SIOBC),a
908 ld a,(mm_sio1)
909 rla
910 srl c
911 rra
912 out (SIOBC),a
913 ld (mm_sio1),a
914 ex af,af'
915
916 stbk2:
917 endif
918
919 global @cbnk
920 global mm_sio0, mm_sio1
921
922 @cbnk: db 0 ; current bank (0..2)
923 mm_sio0:
924 ds 1
925 mm_sio1:
926 ds 1
927
928
929 endif
930
931 ;----------------------------------------------------------------------
932
933 curph defl $
934 .dephase
935 sysrame:
936 .phase curph
937 tim_ms: db 0
938 tim_s: dw 0
939 .dephase
940
941 ;-----------------------------------------------------
942
943
944 cseg
945
946 ;.phase 0ffc0h
947 ;ivtab equ 0ffc0h ; 0ffc0h ;int vector table
948 ;.dephase
949
950 ;.phase 0fffah
951 mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack
952 ;ds 4
953 ;.dephase
954
955
956 end
Z180 Stamp Monitor