| | 1 | page 255\r |
| | 2 | .z80\r |
| | 3 | \r |
| | 4 | extrn ddtz,bpent\r |
| | 5 | extrn $stack\r |
| | 6 | extrn charini,?const,?conin\r |
| | 7 | extrn ?cono,?conos\r |
| | 8 | extrn romend\r |
| | 9 | \r |
| | 10 | \r |
| | 11 | global iobyte\r |
| | 12 | global isv_sw\r |
| | 13 | \r |
| | 14 | include config.inc\r |
| | 15 | if CPU_Z180\r |
| | 16 | include z180reg.inc\r |
| | 17 | include z180.lib\r |
| | 18 | endif\r |
| | 19 | \r |
| | 20 | \r |
| | 21 | \r |
| | 22 | \r |
| | 23 | ;----------------------------------------------------------------------\r |
| | 24 | \r |
| | 25 | cseg\r |
| | 26 | romstart equ $\r |
| | 27 | \r |
| | 28 | org romstart+0\r |
| | 29 | jp start\r |
| | 30 | \r |
| | 31 | iobyte: db 2\r |
| | 32 | \r |
| | 33 | ; restart vectors\r |
| | 34 | \r |
| | 35 | rsti defl 1\r |
| | 36 | rept 7\r |
| | 37 | org 8*rsti + romstart\r |
| | 38 | jp bpent\r |
| | 39 | rsti defl rsti+1\r |
| | 40 | endm\r |
| | 41 | \r |
| | 42 | ;----------------------------------------------------------------------\r |
| | 43 | ; Config space\r |
| | 44 | ;\r |
| | 45 | \r |
| | 46 | org romstart+40h\r |
| | 47 | \r |
| | 48 | dw 0\r |
| | 49 | db 0\r |
| | 50 | \r |
| | 51 | \r |
| | 52 | if ROMSYS\r |
| | 53 | $crom: defb c$rom ;\r |
| | 54 | else\r |
| | 55 | db 0 ;\r |
| | 56 | endif\r |
| | 57 | \r |
| | 58 | INIWAITS defl CWAITIO\r |
| | 59 | if ROMSYS\r |
| | 60 | INIWAITS defl INIWAITS+CWAITROM\r |
| | 61 | endif\r |
| | 62 | \r |
| | 63 | ;----------------------------------------------------------------------\r |
| | 64 | \r |
| | 65 | org romstart+50h\r |
| | 66 | start:\r |
| | 67 | jp cstart\r |
| | 68 | jp wstart\r |
| | 69 | jp ?const\r |
| | 70 | jp ?conin\r |
| | 71 | jp ?cono\r |
| | 72 | jp ?conos\r |
| | 73 | jp charini\r |
| | 74 | \r |
| | 75 | ;----------------------------------------------------------------------\r |
| | 76 | \r |
| | 77 | hwini0:\r |
| | 78 | if CPU_Z180\r |
| | 79 | db 3 ;count\r |
| | 80 | db rcr,CREFSH ;configure DRAM refresh\r |
| | 81 | db dcntl,INIWAITS ;wait states\r |
| | 82 | db cbr,SYS$CBR\r |
| | 83 | db cbar,SYS$CBAR\r |
| | 84 | endif\r |
| | 85 | db 0\r |
| | 86 | \r |
| | 87 | if CPU_Z180\r |
| | 88 | dmclrt: ;clear ram per dma\r |
| | 89 | db dmct_e-dmclrt-2 ;\r |
| | 90 | db sar0l ;first port\r |
| | 91 | dw nullbyte ;src (fixed)\r |
| | 92 | nullbyte:\r |
| | 93 | db 000h ;src\r |
| | 94 | dw romend ;dst (inc), start after "rom" code\r |
| | 95 | db 00h ;dst\r |
| | 96 | dw 0-romend ;count (64k)\r |
| | 97 | dmct_e:\r |
| | 98 | db 0\r |
| | 99 | endif\r |
| | 100 | \r |
| | 101 | \r |
| | 102 | cstart:\r |
| | 103 | if CPU_Z180\r |
| | 104 | \r |
| | 105 | push af\r |
| | 106 | in0 a,(itc) ;Illegal opcode trap?\r |
| | 107 | jp m,??st01\r |
| | 108 | ld a,i ;I register == 0 ?\r |
| | 109 | jr z,hw_reset ; yes, harware reset\r |
| | 110 | \r |
| | 111 | ??st01:\r |
| | 112 | ; TODO: SYS$CBR\r |
| | 113 | ld a,(syscbr)\r |
| | 114 | out0 (cbr),a\r |
| | 115 | pop af ;restore registers\r |
| | 116 | jp bpent ;\r |
| | 117 | \r |
| | 118 | hw_reset:\r |
| | 119 | di ;0058\r |
| | 120 | ld a,CREFSH\r |
| | 121 | out0 (rcr),a ; configure DRAM refresh\r |
| | 122 | ld a,CWAITIO\r |
| | 123 | out0 (dcntl),a ; wait states\r |
| | 124 | \r |
| | 125 | ld a,M_NCD ;No Clock Divide\r |
| | 126 | out0 (ccr),a\r |
| | 127 | ; ld a,M_X2CM ;X2 Clock Multiplier\r |
| | 128 | ; out0 (cmr),a\r |
| | 129 | else\r |
| | 130 | di\r |
| | 131 | xor a\r |
| | 132 | ld (@cbnk),a\r |
| | 133 | endif\r |
| | 134 | \r |
| | 135 | ; check warm start mark\r |
| | 136 | \r |
| | 137 | ld ix,mark_55AA ; top of common area\r |
| | 138 | ld a,0aah ;\r |
| | 139 | cp (ix+000h) ;\r |
| | 140 | jr nz,kstart ;\r |
| | 141 | cp (ix+002h) ;\r |
| | 142 | jr nz,kstart ;\r |
| | 143 | cpl ;\r |
| | 144 | cp (ix+001h) ;\r |
| | 145 | jr nz,kstart ;\r |
| | 146 | cp (ix+003h) ;\r |
| | 147 | jr nz,kstart ;\r |
| | 148 | ld sp,$stack ; mark found, check\r |
| | 149 | jp z,wstart ; check ok,\r |
| | 150 | \r |
| | 151 | ; ram not ok, initialize -- kstart --\r |
| | 152 | \r |
| | 153 | kstart:\r |
| | 154 | if CPU_Z180\r |
| | 155 | ld a,SYS$CBR\r |
| | 156 | out0 (cbr),a\r |
| | 157 | ld a,SYS$CBAR\r |
| | 158 | out0 (cbar),a\r |
| | 159 | endif\r |
| | 160 | \r |
| | 161 | ld sp,$stack ;01e1\r |
| | 162 | \r |
| | 163 | ; Clear RAM using DMA0\r |
| | 164 | \r |
| | 165 | if CPU_Z180\r |
| | 166 | if 0\r |
| | 167 | \r |
| | 168 | ld hl,dmclrt ;load DMA registers\r |
| | 169 | call ioiniml\r |
| | 170 | ld a,0cbh ;01ef dst +1, src fixed, burst\r |
| | 171 | out0 (dmode),a ;01f1\r |
| | 172 | \r |
| | 173 | ld b,512/64\r |
| | 174 | ld a,062h ;01f4 enable dma0,\r |
| | 175 | ??cl_1:\r |
| | 176 | out0 (dstat),a ;01f9 clear (up to) 64k\r |
| | 177 | djnz ??cl_1 ; end of RAM?\r |
| | 178 | \r |
| | 179 | endif\r |
| | 180 | endif\r |
| | 181 | \r |
| | 182 | ld hl,055AAh ;set warm start mark\r |
| | 183 | ld (mark_55AA),hl\r |
| | 184 | ld (mark_55AA+2),hl\r |
| | 185 | \r |
| | 186 | ; -- wstart --\r |
| | 187 | \r |
| | 188 | wstart:\r |
| | 189 | call sysram_init\r |
| | 190 | call ivtab_init\r |
| | 191 | if CPU_Z180\r |
| | 192 | ; call prt0_init\r |
| | 193 | endif\r |
| | 194 | \r |
| | 195 | call charini\r |
| | 196 | call bufferinit\r |
| | 197 | \r |
| | 198 | if CPU_Z80\r |
| | 199 | ld a,0\r |
| | 200 | call selbnk\r |
| | 201 | endif\r |
| | 202 | \r |
| | 203 | ld a,INIDONEVAL ;tell others (CP/M) that hardware and fifos\r |
| | 204 | ld (INIDONE),a ; are allready initialized\r |
| | 205 | \r |
| | 206 | im 2\r |
| | 207 | ei\r |
| | 208 | \r |
| | 209 | call ?const\r |
| | 210 | call ?const\r |
| | 211 | or a\r |
| | 212 | call nz,?conin\r |
| | 213 | \r |
| | 214 | if CPU_Z180\r |
| | 215 | ld e,0 ;Sys$Bank\r |
| | 216 | else\r |
| | 217 | ; TODO:\r |
| | 218 | endif\r |
| | 219 | jp ddtz\r |
| | 220 | \r |
| | 221 | \r |
| | 222 | if CPU_Z180\r |
| | 223 | ; TODO: SYS$CBR\r |
| | 224 | syscbr: db 0\r |
| | 225 | endif\r |
| | 226 | \r |
| | 227 | ;\r |
| | 228 | ;----------------------------------------------------------------------\r |
| | 229 | ;\r |
| | 230 | \r |
| | 231 | global buf.init\r |
| | 232 | \r |
| | 233 | buf.init:\r |
| | 234 | ld (ix+o.in_idx),0\r |
| | 235 | ld (ix+o.out_idx),0\r |
| | 236 | ld (ix+o.mask),a\r |
| | 237 | \r |
| | 238 | ld a,(ix+o.id)\r |
| | 239 | cp 4\r |
| | 240 | ret nc\r |
| | 241 | \r |
| | 242 | push de\r |
| | 243 | push hl\r |
| | 244 | ld hl,fifo_list\r |
| | 245 | push hl ;save fifo_list\r |
| | 246 | ld e,a\r |
| | 247 | ld d,0\r |
| | 248 | add hl,de\r |
| | 249 | add hl,de\r |
| | 250 | add hl,de\r |
| | 251 | push ix\r |
| | 252 | pop de\r |
| | 253 | ; TODO: address translation\r |
| | 254 | ld (hl),e\r |
| | 255 | inc hl\r |
| | 256 | ld (hl),d\r |
| | 257 | pop hl ;get fifo_list back\r |
| | 258 | or a\r |
| | 259 | jr nz,bufi_ex\r |
| | 260 | \r |
| | 261 | ld (040h),hl\r |
| | 262 | ld (040h+2),a\r |
| | 263 | bufi_ex:\r |
| | 264 | pop hl\r |
| | 265 | pop de\r |
| | 266 | \r |
| | 267 | ret\r |
| | 268 | \r |
| | 269 | \r |
| | 270 | fifo_list:\r |
| | 271 | rept 4\r |
| | 272 | dw 0\r |
| | 273 | db 0\r |
| | 274 | endm\r |
| | 275 | \r |
| | 276 | ;----------------------------------------------------------------------\r |
| | 277 | \r |
| | 278 | extrn msginit,msg.sout\r |
| | 279 | extrn mtx.fifo,mrx.fifo\r |
| | 280 | extrn co.fifo,ci.fifo\r |
| | 281 | \r |
| | 282 | \r |
| | 283 | bufferinit:\r |
| | 284 | if CPU_Z180\r |
| | 285 | call msginit\r |
| | 286 | \r |
| | 287 | ld hl,buffers\r |
| | 288 | ld b,buftablen\r |
| | 289 | bfi_1:\r |
| | 290 | ld a,(hl)\r |
| | 291 | inc hl\r |
| | 292 | ld (bufdat+0),a\r |
| | 293 | ld e,(hl)\r |
| | 294 | inc hl\r |
| | 295 | ld d,(hl)\r |
| | 296 | inc hl\r |
| | 297 | ex de,hl\r |
| | 298 | \r |
| | 299 | or a\r |
| | 300 | jr nz,bfi_2\r |
| | 301 | ; call hwl2phy\r |
| | 302 | ; ld (40h+0),hl\r |
| | 303 | ; ld (40h+2),a\r |
| | 304 | out (AVRINT5),a\r |
| | 305 | jr bfi_3\r |
| | 306 | bfi_2:\r |
| | 307 | call hwl2phy\r |
| | 308 | ld (bufdat+1),hl\r |
| | 309 | ld (bufdat+3),a\r |
| | 310 | ld hl,inimsg\r |
| | 311 | call msg.sout\r |
| | 312 | bfi_3:\r |
| | 313 | ex de,hl\r |
| | 314 | djnz bfi_1\r |
| | 315 | ret\r |
| | 316 | \r |
| | 317 | else ;CPU_Z180\r |
| | 318 | \r |
| | 319 | call msginit\r |
| | 320 | \r |
| | 321 | ld hl,buffers\r |
| | 322 | ld b,buftablen\r |
| | 323 | bfi_1:\r |
| | 324 | ld a,(hl)\r |
| | 325 | inc hl\r |
| | 326 | ld (bufdat+0),a\r |
| | 327 | ld e,(hl)\r |
| | 328 | inc hl\r |
| | 329 | ld d,(hl)\r |
| | 330 | inc hl\r |
| | 331 | ex de,hl\r |
| | 332 | \r |
| | 333 | or a\r |
| | 334 | jr nz,bfi_2\r |
| | 335 | \r |
| | 336 | ld a,(@cbnk)\r |
| | 337 | call bnk2phy\r |
| | 338 | \r |
| | 339 | ld (40h+0),hl\r |
| | 340 | ld (40h+2),a\r |
| | 341 | out (AVRINT5),a\r |
| | 342 | jr bfi_3\r |
| | 343 | bfi_2:\r |
| | 344 | \r |
| | 345 | ld a,(@cbnk)\r |
| | 346 | call bnk2phy\r |
| | 347 | \r |
| | 348 | ld (bufdat+1),hl\r |
| | 349 | ld (bufdat+3),a\r |
| | 350 | ld hl,inimsg\r |
| | 351 | call msg.sout\r |
| | 352 | bfi_3:\r |
| | 353 | ex de,hl\r |
| | 354 | djnz bfi_1\r |
| | 355 | ret\r |
| | 356 | endif\r |
| | 357 | \r |
| | 358 | buffers:\r |
| | 359 | db 0\r |
| | 360 | dw mtx.fifo\r |
| | 361 | db 1\r |
| | 362 | dw mrx.fifo\r |
| | 363 | db 2\r |
| | 364 | dw ci.fifo\r |
| | 365 | db 3\r |
| | 366 | dw co.fifo\r |
| | 367 | buftablen equ ($ - buffers)/3\r |
| | 368 | \r |
| | 369 | inimsg:\r |
| | 370 | db inimsg_e - $ -1\r |
| | 371 | db 0AEh\r |
| | 372 | db inimsg_e - $ -1\r |
| | 373 | db 0\r |
| | 374 | bufdat:\r |
| | 375 | db 0\r |
| | 376 | dw 0\r |
| | 377 | db 0\r |
| | 378 | inimsg_e:\r |
| | 379 | \r |
| | 380 | \r |
| | 381 | ;\r |
| | 382 | ;----------------------------------------------------------------------\r |
| | 383 | ;\r |
| | 384 | \r |
| | 385 | sysram_init:\r |
| | 386 | ld hl,sysramw\r |
| | 387 | ld de,topcodsys\r |
| | 388 | ld bc,sysrame-sysramw\r |
| | 389 | ldir\r |
| | 390 | \r |
| | 391 | ret\r |
| | 392 | \r |
| | 393 | ;----------------------------------------------------------------------\r |
| | 394 | \r |
| | 395 | ivtab_init:\r |
| | 396 | ld hl,ivtab ;\r |
| | 397 | ld a,h ;\r |
| | 398 | ld i,a ;\r |
| | 399 | if CPU_Z180\r |
| | 400 | out0 (il),l ;\r |
| | 401 | endif\r |
| | 402 | \r |
| | 403 | ; Let all vectors point to spurious int routines.\r |
| | 404 | \r |
| | 405 | ld d,high sp.int0\r |
| | 406 | ld a,low sp.int0\r |
| | 407 | ld b,9\r |
| | 408 | ivt_i1:\r |
| | 409 | ld (hl),a\r |
| | 410 | inc l\r |
| | 411 | ld (hl),d\r |
| | 412 | inc l\r |
| | 413 | add a,sp.int.len\r |
| | 414 | djnz ivt_i1\r |
| | 415 | ret\r |
| | 416 | \r |
| | 417 | ;----------------------------------------------------------------------\r |
| | 418 | \r |
| | 419 | if CPU_Z180\r |
| | 420 | prt0_init:\r |
| | 421 | ld a,i\r |
| | 422 | ld h,a\r |
| | 423 | in0 a,(il)\r |
| | 424 | and 0E0h\r |
| | 425 | or IV$PRT0\r |
| | 426 | ld l,a\r |
| | 427 | ld (hl),low iprt0\r |
| | 428 | inc hl\r |
| | 429 | ld (hl),high iprt0\r |
| | 430 | ld hl,prt0itab\r |
| | 431 | call ioiniml\r |
| | 432 | ret\r |
| | 433 | \r |
| | 434 | prt0itab:\r |
| | 435 | db prt0it_e-prt0itab-2\r |
| | 436 | db tmdr0l\r |
| | 437 | dw PRT_TC10MS\r |
| | 438 | dw PRT_TC10MS\r |
| | 439 | db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.\r |
| | 440 | prt0it_e:\r |
| | 441 | db 0\r |
| | 442 | endif\r |
| | 443 | \r |
| | 444 | \r |
| | 445 | ;\r |
| | 446 | ;----------------------------------------------------------------------\r |
| | 447 | ;\r |
| | 448 | \r |
| | 449 | if CPU_Z180\r |
| | 450 | io.ini:\r |
| | 451 | if 0\r |
| | 452 | push bc\r |
| | 453 | ld b,0 ;high byte port adress\r |
| | 454 | ioi_nxt:\r |
| | 455 | ld a,(hl) ;count\r |
| | 456 | inc hl\r |
| | 457 | or a\r |
| | 458 | jr z,ioi_e\r |
| | 459 | \r |
| | 460 | ld c,(hl) ;port address\r |
| | 461 | inc hl\r |
| | 462 | ioi_r:\r |
| | 463 | outi\r |
| | 464 | inc b ;outi decrements b\r |
| | 465 | dec a\r |
| | 466 | jr nz,ioi_r\r |
| | 467 | jr ioi_nxt\r |
| | 468 | ioi_e:\r |
| | 469 | pop bc\r |
| | 470 | ret\r |
| | 471 | \r |
| | 472 | else ;(if 1/0)\r |
| | 473 | \r |
| | 474 | push bc\r |
| | 475 | jr ioi_nxt\r |
| | 476 | ioi_l:\r |
| | 477 | ld c,(hl) ;port address\r |
| | 478 | inc hl\r |
| | 479 | inc c\r |
| | 480 | ioi_r:\r |
| | 481 | dec c ;otim increments c\r |
| | 482 | otim\r |
| | 483 | jr z,ioi_r\r |
| | 484 | ioi_nxt:\r |
| | 485 | ld b,(hl) ;count\r |
| | 486 | inc hl\r |
| | 487 | inc b ;stop if count == 0\r |
| | 488 | djnz ioi_l\r |
| | 489 | pop bc\r |
| | 490 | ret\r |
| | 491 | \r |
| | 492 | endif ;(1/0)\r |
| | 493 | \r |
| | 494 | else\r |
| | 495 | \r |
| | 496 | io.ini:\r |
| | 497 | push bc\r |
| | 498 | jr ioi_nxt\r |
| | 499 | ioi_l:\r |
| | 500 | ld c,(hl) ;port address\r |
| | 501 | inc hl\r |
| | 502 | otir\r |
| | 503 | ioi_nxt:\r |
| | 504 | ld b,(hl) ;count\r |
| | 505 | inc hl\r |
| | 506 | inc b\r |
| | 507 | djnz ioi_l\r |
| | 508 | endif\r |
| | 509 | pop bc\r |
| | 510 | ret\r |
| | 511 | \r |
| | 512 | ;----------------------------------------------------------------------\r |
| | 513 | \r |
| | 514 | if CPU_Z180\r |
| | 515 | \r |
| | 516 | global ioiniml\r |
| | 517 | \r |
| | 518 | ioiniml:\r |
| | 519 | push bc\r |
| | 520 | xor a\r |
| | 521 | ioml_lp:\r |
| | 522 | ld b,(hl)\r |
| | 523 | inc hl\r |
| | 524 | cp b\r |
| | 525 | jr z,ioml_e\r |
| | 526 | \r |
| | 527 | ld c,(hl)\r |
| | 528 | inc hl\r |
| | 529 | otimr\r |
| | 530 | jr ioml_lp\r |
| | 531 | ioml_e:\r |
| | 532 | pop bc\r |
| | 533 | ret z\r |
| | 534 | endif\r |
| | 535 | \r |
| | 536 | io.ini.l:\r |
| | 537 | ;\r |
| | 538 | \r |
| | 539 | \r |
| | 540 | \r |
| | 541 | ;----------------------------------------------------------------------\r |
| | 542 | ;\r |
| | 543 | if CPU_Z180\r |
| | 544 | \r |
| | 545 | ;--------------------------------------------------------------------\r |
| | 546 | ; Return the BBR value for the given bank number\r |
| | 547 | ;\r |
| | 548 | ; in a: Bank number\r |
| | 549 | ; out a: bbr value\r |
| | 550 | \r |
| | 551 | bnk2log:\r |
| | 552 | or a ;\r |
| | 553 | ret z ; Bank 0 is at physical address 0\r |
| | 554 | \r |
| | 555 | push bc ;\r |
| | 556 | ld b,a ;\r |
| | 557 | ld c,CA ;\r |
| | 558 | mlt bc ;\r |
| | 559 | ld a,c ;\r |
| | 560 | add a,10h ;\r |
| | 561 | pop bc ;\r |
| | 562 | ret ;\r |
| | 563 | \r |
| | 564 | ;--------------------------------------------------------------\r |
| | 565 | \r |
| | 566 | ;in hl: Log. Address\r |
| | 567 | ; a: Bank number\r |
| | 568 | ;\r |
| | 569 | ;out ahl: Phys. (linear) Address\r |
| | 570 | \r |
| | 571 | \r |
| | 572 | bnk2phy:\r |
| | 573 | call bnk2log\r |
| | 574 | ; fall thru\r |
| | 575 | \r |
| | 576 | ;--------------------------------------------------------------\r |
| | 577 | ;\r |
| | 578 | ; hl: Log. Address\r |
| | 579 | ; a: Bank base (bbr)\r |
| | 580 | ;\r |
| | 581 | ; 2 0 0\r |
| | 582 | ; 0 6 8 0\r |
| | 583 | ; hl hhhhhhhhllllllll\r |
| | 584 | ; a + bbbbbbbb\r |
| | 585 | ;\r |
| | 586 | ; OP: ahl = (a<<12) + (h<<8) + l\r |
| | 587 | ;\r |
| | 588 | ;out ahl: Phys. (linear) Address\r |
| | 589 | \r |
| | 590 | log2phy:\r |
| | 591 | push bc ;\r |
| | 592 | l2p_i:\r |
| | 593 | ld c,a ;\r |
| | 594 | ld b,16 ;\r |
| | 595 | mlt bc ; bc = a<<4\r |
| | 596 | ld a,c ;\r |
| | 597 | add a,h ;\r |
| | 598 | ld h,a ;\r |
| | 599 | ld a,b ;\r |
| | 600 | adc a,0 ;\r |
| | 601 | pop bc ;\r |
| | 602 | ret ;\r |
| | 603 | \r |
| | 604 | ;--------------------------------------------------------------\r |
| | 605 | ;\r |
| | 606 | ; hl: Log. Address\r |
| | 607 | ;\r |
| | 608 | ;\r |
| | 609 | ; OP: ahl = (bankbase<<12) + (d<<8) + e\r |
| | 610 | ;\r |
| | 611 | ;out ahl: Phys. (linear) Address\r |
| | 612 | \r |
| | 613 | \r |
| | 614 | hwl2phy:\r |
| | 615 | push bc ;\r |
| | 616 | in0 c,(cbar) ;\r |
| | 617 | ld a,h ;\r |
| | 618 | or 00fh ; log. addr in common1?\r |
| | 619 | cp c\r |
| | 620 | jr c,hlp_1\r |
| | 621 | \r |
| | 622 | in0 a,(cbr) ; yes, cbr is address base\r |
| | 623 | jr hl2p_x\r |
| | 624 | hlp_1:\r |
| | 625 | ld b,16 ; log. address in baked area?\r |
| | 626 | mlt bc\r |
| | 627 | ld a,h\r |
| | 628 | cp c\r |
| | 629 | jr c,hlp_2\r |
| | 630 | in0 a,(bbr) ; yes, bbr is address base\r |
| | 631 | jr hl2p_x\r |
| | 632 | hlp_2:\r |
| | 633 | xor a ; common1\r |
| | 634 | hl2p_x:\r |
| | 635 | jr nz,l2p_i\r |
| | 636 | \r |
| | 637 | pop bc ; bank part is 0, no translation\r |
| | 638 | ret ;\r |
| | 639 | \r |
| | 640 | \r |
| | 641 | \r |
| | 642 | else ;CPU_Z180\r |
| | 643 | \r |
| | 644 | ;----------------------------------------------------------------------\r |
| | 645 | ;\r |
| | 646 | \r |
| | 647 | bnk2phy:\r |
| | 648 | sla h\r |
| | 649 | jr nc,b2p_1 ;A15=1 --> common\r |
| | 650 | ld a,3\r |
| | 651 | b2p_1:\r |
| | 652 | srl a\r |
| | 653 | rr h\r |
| | 654 | ret\r |
| | 655 | \r |
| | 656 | endif\r |
| | 657 | \r |
| | 658 | ;--------------------------------------------------------------\r |
| | 659 | ;\r |
| | 660 | ;return:\r |
| | 661 | ; hl = hl + a\r |
| | 662 | ; Flags undefined\r |
| | 663 | ;\r |
| | 664 | \r |
| | 665 | add_hl_a:\r |
| | 666 | add a,l\r |
| | 667 | ld l,a\r |
| | 668 | ret nc\r |
| | 669 | inc h\r |
| | 670 | ret\r |
| | 671 | \r |
| | 672 | ; ---------------------------------------------------------\r |
| | 673 | \r |
| | 674 | sysramw:\r |
| | 675 | \r |
| | 676 | .phase isvsw_loc\r |
| | 677 | topcodsys:\r |
| | 678 | \r |
| | 679 | ; Trampoline for interrupt routines in banked ram.\r |
| | 680 | ; Switch stack pointer to "system" stack in top ram\r |
| | 681 | ; Save cbar\r |
| | 682 | \r |
| | 683 | isv_sw: ;\r |
| | 684 | ex (sp),hl ;save hl, 'return adr' in hl\r |
| | 685 | push de ;\r |
| | 686 | push af ;\r |
| | 687 | ex de,hl ;'return address' in de\r |
| | 688 | ld hl,0 ;\r |
| | 689 | add hl,sp ;\r |
| | 690 | ld a,h ;\r |
| | 691 | cp 0f8h ;\r |
| | 692 | jr nc,isw_1 ;stack allready in top ram\r |
| | 693 | ld sp,$stack ;\r |
| | 694 | isw_1:\r |
| | 695 | push hl ;save user stack pointer\r |
| | 696 | in0 h,(cbar) ;\r |
| | 697 | push hl ;\r |
| | 698 | ld a,SYS$CBAR ;\r |
| | 699 | out0 (cbar),a ;\r |
| | 700 | ex de,hl ;\r |
| | 701 | ld e,(hl) ;\r |
| | 702 | inc hl ;\r |
| | 703 | ld d,(hl) ;\r |
| | 704 | ex de,hl ;\r |
| | 705 | push bc ;\r |
| | 706 | call jphl ;\r |
| | 707 | \r |
| | 708 | pop bc ;\r |
| | 709 | pop hl ;\r |
| | 710 | out0 (cbar),h ;\r |
| | 711 | pop hl ;\r |
| | 712 | ld sp,hl ;\r |
| | 713 | pop af ;\r |
| | 714 | pop de ;\r |
| | 715 | pop hl ;\r |
| | 716 | ei ;\r |
| | 717 | ret ;\r |
| | 718 | jphl:\r |
| | 719 | jp (hl) ;\r |
| | 720 | \r |
| | 721 | ; ---------------------------------------------------------\r |
| | 722 | \r |
| | 723 | if CPU_Z180\r |
| | 724 | \r |
| | 725 | iprt0:\r |
| | 726 | push af\r |
| | 727 | push hl\r |
| | 728 | in0 a,(tcr)\r |
| | 729 | in0 a,(tmdr0l)\r |
| | 730 | in0 a,(tmdr0h)\r |
| | 731 | ld a,(tim_ms)\r |
| | 732 | inc a\r |
| | 733 | cp 100\r |
| | 734 | jr nz,iprt_1\r |
| | 735 | xor a\r |
| | 736 | ld hl,(tim_s)\r |
| | 737 | inc hl\r |
| | 738 | ld (tim_s),hl\r |
| | 739 | iprt_1:\r |
| | 740 | ld (tim_ms),a\r |
| | 741 | pop hl\r |
| | 742 | pop af\r |
| | 743 | ei\r |
| | 744 | ret\r |
| | 745 | \r |
| | 746 | endif\r |
| | 747 | \r |
| | 748 | ; ---------------------------------------------------------\r |
| | 749 | \r |
| | 750 | sp.int0:\r |
| | 751 | ld a,0d0h\r |
| | 752 | jr sp.i.1\r |
| | 753 | sp.int.len equ $-sp.int0\r |
| | 754 | ld a,0d1h\r |
| | 755 | jr sp.i.1\r |
| | 756 | ld a,0d2h\r |
| | 757 | jr sp.i.1\r |
| | 758 | ld a,0d3h\r |
| | 759 | jr sp.i.1\r |
| | 760 | ld a,0d4h\r |
| | 761 | jr sp.i.1\r |
| | 762 | ld a,0d5h\r |
| | 763 | jr sp.i.1\r |
| | 764 | ld a,0d6h\r |
| | 765 | jr sp.i.1\r |
| | 766 | ld a,0d7h\r |
| | 767 | jr sp.i.1\r |
| | 768 | ld a,0d8h\r |
| | 769 | sp.i.1:\r |
| | 770 | ; out (80h),a\r |
| | 771 | halt\r |
| | 772 | \r |
| | 773 | ; ---------------------------------------------------------\r |
| | 774 | \r |
| | 775 | if CPU_Z80\r |
| | 776 | \r |
| | 777 | ; Get IFF2\r |
| | 778 | ; This routine may not be loaded in page zero\r |
| | 779 | ;\r |
| | 780 | ; return Carry clear, if INTs are enabled.\r |
| | 781 | ;\r |
| | 782 | global getiff\r |
| | 783 | getiff:\r |
| | 784 | xor a ;clear accu and carry\r |
| | 785 | push af ;stack bottom := 00xxh\r |
| | 786 | pop af\r |
| | 787 | ld a,i ;P flag := IFF2\r |
| | 788 | ret pe ;exit carry clear, if enabled\r |
| | 789 | dec sp\r |
| | 790 | dec sp ;has stack bottom been overwritten?\r |
| | 791 | pop af\r |
| | 792 | and a ;if not 00xxh, INTs were\r |
| | 793 | ret nz ;actually enabled\r |
| | 794 | scf ;Otherwise, they really are disabled\r |
| | 795 | ret\r |
| | 796 | \r |
| | 797 | ;----------------------------------------------------------------------\r |
| | 798 | \r |
| | 799 | global selbnk\r |
| | 800 | \r |
| | 801 | ; a: bank (0..2)\r |
| | 802 | \r |
| | 803 | selbnk:\r |
| | 804 | push bc\r |
| | 805 | ld c,a\r |
| | 806 | call getiff\r |
| | 807 | push af\r |
| | 808 | \r |
| | 809 | ld a,c\r |
| | 810 | di\r |
| | 811 | ld (@cbnk),a\r |
| | 812 | ld a,5\r |
| | 813 | out (SIOAC),a\r |
| | 814 | ld a,(mm_sio0)\r |
| | 815 | rla\r |
| | 816 | srl c\r |
| | 817 | rra\r |
| | 818 | out (SIOAC),a\r |
| | 819 | ld (mm_sio0),a\r |
| | 820 | \r |
| | 821 | ld a,5\r |
| | 822 | out (SIOBC),a\r |
| | 823 | ld a,(mm_sio1)\r |
| | 824 | rla\r |
| | 825 | srl c\r |
| | 826 | rra\r |
| | 827 | out (SIOBC),a\r |
| | 828 | ld (mm_sio1),a\r |
| | 829 | pop af\r |
| | 830 | pop bc\r |
| | 831 | ret c ;INTs were disabled\r |
| | 832 | ei\r |
| | 833 | ret\r |
| | 834 | \r |
| | 835 | ;----------------------------------------------------------------------\r |
| | 836 | \r |
| | 837 | ; c: bank (0..2)\r |
| | 838 | \r |
| | 839 | if 0\r |
| | 840 | \r |
| | 841 | selbnk:\r |
| | 842 | ld a,(@cbnk)\r |
| | 843 | xor c\r |
| | 844 | and 3\r |
| | 845 | ret z ;no change\r |
| | 846 | \r |
| | 847 | call getiff\r |
| | 848 | push af\r |
| | 849 | ld a,c\r |
| | 850 | di\r |
| | 851 | ld (@cbnk),a\r |
| | 852 | ld a,5\r |
| | 853 | out (SIOAC),a\r |
| | 854 | ld a,(mm_sio0)\r |
| | 855 | rla\r |
| | 856 | srl c\r |
| | 857 | rra\r |
| | 858 | out (SIOAC),a\r |
| | 859 | ld (mm_sio0),a\r |
| | 860 | \r |
| | 861 | ld a,5\r |
| | 862 | out (SIOBC),a\r |
| | 863 | ld a,(mm_sio1)\r |
| | 864 | rla\r |
| | 865 | srl c\r |
| | 866 | rra\r |
| | 867 | out (SIOBC),a\r |
| | 868 | ld (mm_sio1),a\r |
| | 869 | pop af\r |
| | 870 | ret nc ;INTs were disabled\r |
| | 871 | ei\r |
| | 872 | ret\r |
| | 873 | \r |
| | 874 | endif\r |
| | 875 | \r |
| | 876 | ;----------------------------------------------------------------------\r |
| | 877 | \r |
| | 878 | if 0\r |
| | 879 | ex af,af'\r |
| | 880 | push af\r |
| | 881 | ex af,af'\r |
| | 882 | \r |
| | 883 | rra\r |
| | 884 | jr nc,stbk1\r |
| | 885 | ex af,af'\r |
| | 886 | ld a,5\r |
| | 887 | out (SIOAC),a\r |
| | 888 | ld a,(mm_sio0)\r |
| | 889 | rla\r |
| | 890 | srl c\r |
| | 891 | rra\r |
| | 892 | out (SIOAC),a\r |
| | 893 | ld (mm_sio1),a\r |
| | 894 | ex af,af'\r |
| | 895 | \r |
| | 896 | stbk1:\r |
| | 897 | rra\r |
| | 898 | jr nc,stbk2\r |
| | 899 | ex af,af'\r |
| | 900 | ld a,5\r |
| | 901 | out (SIOBC),a\r |
| | 902 | ld a,(mm_sio1)\r |
| | 903 | rla\r |
| | 904 | srl c\r |
| | 905 | rra\r |
| | 906 | out (SIOBC),a\r |
| | 907 | ld (mm_sio1),a\r |
| | 908 | ex af,af'\r |
| | 909 | \r |
| | 910 | stbk2:\r |
| | 911 | endif\r |
| | 912 | \r |
| | 913 | global @cbnk\r |
| | 914 | global mm_sio0, mm_sio1\r |
| | 915 | \r |
| | 916 | @cbnk: db 0 ; current bank (0..2)\r |
| | 917 | mm_sio0:\r |
| | 918 | ds 1\r |
| | 919 | mm_sio1:\r |
| | 920 | ds 1\r |
| | 921 | \r |
| | 922 | \r |
| | 923 | endif\r |
| | 924 | \r |
| | 925 | ;----------------------------------------------------------------------\r |
| | 926 | \r |
| | 927 | curph defl $\r |
| | 928 | .dephase\r |
| | 929 | sysrame:\r |
| | 930 | .phase curph\r |
| | 931 | tim_ms: db 0\r |
| | 932 | tim_s: dw 0\r |
| | 933 | .dephase\r |
| | 934 | \r |
| | 935 | ;-----------------------------------------------------\r |
| | 936 | \r |
| | 937 | \r |
| | 938 | cseg\r |
| | 939 | \r |
| | 940 | ;.phase 0ffc0h\r |
| | 941 | ;ivtab equ 0ffc0h ; 0ffc0h ;int vector table\r |
| | 942 | ;.dephase\r |
| | 943 | \r |
| | 944 | ;.phase 0fffah\r |
| | 945 | mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack\r |
| | 946 | ;ds 4\r |
| | 947 | ;.dephase\r |
| | 948 | \r |
| | 949 | \r |
| | 950 | end\r |
projects / z180-stamp.git / blame_incremental