]> cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
projects / z180-stamp.git / blob
? search:


08d417b832bd5b69c3675afd553775205b1c745c
[z180-stamp.git] / avr / z80-if.c
1 /*
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 /**
8 *
9 * Pin assignments
10 *
11 * | Z180-Sig | AVR-Port | Dir |
12 * +------------+---------------+-------+
13 * | A0 | PA 0 | O |
14 * | A1 | PA 1 | O |
15 * | A2 | PA 2 | O |
16 * | A3 | PA 3 | O |
17 * | A4 | PA 4 | O |
18 * | A5 | PA 5 | O |
19 * | A6 | PA 6 | O |
20 * | A7 | PA 7 | O |
21 * | A8 | PC 0 | O |
22 * | A9 | PC 1 | O |
23 * | A10 | PC 2 | O |
24 * | A11 | PC 3 | O |
25 * | A12 | PC 4 | O |
26 * | A13 | PC 5 | O |
27 * | A14 | PC 6 | O |
28 * | A15 | PC 7 | O |
29 * | A16 | PE 2 | O |
30 * | A17 | PE 3 | O |
31 * | A18 | PE 4 | O |
32 * | D0 | PF 0 | I/O |
33 * | D1 | PF 1 | I/O |
34 * | D2 | PF 2 | I/O |
35 * | D3 | PF 3 | I/O |
36 * | D4 | PF 4 | I/O |
37 * | D5 | PF 5 | I/O |
38 * | D6 | PF 6 | I/O |
39 * | D7 | PF 7 | I/O |
40 * | RD | PD 3 | O |
41 * | WR | PD 2 | O |
42 * | MREQ | PD 4 | O |
43 * | RST | PD 5 | O |
44 * | BUSREQ | PD 7 | O |
45 * | BUSACK | PD 6 | I |
46 * |
47 * | Optional
48 * +------------------------------------+
49 * | STEP | PG 0 | O |
50 * | RUN | PG 1 | O |
51 * | WAIT | PG 2 | I |
52
53 */
54
55
56 #include "z80-if.h"
57 #include <util/atomic.h>
58 #include "debug.h"
59 #include "config.h"
60 #include "env.h"
61
62
63 //#define P_ZCLK PORTB
64 //#define ZCLK 5
65 //#define DDR_ZCLK DDRB
66 #define P_MREQ PORTD
67 #define MREQ 4
68 #define DDR_MREQ DDRD
69 #define P_RD PORTD
70 #define RD 3
71 #define P_WR PORTD
72 #define WR 2
73 #define P_BUSREQ PORTD
74 #define BUSREQ 7
75 #define DDR_BUSREQ DDRD
76 #define P_BUSACK PORTD
77 #define PIN_BUSACK PIND
78 #define BUSACK 6
79 #define DDR_BUSACK DDRD
80 #define P_RST PORTD
81 #define DDR_RST DDRD
82 #define RST 5
83
84
85 #define P_DB PORTF
86 #define PIN_DB PINF
87 #define DDR_DB DDRF
88
89 #define P_ADL PORTA
90 #define P_ADH PORTC
91 #define P_ADB PORTE
92 #define PIN_ADB PINE
93 #define DDR_ADL DDRA
94 #define DDR_ADH DDRC
95 #define DDR_ADB DDRE
96
97 #define ADB_WIDTH 3
98 #define ADB_SHIFT 2
99 //#define ADB_PORT PORTE
100
101
102 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
103 #define Z80_O_MREQ SBIT(P_MREQ, 4)
104 #define Z80_O_RD SBIT(P_RD, 3)
105 #define Z80_O_WR SBIT(P_WR, 2)
106 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
107 //#define Z80_O_NMI SBIT(P_NMI, )
108 #define Z80_O_RST SBIT(P_RST, 5)
109 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
110 //#define Z80_I_HALT SBIT(P_HALT, )
111
112 /* Optional */
113 #define P_RUN PORTG
114 #define RUN 1
115 #define DDR_RUN DDRG
116 #define P_STEP PORTG
117 #define STEP 0
118 #define DDR_STEP DDRG
119 #define P_WAIT PORTG
120 #define WAIT 2
121 #define DDR_WAIT DDRG
122 /* All three signals are on the same Port (PortG) */
123 #define PORT_SS PORTG
124 #define DDR_SS DDRG
125 #define PIN_SS PING
126 #define Z80_O_RUN SBIT(PORT_SS, RUN)
127 #define Z80_O_STEP SBIT(PORT_SS, STEP)
128 #define Z80_I_WAIT SBIT(PORT_SS, WAIT)
129
130
131 #define BUS_TO 20
132
133
134 #define MASK(n) ((1<<(n))-1)
135 #define SMASK(w,s) (MASK(w) << (s))
136
137
138 static zstate_t zstate;
139 static volatile uint8_t timer; /* used for bus timeout */
140
141 /*---------------------------------------------------------*/
142 /* 10Hz timer interrupt generated by OC4A */
143 /*---------------------------------------------------------*/
144
145 ISR(TIMER5_COMPA_vect)
146 {
147
148 uint8_t i = timer;
149
150 if (i)
151 timer = i - 1;
152 }
153
154 /*--------------------------------------------------------------------------*/
155
156
157 static void z80_addrbus_set_in(void)
158 {
159 /* /MREQ, /RD, /WR: Input, no pullup */
160 DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
161 Z80_O_MREQ = 0;
162 Z80_O_RD = 0;
163 Z80_O_WR = 0;
164
165 P_ADL = 0;
166 DDR_ADL = 0;
167 P_ADH = 0;
168 DDR_ADH = 0;
169 PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
170 DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
171 }
172
173
174 static void z80_addrbus_set_out(void)
175 {
176 /* /MREQ, /RD, /WR: Output and high */
177 Z80_O_MREQ = 1;
178 Z80_O_RD = 1;
179 Z80_O_WR = 1;
180 DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);
181
182 DDR_ADL = 0xff;
183 DDR_ADH = 0xff;
184 DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
185 }
186
187
188 static void z80_dbus_set_in(void)
189 {
190 DDR_DB = 0;
191 P_DB = 0;
192 }
193
194
195 static void z80_dbus_set_out(void)
196 {
197 DDR_DB = 0xff;
198 }
199
200
201 static void z80_reset_pulse(void)
202 {
203 Z80_O_RST = 0;
204 _delay_us(10);
205 Z80_O_RST = 1;
206 }
207
208
209 void z80_setup_bus(void)
210 {
211 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
212
213 /* /ZRESET: Output and low */
214 Z80_O_RST = 0;
215 DDR_RST |= _BV(RST);
216
217 /* /BUSREQ: Output and high */
218 Z80_O_BUSREQ = 1;
219 DDR_BUSREQ |= _BV(BUSREQ);
220
221 /* /BUSACK: Input, no pullup */
222 DDR_BUSACK &= ~_BV(BUSACK);
223 P_BUSACK &= ~_BV(BUSACK);
224
225 z80_addrbus_set_in();
226 z80_dbus_set_in();
227
228 if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
229 /* /RUN & /STEP: output, /WAIT: input */
230
231 PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP);
232 DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
233 }
234
235 zstate = RESET;
236 }
237
238 /* Timer 5 */
239 PRR1 &= ~_BV(PRTIM5);
240 OCR5A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
241 TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
242 TIMSK5 = _BV(OCIE5A); /* Enable oca interrupt */
243
244 }
245
246
247 zstate_t z80_bus_state(void)
248 {
249 return zstate;
250 }
251
252
253 static void z80_busreq_hpulse(void)
254 {
255 z80_dbus_set_in();
256 z80_addrbus_set_in();
257
258 #if 0
259 ATOMIC_BLOCK(ATOMIC_FORCEON) {
260 Z80_O_BUSREQ = 1;
261 Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
262 Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
263 }
264 #endif
265
266 #if 1
267 ATOMIC_BLOCK(ATOMIC_FORCEON) {
268 Z80_O_BUSREQ = 1;
269
270 do {
271 if (Z80_I_BUSACK == 1) {
272 Z80_O_BUSREQ = 0;
273 break;
274 }
275 } while (1);
276 }
277 #endif
278
279 if (zstate & ZST_ACQUIRED) {
280 timer = BUS_TO;
281 while (Z80_I_BUSACK == 1 && timer)
282 ;
283 if (Z80_I_BUSACK == 0)
284 z80_addrbus_set_out();
285 }
286 }
287
288
289 /*
290
291 + | | | | |
292 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
293 + | | | | |
294 + | 0 | 1 | 2 | 3 |
295 Event + | | | | |
296 ----------------+---------------+---------------+---------------+---------------+
297 | | | | |
298 Reset | 0 | 0 | 0 | 0 |
299 | | | | |
300 | | | | |
301 Request | 1 | | 3 | |
302 | | | | |
303 | | | | |
304 Release | | 0 | | 2 |
305 | | | | |
306 | | | | |
307 Run | 2 | 3 | | |
308 | | | | |
309 | | | | |
310 Restart | | | 2 | 3 |
311 | | | | |
312 | | | | |
313 M_Cycle | | | | 3 |
314 | | | | |
315 | | | | |
316 */
317
318 zstate_t z80_bus_cmd(bus_cmd_t cmd)
319 {
320 switch (cmd) {
321
322 case Reset:
323 z80_dbus_set_in();
324 z80_addrbus_set_in();
325 Z80_O_RST = 0;
326 Z80_O_BUSREQ = 1;
327 zstate = RESET;
328 break;
329
330 case Request:
331 switch (zstate) {
332 case RESET:
333 Z80_O_BUSREQ = 0;
334 Z80_O_RST = 1;
335 timer = BUS_TO;
336 while (Z80_I_BUSACK == 1 && timer)
337 ;
338 if (Z80_I_BUSACK == 0) {
339 z80_addrbus_set_out();
340 zstate = RESET_AQRD;
341 } else {
342 Z80_O_RST = 0;
343 Z80_O_BUSREQ = 1;
344 }
345 break;
346
347 case RUNNING:
348 Z80_O_BUSREQ = 0;
349 timer = BUS_TO;
350 while (Z80_I_BUSACK == 1 && timer)
351 ;
352 if (Z80_I_BUSACK == 0) {
353 z80_addrbus_set_out();
354 zstate = RUNNING_AQRD;
355 } else {
356 Z80_O_BUSREQ = 1;
357 }
358 break;
359
360 default:
361 break;
362 }
363 break;
364
365 case Release:
366 switch (zstate) {
367 case RESET_AQRD:
368 z80_dbus_set_in();
369 z80_addrbus_set_in();
370 Z80_O_RST = 0;
371 Z80_O_BUSREQ = 1;
372 zstate = RESET;
373 break;
374 case RUNNING_AQRD:
375 z80_dbus_set_in();
376 z80_addrbus_set_in();
377 Z80_O_BUSREQ = 1;
378 zstate = RUNNING;
379 break;
380 default:
381 break;
382 }
383 break;
384
385 case Run:
386 switch (zstate) {
387 case RESET:
388 Z80_O_RST = 1;
389 zstate = RUNNING;
390 break;
391
392 case RESET_AQRD:
393 z80_dbus_set_in();
394 z80_addrbus_set_in();
395 z80_reset_pulse();
396 z80_addrbus_set_out();
397 zstate = RUNNING_AQRD;
398 break;
399 default:
400 break;
401 }
402 break;
403
404 case Restart:
405 switch (zstate) {
406 case RUNNING:
407 case RUNNING_AQRD:
408 z80_reset_pulse();
409 break;
410 default:
411 break;
412 }
413 break;
414
415 case M_Cycle:
416 switch (zstate) {
417 case RUNNING_AQRD:
418 z80_busreq_hpulse(); /* TODO: */
419 break;
420 default:
421 break;
422 }
423 }
424 return zstate;
425 }
426
427
428 /*--------------------------------------------------------------------------*/
429
430 static
431 //inline __attribute__ ((always_inline))
432 void z80_setaddress(uint32_t addr)
433 {
434 P_ADL = addr;
435 P_ADH = (addr & 0xff00) >> 8;
436 PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
437 }
438
439 void z80_write(uint32_t addr, uint8_t data)
440 {
441 z80_setaddress(addr);
442 Z80_O_MREQ = 0;
443 z80_dbus_set_out();
444 P_DB = data;
445 P_DB = data;
446 Z80_O_WR = 0;
447 Z80_O_WR = 0;
448 Z80_O_WR = 1;
449 Z80_O_MREQ = 1;
450 }
451
452 uint8_t z80_read(uint32_t addr)
453 {
454 uint8_t data;
455
456 z80_setaddress(addr);
457 Z80_O_MREQ = 0;
458 z80_dbus_set_in();
459 Z80_O_RD = 0;
460 Z80_O_RD = 0;
461 Z80_O_RD = 0;
462 data = PIN_DB;
463 Z80_O_RD = 1;
464 Z80_O_MREQ = 1;
465
466 return data;
467 }
468
469
470 void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
471 {
472 z80_dbus_set_out();
473 Z80_O_MREQ = 0;
474 P_DB = data;
475 while(length--) {
476 z80_setaddress(addr++);
477 Z80_O_WR = 0;
478 Z80_O_WR = 0;
479 Z80_O_WR = 1;
480 }
481 Z80_O_MREQ = 1;
482 }
483
484 void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
485 {
486 uint8_t data;
487
488 z80_dbus_set_out();
489 Z80_O_MREQ = 0;
490 while(length--) {
491 z80_setaddress(dest++);
492 data = *src++;
493 P_DB = data;
494 P_DB = data;
495 Z80_O_WR = 0;
496 Z80_O_WR = 0;
497 Z80_O_WR = 1;
498 }
499 Z80_O_MREQ = 1;
500 }
501
502 void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
503 {
504 uint8_t data;
505
506 z80_dbus_set_out();
507 Z80_O_MREQ = 0;
508 while(length--) {
509 z80_setaddress(dest++);
510 data = *src++;
511 P_DB = data;
512 P_DB = data;
513 Z80_O_WR = 0;
514 Z80_O_WR = 0;
515 Z80_O_WR = 1;
516 }
517 Z80_O_MREQ = 1;
518 }
519
520 void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
521 {
522 uint8_t data;
523
524 Z80_O_MREQ = 0;
525 z80_dbus_set_in();
526 while(length--) {
527 z80_setaddress(src++);
528 Z80_O_RD = 0;
529 Z80_O_RD = 0;
530 Z80_O_RD = 0;
531 data = PIN_DB;
532 Z80_O_RD = 1;
533 *dest++ = data;
534 }
535 Z80_O_MREQ = 1;
536 }
537
538
539 /*
540 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
541 017A' rx.in_idx: ds 1 ;
542 017B' rx.out_idx: ds 1 ;
543 017C' rx.buf: ds rx.buf_len ;
544 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
545
546 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
547 018D' tx.in_idx: ds 1 ;
548 018E' tx.out_idx: ds 1 ;
549 018F' tx.buf: ds tx.buf_len ;
550 019E' tx.buf_end equ $-1 ; last byte
551 */
552
553
554 typedef struct __attribute__((packed)) {
555 uint8_t mask;
556 uint8_t in_idx;
557 uint8_t out_idx;
558 uint8_t buf[];
559 } zfifo_t;
560
561
562
563 #define FIFO_BUFSIZE_MASK -3
564 #define FIFO_INDEX_IN -2
565 #define FIFO_INDEX_OUT -1
566
567
568 static struct {
569 uint32_t base;
570 uint8_t idx_out,
571 idx_in,
572 mask;
573 } fifo_dsc[NUM_FIFOS];
574
575
576 void z80_memfifo_init(const fifo_t f, uint32_t addr)
577 {
578 fifo_dsc[f].base = addr;
579
580
581 if (addr != 0) {
582 z80_bus_cmd(Request);
583 fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
584 fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
585 fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
586 z80_bus_cmd(Release);
587
588 if (fifo_dsc[f].idx_in != 0 || fifo_dsc[f].idx_out != 0) {
589 DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
590 f, addr, fifo_dsc[f].idx_in, fifo_dsc[f].idx_out, fifo_dsc[f].mask);
591 }
592 }
593 }
594
595
596 int z80_memfifo_is_empty(const fifo_t f)
597 {
598 int rc = 1;
599
600 if (fifo_dsc[f].base != 0) {
601
602 uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
603 uint8_t idx;
604
605 z80_bus_cmd(Request);
606 idx = z80_read(adr);
607 z80_bus_cmd(Release);
608 rc = idx == fifo_dsc[f].idx_out;
609 }
610
611 return rc;
612 }
613
614 int z80_memfifo_is_full(const fifo_t f)
615 {
616 int rc = 0;
617
618 if (fifo_dsc[f].base != 0) {
619 z80_bus_cmd(Request);
620 rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
621 == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
622 z80_bus_cmd(Release);
623 }
624 return rc;
625 }
626
627
628 uint8_t z80_memfifo_getc_wait(const fifo_t f)
629 {
630 uint8_t rc, idx;
631
632 while (z80_memfifo_is_empty(f))
633 ;
634
635 z80_bus_cmd(Request);
636 idx = fifo_dsc[f].idx_out;
637 rc = z80_read(fifo_dsc[f].base+idx);
638 fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
639 z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
640 z80_bus_cmd(Release);
641
642 return rc;
643 }
644
645 int z80_memfifo_getc(const fifo_t f)
646 {
647 int rc = -1;
648
649 if (fifo_dsc[f].base != 0) {
650 uint8_t idx = fifo_dsc[f].idx_out;
651 z80_bus_cmd(Request);
652 if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
653 rc = z80_read(fifo_dsc[f].base+idx);
654 fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
655 z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
656 }
657 z80_bus_cmd(Release);
658 }
659
660 return rc;
661 }
662
663
664 void z80_memfifo_putc(fifo_t f, uint8_t val)
665 {
666 int idx;
667
668 while (z80_memfifo_is_full(f))
669 ;
670
671 z80_bus_cmd(Request);
672 idx = fifo_dsc[f].idx_in;
673 z80_write(fifo_dsc[f].base+idx, val);
674 fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
675 z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
676 z80_bus_cmd(Release);
677 }
Z180 Stamp Monitor