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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z180-serv.c
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <util/atomic.h>
13 #include "background.h"
19 #include "print-utils.h"
20 #include "z180-serv.h"
24 #define DEBUG_CPM_SDIO 0 /* set to 1 to debug */
26 #define debug_cpmsd(fmt, args...) \
27 debug_cond(DEBUG_CPM_SDIO, fmt, ##args)
31 /*--------------------------------------------------------------------------*/
34 uint8_t z80_get_byte(uint32_t adr
)
46 /*--------------------------------------------------------------------------*/
50 uint8_t sub_min
, sub_max
;
51 void (*func
)(uint8_t, int, uint8_t *);
54 uint32_t msg_to_addr(uint8_t *msg
)
70 static int msg_xmit_header(uint8_t func
, uint8_t subf
, int len
)
72 z80_memfifo_putc(fifo_msgout
, 0xAE);
73 z80_memfifo_putc(fifo_msgout
, len
+2);
74 z80_memfifo_putc(fifo_msgout
, func
);
75 z80_memfifo_putc(fifo_msgout
, subf
);
80 int msg_xmit(uint8_t func
, uint8_t subf
, int len
, uint8_t *msg
)
82 msg_xmit_header(func
, subf
, len
);
84 z80_memfifo_putc(fifo_msgout
, *msg
++);
89 void do_msg_ini_memfifo(uint8_t subf
, int len
, uint8_t * msg
)
93 z80_memfifo_init(subf
, msg_to_addr(msg
));
97 void do_msg_char_out(uint8_t subf
, int len
, uint8_t * msg
)
106 void do_msg_echo(uint8_t subf
, int len
, uint8_t * msg
)
111 msg_xmit(1, 3, len
, msg
);
114 /* ---------------------------------------------------------------------------*/
117 #define BLOCK_SIZE 512
118 #define TPA_BASE 0x10000
119 #define COMMON_BASE 0xC000
128 static uint8_t disk_buffer
[BLOCK_SIZE
];
129 static struct cpm_drive_s drv_table
[MAX_DRIVE
];
133 ds 1 ; subcommand (login/read/write)
134 ds 1 ; @adrv (8 bits) +0
135 ds 1 ; @rdrv (8 bits) +1
136 ds 3 ; @xdph (24 bits) +2
139 void do_msg_cpm_login(uint8_t subf
, int len
, uint8_t * msg
)
146 uint8_t result_msg
[3];
150 if (len
!= 5) { /* TODO: check adrv, rdrv */
155 debug_cpmsd("\n## %7lu login: %c:\n", get_timer(0), msg
[0]+'A');
159 if ( drv
>= MAX_DRIVE
) {
165 uint32_t dph = ((uint32_t)msg[4] << 16) + ((uint16_t)msg[3] << 8) + msg[2];
168 if (drv_table
[drv
].img_name
!= NULL
) {
169 debug_cpmsd("## %7lu close: '%s'\n", get_timer(0), drv_table
[drv
].img_name
);
170 f_close(&drv_table
[drv
].fd
);
171 free(drv_table
[drv
].img_name
);
172 drv_table
[drv
].img_name
= NULL
;
175 strcpy_P((char *)disk_buffer
, PSTR("dsk0"));
176 disk_buffer
[3] = msg
[0] + '0';
177 if (((np
= getenv((char*)disk_buffer
)) == NULL
) ||
178 ((drv_table
[drv
].img_name
= strdup(np
)) == NULL
)) {
184 res
= f_open(&drv_table
[drv
].fd
, drv_table
[drv
].img_name
,
187 debug_cpmsd("## %7lu open: '%s', (env: '%s'), res: %d\n", get_timer(0),
188 drv_table
[drv
].img_name
, disk_buffer
, res
);
197 result_msg
[2] = res
>> 8;
200 debug_cpmsd("## %7lu error rc: %.02x, res: %d\n", get_timer(0), rc
, res
);
204 msg_xmit(2, subf
, sizeof(result_msg
), result_msg
);
210 ds 1 ; subcommand (login/read/write)
211 ds 1 ; @adrv (8 bits) +0
212 ds 1 ; @rdrv (8 bits) +1
213 ds 2 ; @trk (16 bits) +2
214 ds 2 ; @sect(16 bits) +4
215 ds 1 ; @cnt (8 bits) +6
216 ds 3 ; phys. transfer addr +7
226 void do_msg_cpm_rw(uint8_t subf
, int len
, uint8_t * msg
)
232 bool dowrite
= (subf
== 2);
236 uint8_t result_msg
[3];
238 if (len
!= 10) { /* TODO: check adrv, rdrv */
244 if ( drv
>= MAX_DRIVE
) {
250 addr
= ((uint32_t)msg
[ADDR
+2] << 16) + ((uint16_t)msg
[ADDR
+1] << 8) + msg
[ADDR
];
253 /* TODO: tracks per sector from dpb */
254 pos
= (((uint16_t)(msg
[TRK
+1] << 8) + msg
[TRK
]) * 8
255 + ((uint32_t)(msg
[SEC
+1] << 8) + msg
[SEC
])) * BLOCK_SIZE
;
257 debug_cpmsd("## %7lu cpm_rw: %s %c: trk:%4d, sec: %d, pos: %.8lx, secs: %2d, "
258 "addr: %.5lx\n", get_timer(0), dowrite
? "write" : " read",
259 msg
[ADRV
]+'A', ((uint16_t)(msg
[TRK
+1] << 8) + msg
[TRK
]), msg
[SEC
],
260 pos
, msg
[CNT
], addr
);
262 res
= f_lseek(&drv_table
[drv
].fd
, pos
);
263 while (!res
&& secs
--) {
264 unsigned int cnt
, br
;
266 /* check bank boundary crossing */
268 if (addr
< (TPA_BASE
+ COMMON_BASE
) &&
269 (addr
+ BLOCK_SIZE
) > (TPA_BASE
+ COMMON_BASE
)) {
270 cnt
= (TPA_BASE
+ COMMON_BASE
) - addr
;
274 debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr
, cnt
);
275 debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr
+cnt
-TPA_BASE
, BLOCK_SIZE
-cnt
);
279 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
)) {
284 z80_read_block(disk_buffer
, addr
, cnt
);
285 addr
= addr
+ cnt
- TPA_BASE
;
287 z80_read_block(disk_buffer
+cnt
, addr
, BLOCK_SIZE
- cnt
);
288 z80_bus_cmd(Release
);
290 res
= f_write(&drv_table
[drv
].fd
, disk_buffer
, BLOCK_SIZE
, &br
);
292 res
= f_read(&drv_table
[drv
].fd
, disk_buffer
, BLOCK_SIZE
, &br
);
293 if (res
== FR_OK
&& br
== BLOCK_SIZE
) {
294 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
)) {
299 z80_write_block(disk_buffer
, addr
, cnt
);
300 addr
= addr
+ cnt
- TPA_BASE
;
302 z80_write_block(disk_buffer
+cnt
, addr
, BLOCK_SIZE
- cnt
);
303 z80_bus_cmd(Release
);
308 if (br
!= BLOCK_SIZE
) {
309 debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res
, br
);
310 dump_ram(disk_buffer
, 0, 64, "Read Data");
318 res
= f_sync(&drv_table
[drv
].fd
);
322 debug_cpmsd("Bus timeout\n");
330 result_msg
[2] = res
>> 8;
333 debug_cpmsd("###%7lu error rc: %.02x, res: %d\n", get_timer(0), rc
, res
);
337 msg_xmit(2, subf
, sizeof(result_msg
), result_msg
);
341 const FLASH
struct msg_item z80_messages
[] =
344 1, 3, /* sub fct nr. from, to */
358 { 0xff, /* end mark */
367 void do_message(int len
, uint8_t *msg
)
369 uint8_t fct
, sub_fct
;
377 while (fct
!= z80_messages
[i
].fct
) {
378 if (z80_messages
[i
].fct
== 0xff) {
379 DBG_P(1, "do_message: Unknown function: %i, %i\n",
381 return; /* TODO: unknown message # */
387 while (fct
== z80_messages
[i
].fct
) {
388 if (sub_fct
>= z80_messages
[i
].sub_min
&&
389 sub_fct
<= z80_messages
[i
].sub_max
)
394 if (z80_messages
[i
].fct
!= fct
) {
395 DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
397 return; /* TODO: unknown message sub# */
400 (z80_messages
[i
].func
)(sub_fct
, len
, msg
);
405 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len
);
411 #define CTRBUF_LEN 256
413 void check_msg_fifo(void)
416 static int_fast8_t state
;
417 static int msglen
,idx
;
418 static uint8_t buffer
[CTRBUF_LEN
];
420 while ((ch
= z80_memfifo_getc(fifo_msgin
)) >= 0) {
422 case 0: /* wait for start of message */
423 if (ch
== 0xAE) { /* TODO: magic number */
429 case 1: /* get msg len */
430 if (ch
> 0 && ch
<= CTRBUF_LEN
) {
436 case 2: /* get message */
439 do_message(msglen
, buffer
);
448 int msg_handling(int state
)
452 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
453 pending
= (Stat
& S_MSG_PENDING
) != 0;
454 Stat
&= ~S_MSG_PENDING
;
459 case 0: /* need init */
460 /* Get address of fifo_list */
461 z80_bus_cmd(Request
);
462 uint32_t fifo_list
= z80_read(0x40) +
463 ((uint16_t) z80_read(0x41) << 8) +
464 ((uint32_t) z80_read(0x42) << 16);
465 z80_bus_cmd(Release
);
466 if (fifo_list
!= 0) {
467 /* Get address of fifo 0 */
468 z80_bus_cmd(Request
);
469 uint32_t fifo_addr
= z80_read(fifo_list
) +
470 ((uint16_t) z80_read(fifo_list
+1) << 8) +
471 ((uint32_t) z80_read(fifo_list
+2) << 16);
472 z80_bus_cmd(Release
);
473 if (fifo_addr
!= 0) {
474 z80_memfifo_init(fifo_msgin
, fifo_addr
);
479 case 1: /* awaiting messages */
489 static int handle_msg_handling
;
491 void setup_z180_serv(void)
494 handle_msg_handling
= bg_register(msg_handling
, 0);
497 void restart_z180_serv(void)
499 z80_bus_cmd(Request
);
503 z80_bus_cmd(Release
);
505 for (int i
= 0; i
< NUM_FIFOS
; i
++)
506 z80_memfifo_init(i
, 0);
507 bg_setstat(handle_msg_handling
, 0);
511 /*--------------------------------------------------------------------------*/
513 const FLASH
uint8_t iniprog
[] = {
515 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
516 0x3E, 0x30, // ld a,030h
517 0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states
520 const FLASH
uint8_t sertest
[] = {
522 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
523 0x3E, 0x30, // ld a,030h
524 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
525 0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0
526 0xED, 0x39, 0x03, // out0 (cntlb1),a
527 0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ;
528 0xED, 0x39, 0x01, // out0 (cntla1),a
529 0x3E, 0x00, // ld a,0
530 0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts
531 0xED, 0x38, 0x05, //l0:in0 a,(stat1)
532 0xE6, 0x80, // and 80h
533 0x28, 0xF9, // jr z,l0
534 0xED, 0x00, 0x09, // in0 b,(rdr1)
535 0xED, 0x38, 0x05, //l1:in0 a,(stat1)
536 0xE6, 0x02, // and 02h
537 0x28, 0xF9, // jr z,l1
538 0xED, 0x01, 0x07, // out0 (tdr1),b
542 const FLASH
uint8_t test1
[] = {
544 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
545 0x3E, 0x30, // ld a,030h
546 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
547 0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers
548 0x06, 0x08, // ld b,dmct_e-dmclrt
549 0x0E, 0x20, // ld c,sar0l
551 0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst
552 0xED, 0x39, 0x31, // out0 (dmode),a ;
553 0x3E, 0x62, // ld a,062h ;enable dma0,
554 0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k
555 0x18, 0xFB, // jr cl_1 ;
556 0x00, 0x00, //dmclrt: dw 0 ;src (inc)
558 0x00, 0x00, // dw 0 ;dst (inc),
560 0x00, 0x00, // dw 0 ;count (64k)