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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/i2c.c
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
4 * SPDX-License-Identifier: GPL-2.0+
8 * I2C (TWI) master interface.
12 #include <avr/interrupt.h>
21 #define debug_i2c(fmt, args...) \
22 debug_cond(DEBUG_I2C, fmt, ##args)
25 /* General TWI Master status codes */
26 #define TWI_START 0x08 /* START has been transmitted */
27 #define TWI_REP_START 0x10 /* Repeated START has been transmitted */
28 #define TWI_ARB_LOST 0x38 /* Arbitration lost */
30 /* TWI Master Transmitter status codes */
31 #define TWI_MTX_ADR_ACK 0x18 /* SLA+W has been transmitted and ACK received */
32 #define TWI_MTX_ADR_NACK 0x20 /* SLA+W has been transmitted and NACK received */
33 #define TWI_MTX_DATA_ACK 0x28 /* Data byte has been transmitted and ACK received */
34 #define TWI_MTX_DATA_NACK 0x30 /* Data byte has been transmitted and NACK received */
36 /* TWI Master Receiver status codes */
37 #define TWI_MRX_ADR_ACK 0x40 /* SLA+R has been transmitted and ACK received */
38 #define TWI_MRX_ADR_NACK 0x48 /* SLA+R has been transmitted and NACK received */
39 #define TWI_MRX_DATA_ACK 0x50 /* Data byte has been received and ACK transmitted */
40 #define TWI_MRX_DATA_NACK 0x58 /* Data byte has been received and NACK transmitted */
42 /* TWI Miscellaneous status codes */
43 #define TWI_NO_STATE 0xF8 /* No relevant state information available */
44 #define TWI_BUS_ERROR 0x00 /* Bus error due to an illegal START or STOP condition */
48 * TWINT: TWI Interrupt Flag
49 * TWEA: TWI Enable Acknowledge Bit
50 * TWSTA: TWI START Condition Bit
51 * TWSTO: TWI STOP Condition Bit
52 * TWEN: TWI Enable Bit
53 * TWIE: TWI Interrupt Enable
55 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)
56 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)| (1<<TWEA)
57 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)
60 * (1<<TWEN)| (1<<TWINT)| (1<<TWSTO)
66 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
67 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
68 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
69 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
72 * (1<<TWIE)|(1<<TWSTO)
78 * 0b10000000 Busy (Transmission in progress)
80 * 0b00001000 Start transmitted
81 * 0b00000100 Slave acknowledged address
82 * 0b00000010 Data byte(s) transmitted/received
83 * 0b00000001 Transmission completed
86 *----------------------------------------------------------------------
89 #define TWI_C_DISABLE 0x00
90 #define TWI_C_ENABLE (1<<TWEN)
94 typedef struct i2c_msg_s
{
96 #define XMIT_DONE (1<<0)
97 #define DATA_ACK (1<<1)
98 #define ADDR_ACK (1<<2)
100 #define TIMEOUT (1<<6)
104 uint8_t buf
[CONFIG_SYS_I2C_BUFSIZE
];
107 static volatile i2c_msg_t xmit
;
117 tmp_stat
= xmit
.stat
;
121 switch (twsr
& 0xf8) {
125 tmp_stat
= BUSY
| START
;
126 tmp_idx
= 0; /* reset xmit_buf index */
128 if (tmp_idx
< xmit
.len
) { /* all bytes transmited? */
129 TWDR
= xmit
.buf
[tmp_idx
];
131 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
);
133 tmp_stat
|= XMIT_DONE
;
135 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
139 case TWI_MTX_ADR_ACK
:
140 case TWI_MTX_DATA_ACK
:
141 if ((twsr
&0xf8) == TWI_MTX_ADR_ACK
)
142 tmp_stat
|= ADDR_ACK
;
144 tmp_stat
|= DATA_ACK
;
146 if (tmp_idx
< xmit
.len
) { /* all bytes transmited? */
147 TWDR
= xmit
.buf
[tmp_idx
];
149 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
);
151 tmp_stat
|= XMIT_DONE
;
153 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
157 case TWI_MTX_DATA_NACK
:
158 tmp_stat
|= XMIT_DONE
;
160 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
163 case TWI_MRX_DATA_ACK
:
164 xmit
.buf
[tmp_idx
] = TWDR
;
167 case TWI_MRX_ADR_ACK
:
168 if ((twsr
&0xf8) == TWI_MRX_ADR_ACK
)
169 tmp_stat
|= ADDR_ACK
;
171 tmp_stat
|= DATA_ACK
;
175 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
)|(1<<TWEA
);
177 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
);
181 case TWI_MRX_DATA_NACK
:
182 tmp_stat
|= ADDR_ACK
| DATA_ACK
;
184 xmit
.buf
[tmp_idx
] = TWDR
;
189 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
193 xmit
.stat
= tmp_stat
;
196 debug_i2c("|%02x", twsr
);
201 /*------------------------------------------------------------------*/
207 static void _init(void)
211 /* Disable TWI, disable TWI interrupt. */
212 /* (Reset TWI hardware state machine.) */
213 TWCR
= TWI_C_DISABLE
;
216 memset((void *) xmit
.buf
, 0xdf, sizeof(xmit
.buf
));
225 void i2c_init(uint32_t speed
)
228 uint32_t tmp_twbr
= F_CPU
/2 / speed
- 8;
230 while (tmp_twbr
> 255) {
234 debug_cond((twps
> 3), "*** TWCLK too low: %lu Hz\n", speed
);
236 twbr
= (uint8_t) tmp_twbr
;
243 int_fast8_t i2c_waitready(void)
245 uint32_t timer
= get_timer(0);
249 if (get_timer(timer
) >= 30) {
253 } while ((TWCR
& ((1<<TWIE
)|(1<<TWSTO
))) != 0 && !timeout
);
255 xmit
.stat
|= timeout
;
258 dump_ram((uint8_t *) &xmit
, 4, "=== i2c_wait ready: (done)");
265 int i2c_send(uint8_t chip
, uint16_t addr
, uint8_t alen
, uint8_t *buffer
, int8_t len
)
270 rc
= i2c_waitready();
271 if ((rc
& (BUSY
| TIMEOUT
)) != 0)
275 xmit
.buf
[0] = chip
<<1;
276 for (i
= 1; i
< alen
+1; i
++) {
277 xmit
.buf
[i
] = (uint8_t) addr
;
280 for (n
= len
+ i
; i
< n
; i
++)
281 xmit
.buf
[i
] = *buffer
++;
285 dump_ram((uint8_t *) &xmit
, 0x20, "=== i2c_send");
288 /* Enable TWI, TWI int and initiate start condition */
289 TWCR
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
)|(1<<TWSTA
);
297 int i2c_recv(uint8_t chip
, uint8_t *buffer
, int8_t len
)
301 rc
= i2c_waitready();
302 if ((rc
& (BUSY
| TIMEOUT
)) != 0)
307 xmit
.buf
[0] = (chip
<<1) | 1;
310 dump_ram((uint8_t *) &xmit
, 0x20, "=== i2c_recv: before start");
313 /* Enable TWI, TWI int and initiate start condition */
314 TWCR
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
)|(1<<TWSTA
);
315 rc
= i2c_waitready();
318 dump_ram((uint8_t *) &xmit
, 0x20, "=== i2c_recv: after completion");
322 /* at least 1 byte received */
323 for (uint8_t i
=1, n
=xmit
.idx
; i
< n
; i
++)
324 *buffer
++ = xmit
.buf
[i
];
331 * Read/Write interface:
332 * chip: I2C chip address, range 0..127
333 * addr: Memory (register) address within the chip
334 * alen: Number of bytes to use for addr (typically 1, 2 for larger
335 * memories, 0 for register type devices with only one
337 * buffer: Where to read/write the data
338 * len: How many bytes to read/write
340 * Returns: 0 on success, not 0 on failure
343 int i2c_write(uint8_t chip
, unsigned int addr
, uint_fast8_t alen
,
344 uint8_t *buffer
, uint_fast8_t len
)
348 if ((alen
> 2) || (1 + alen
+ len
> CONFIG_SYS_I2C_BUFSIZE
)) {
349 debug("** i2c_write: buffer overflow, alen: %u, len: %u\n",
354 i2c_send(chip
, addr
, alen
, buffer
, len
);
355 rc
= i2c_waitready();
357 return (rc
& XMIT_DONE
) != 0;
360 int i2c_read(uint8_t chip
, unsigned int addr
, uint_fast8_t alen
,
361 uint8_t *buffer
, uint_fast8_t len
)
365 if ((alen
> 2) || (1 + len
> CONFIG_SYS_I2C_BUFSIZE
)) {
366 debug("** i2c_read: parameter error: alen: %u, len: %u\n",
372 i2c_send(chip
, addr
, alen
, NULL
, 0);
374 rc
= i2c_recv(chip
, buffer
, len
);
376 return !((rc
& (XMIT_DONE
|DATA_ACK
)) == (XMIT_DONE
|DATA_ACK
));