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[z180-stamp.git] / z180 / init.180
1 page 255
2 .z80
3
4 extrn ddtz,bpent
5 extrn $stack
6 extrn charini,?const,?conin
7 extrn ?cono,?conos
8 extrn romend
9
10
11 global iobyte
12 global isv_sw
13
14 include config.inc
15 if CPU_Z180
16 include z180reg.inc
17 include z180.lib
18 endif
19
20
21
22
23 ;----------------------------------------------------------------------
24
25 cseg
26 romstart equ $
27
28 org romstart+0
29 jp start
30
31 iobyte: db 2
32
33 ; restart vectors
34
35 rsti defl 1
36 rept 7
37 org 8*rsti + romstart
38 jp bpent
39 rsti defl rsti+1
40 endm
41
42 ;----------------------------------------------------------------------
43 ; Config space
44 ;
45
46 org romstart+40h
47
48 dw 0
49 db 0
50
51
52 if ROMSYS
53 $crom: defb c$rom ;
54 else
55 db 0 ;
56 endif
57
58 INIWAITS defl CWAITIO
59 if ROMSYS
60 INIWAITS defl INIWAITS+CWAITROM
61 endif
62
63 ;----------------------------------------------------------------------
64
65 org romstart+50h
66 start:
67 jp cstart
68 jp wstart
69 jp ?const
70 jp ?conin
71 jp ?cono
72 jp ?conos
73 jp charini
74
75 ;----------------------------------------------------------------------
76
77 hwini0:
78 if CPU_Z180
79 db 3 ;count
80 db rcr,CREFSH ;configure DRAM refresh
81 db dcntl,INIWAITS ;wait states
82 db cbr,SYS$CBR
83 db cbar,SYS$CBAR
84 endif
85 db 0
86
87 if CPU_Z180
88 dmclrt: ;clear ram per dma
89 db dmct_e-dmclrt-2 ;
90 db sar0l ;first port
91 dw nullbyte ;src (fixed)
92 nullbyte:
93 db 000h ;src
94 dw romend ;dst (inc), start after "rom" code
95 db 00h ;dst
96 dw 0-romend ;count (64k)
97 dmct_e:
98 db 0
99 endif
100
101
102 cstart:
103 if CPU_Z180
104
105 push af
106 in0 a,(itc) ;Illegal opcode trap?
107 jp m,??st01
108 ld a,i ;I register == 0 ?
109 jr z,hw_reset ; yes, harware reset
110
111 ??st01:
112 ; TODO: SYS$CBR
113 ld a,(syscbr)
114 out0 (cbr),a
115 pop af ;restore registers
116 jp bpent ;
117
118 hw_reset:
119 di ;0058
120 ld a,CREFSH
121 out0 (rcr),a ; configure DRAM refresh
122 ld a,CWAITIO
123 out0 (dcntl),a ; wait states
124
125 ld a,M_NCD ;No Clock Divide
126 out0 (ccr),a
127 ; ld a,M_X2CM ;X2 Clock Multiplier
128 ; out0 (cmr),a
129 else
130 di
131 xor a
132 ld (@cbnk),a
133 endif
134
135 ; check warm start mark
136
137 ld ix,mark_55AA ; top of common area
138 ld a,0aah ;
139 cp (ix+000h) ;
140 jr nz,kstart ;
141 cp (ix+002h) ;
142 jr nz,kstart ;
143 cpl ;
144 cp (ix+001h) ;
145 jr nz,kstart ;
146 cp (ix+003h) ;
147 jr nz,kstart ;
148 ld sp,$stack ; mark found, check
149 jp z,wstart ; check ok,
150
151 ; ram not ok, initialize -- kstart --
152
153 kstart:
154 if CPU_Z180
155 ld a,SYS$CBR
156 out0 (cbr),a
157 ld a,SYS$CBAR
158 out0 (cbar),a
159 endif
160
161 ld sp,$stack ;01e1
162
163 ; Clear RAM using DMA0
164
165 if CPU_Z180
166 if 0
167
168 ld hl,dmclrt ;load DMA registers
169 call ioiniml
170 ld a,0cbh ;01ef dst +1, src fixed, burst
171 out0 (dmode),a ;01f1
172
173 ld b,512/64
174 ld a,062h ;01f4 enable dma0,
175 ??cl_1:
176 out0 (dstat),a ;01f9 clear (up to) 64k
177 djnz ??cl_1 ; end of RAM?
178
179 endif
180 endif
181
182 ld hl,055AAh ;set warm start mark
183 ld (mark_55AA),hl
184 ld (mark_55AA+2),hl
185
186 ; -- wstart --
187
188 wstart:
189 call sysram_init
190 call ivtab_init
191 if CPU_Z180
192 ; call prt0_init
193 endif
194
195 call charini
196 call bufferinit
197
198 if CPU_Z80
199 ld a,0
200 call selbnk
201 endif
202
203 ld a,INIDONEVAL ;tell others (CP/M) that hardware and fifos
204 ld (INIDONE),a ; are allready initialized
205
206 im 2
207 ei
208
209 call ?const
210 call ?const
211 or a
212 call nz,?conin
213
214 if CPU_Z180
215 ld e,0 ;Sys$Bank
216 else
217 ; TODO:
218 endif
219 jp ddtz
220
221
222 if CPU_Z180
223 ; TODO: SYS$CBR
224 syscbr: db 0
225 endif
226
227 ;
228 ;----------------------------------------------------------------------
229 ;
230
231 global buf.init
232
233 buf.init:
234 ld (ix+o.in_idx),0
235 ld (ix+o.out_idx),0
236
237 ld a,(ix+o.id)
238 cp 4
239 ret nc
240
241 push de
242 push hl
243 ld hl,fifo_list
244 push hl ;save fifo_list
245 ld e,a
246 ld d,0
247 add hl,de
248 add hl,de
249 push ix
250 pop de
251 ld (hl),e
252 inc hl
253 ld (hl),d
254 pop hl ;get fifo_list back
255 or a
256 jr nz,bufi_ex
257
258 ld (040h),hl
259 ld (040h+2),a
260 bufi_ex:
261 pop hl
262 pop de
263
264 ret
265
266
267 fifo_list:
268 rept 4
269 dw 0
270 endm
271
272 ;----------------------------------------------------------------------
273
274 extrn msginit,msg.sout
275 extrn mtx.fifo,mrx.fifo
276 extrn co.fifo,ci.fifo
277
278
279 bufferinit:
280 if CPU_Z180
281 call msginit
282
283 ld hl,buffers
284 ld b,buftablen
285 bfi_1:
286 ld a,(hl)
287 inc hl
288 ld (bufdat+0),a
289 ld e,(hl)
290 inc hl
291 ld d,(hl)
292 inc hl
293 ex de,hl
294
295 or a
296 jr nz,bfi_2
297 ; call hwl2phy
298 ; ld (40h+0),hl
299 ; ld (40h+2),a
300 out (AVRINT5),a
301 jr bfi_3
302 bfi_2:
303 call hwl2phy
304 ld (bufdat+1),hl
305 ld (bufdat+3),a
306 ld hl,inimsg
307 call msg.sout
308 bfi_3:
309 ex de,hl
310 djnz bfi_1
311 ret
312
313 else ;CPU_Z180
314
315 call msginit
316
317 ld hl,buffers
318 ld b,buftablen
319 bfi_1:
320 ld a,(hl)
321 inc hl
322 ld (bufdat+0),a
323 ld e,(hl)
324 inc hl
325 ld d,(hl)
326 inc hl
327 ex de,hl
328
329 or a
330 jr nz,bfi_2
331
332 ld a,(@cbnk)
333 call bnk2phy
334
335 ld (40h+0),hl
336 ld (40h+2),a
337 out (AVRINT5),a
338 jr bfi_3
339 bfi_2:
340
341 ld a,(@cbnk)
342 call bnk2phy
343
344 ld (bufdat+1),hl
345 ld (bufdat+3),a
346 ld hl,inimsg
347 call msg.sout
348 bfi_3:
349 ex de,hl
350 djnz bfi_1
351 ret
352 endif
353
354 buffers:
355 db 0
356 dw mtx.fifo
357 db 1
358 dw mrx.fifo
359 db 2
360 dw ci.fifo
361 db 3
362 dw co.fifo
363 buftablen equ ($ - buffers)/3
364
365 inimsg:
366 db inimsg_e - $ -1
367 db 0AEh
368 db inimsg_e - $ -1
369 db 0
370 bufdat:
371 db 0
372 dw 0
373 db 0
374 inimsg_e:
375
376
377 ;
378 ;----------------------------------------------------------------------
379 ;
380
381 sysram_init:
382 ld hl,sysramw
383 ld de,topcodsys
384 ld bc,sysrame-sysramw
385 ldir
386
387 ret
388
389 ;----------------------------------------------------------------------
390
391 ivtab_init:
392 ld hl,ivtab ;
393 ld a,h ;
394 ld i,a ;
395 if CPU_Z180
396 out0 (il),l ;
397 endif
398
399 ; Let all vectors point to spurious int routines.
400
401 ld d,high sp.int0
402 ld a,low sp.int0
403 ld b,9
404 ivt_i1:
405 ld (hl),a
406 inc l
407 ld (hl),d
408 inc l
409 add a,sp.int.len
410 djnz ivt_i1
411 ret
412
413 ;----------------------------------------------------------------------
414
415 ; Reload value for 10 ms Int. (0.1KHz):
416 ; tc10ms = phi/prescale/0.1KHz = phi / (prescale/10)
417
418 PRT_TC10MS equ 18432 / (PRT_PRE/10)
419
420
421 if CPU_Z180
422 prt0_init:
423 ld a,i
424 ld h,a
425 in0 a,(il)
426 and 0E0h
427 or IV$PRT0
428 ld l,a
429 ld (hl),low iprt0
430 inc hl
431 ld (hl),high iprt0
432 ld hl,prt0itab
433 call ioiniml
434 ret
435
436 prt0itab:
437 db prt0it_e-prt0itab-2
438 db tmdr0l
439 dw PRT_TC10MS
440 dw PRT_TC10MS
441 db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.
442 prt0it_e:
443 db 0
444 endif
445
446
447 ;
448 ;----------------------------------------------------------------------
449 ;
450
451 if CPU_Z180
452 io.ini:
453 if 0
454 push bc
455 ld b,0 ;high byte port adress
456 ioi_nxt:
457 ld a,(hl) ;count
458 inc hl
459 or a
460 jr z,ioi_e
461
462 ld c,(hl) ;port address
463 inc hl
464 ioi_r:
465 outi
466 inc b ;outi decrements b
467 dec a
468 jr nz,ioi_r
469 jr ioi_nxt
470 ioi_e:
471 pop bc
472 ret
473
474 else ;(if 1/0)
475
476 push bc
477 jr ioi_nxt
478 ioi_l:
479 ld c,(hl) ;port address
480 inc hl
481 inc c
482 ioi_r:
483 dec c ;otim increments c
484 otim
485 jr z,ioi_r
486 ioi_nxt:
487 ld b,(hl) ;count
488 inc hl
489 inc b ;stop if count == 0
490 djnz ioi_l
491 pop bc
492 ret
493
494 endif ;(1/0)
495
496 else
497
498 io.ini:
499 push bc
500 jr ioi_nxt
501 ioi_l:
502 ld c,(hl) ;port address
503 inc hl
504 otir
505 ioi_nxt:
506 ld b,(hl) ;count
507 inc hl
508 inc b
509 djnz ioi_l
510 endif
511 pop bc
512 ret
513
514 ;----------------------------------------------------------------------
515
516 if CPU_Z180
517
518 global ioiniml
519
520 ioiniml:
521 push bc
522 xor a
523 ioml_lp:
524 ld b,(hl)
525 inc hl
526 cp b
527 jr z,ioml_e
528
529 ld c,(hl)
530 inc hl
531 otimr
532 jr ioml_lp
533 ioml_e:
534 pop bc
535 ret z
536 endif
537
538 io.ini.l:
539 ;
540
541
542
543 ;----------------------------------------------------------------------
544 ;
545 if CPU_Z180
546
547 ;--------------------------------------------------------------------
548 ; Return the BBR value for the given bank number
549 ;
550 ; in a: Bank number
551 ; out a: bbr value
552
553 bnk2log:
554 or a ;
555 ret z ; Bank 0 is at physical address 0
556
557 push bc ;
558 ld b,a ;
559 ld c,CA ;
560 mlt bc ;
561 ld a,c ;
562 add a,10h ;
563 pop bc ;
564 ret ;
565
566 ;--------------------------------------------------------------
567
568 ;in hl: Log. Address
569 ; a: Bank number
570 ;
571 ;out ahl: Phys. (linear) Address
572
573
574 bnk2phy:
575 call bnk2log
576 ; fall thru
577
578 ;--------------------------------------------------------------
579 ;
580 ; hl: Log. Address
581 ; a: Bank base (bbr)
582 ;
583 ; 2 0 0
584 ; 0 6 8 0
585 ; hl hhhhhhhhllllllll
586 ; a + bbbbbbbb
587 ;
588 ; OP: ahl = (a<<12) + (h<<8) + l
589 ;
590 ;out ahl: Phys. (linear) Address
591
592 log2phy:
593 push bc ;
594 l2p_i:
595 ld c,a ;
596 ld b,16 ;
597 mlt bc ; bc = a<<4
598 ld a,c ;
599 add a,h ;
600 ld h,a ;
601 ld a,b ;
602 adc a,0 ;
603 pop bc ;
604 ret ;
605
606 ;--------------------------------------------------------------
607 ;
608 ; hl: Log. Address
609 ;
610 ;
611 ; OP: ahl = (bankbase<<12) + (d<<8) + e
612 ;
613 ;out ahl: Phys. (linear) Address
614
615
616 hwl2phy:
617 push bc ;
618 in0 c,(cbar) ;
619 ld a,h ;
620 or 00fh ; log. addr in common1?
621 cp c
622 jr c,hlp_1
623
624 in0 a,(cbr) ; yes, cbr is address base
625 jr hl2p_x
626 hlp_1:
627 ld b,16 ; log. address in baked area?
628 mlt bc
629 ld a,h
630 cp c
631 jr c,hlp_2
632 in0 a,(bbr) ; yes, bbr is address base
633 jr hl2p_x
634 hlp_2:
635 xor a ; common1
636 hl2p_x:
637 jr nz,l2p_i
638
639 pop bc ; bank part is 0, no translation
640 ret ;
641
642
643
644 else ;CPU_Z180
645
646 ;----------------------------------------------------------------------
647 ;
648
649 bnk2phy:
650 sla h
651 jr nc,b2p_1 ;A15=1 --> common
652 ld a,3
653 b2p_1:
654 srl a
655 rr h
656 ret
657
658 endif
659
660 ;--------------------------------------------------------------
661 ;
662 ;return:
663 ; hl = hl + a
664 ; Flags undefined
665 ;
666
667 add_hl_a:
668 add a,l
669 ld l,a
670 ret nc
671 inc h
672 ret
673
674 ; ---------------------------------------------------------
675
676 sysramw:
677
678 .phase isvsw_loc
679 topcodsys:
680
681 ; Trampoline for interrupt routines in banked ram.
682 ; Switch stack pointer to "system" stack in top ram
683 ; Save cbar
684
685 isv_sw: ;
686 ex (sp),hl ;save hl, 'return adr' in hl
687 push de ;
688 push af ;
689 ex de,hl ;'return address' in de
690 ld hl,0 ;
691 add hl,sp ;
692 ld a,h ;
693 cp 0f8h ;
694 jr nc,isw_1 ;stack allready in top ram
695 ld sp,$stack ;
696 isw_1:
697 push hl ;save user stack pointer
698 in0 h,(cbar) ;
699 push hl ;
700 ld a,SYS$CBAR ;
701 out0 (cbar),a ;
702 ex de,hl ;
703 ld e,(hl) ;
704 inc hl ;
705 ld d,(hl) ;
706 ex de,hl ;
707 push bc ;
708 call jphl ;
709
710 pop bc ;
711 pop hl ;
712 out0 (cbar),h ;
713 pop hl ;
714 ld sp,hl ;
715 pop af ;
716 pop de ;
717 pop hl ;
718 ei ;
719 ret ;
720 jphl:
721 jp (hl) ;
722
723 ; ---------------------------------------------------------
724
725 if CPU_Z180
726
727 iprt0:
728 push af
729 push hl
730 in0 a,(tcr)
731 in0 a,(tmdr0l)
732 in0 a,(tmdr0h)
733 ld a,(tim_ms)
734 inc a
735 cp 100
736 jr nz,iprt_1
737 xor a
738 ld hl,(tim_s)
739 inc hl
740 ld (tim_s),hl
741 iprt_1:
742 ld (tim_ms),a
743 pop hl
744 pop af
745 ei
746 ret
747
748 endif
749
750 ; ---------------------------------------------------------
751
752 sp.int0:
753 ld a,0d0h
754 jr sp.i.1
755 sp.int.len equ $-sp.int0
756 ld a,0d1h
757 jr sp.i.1
758 ld a,0d2h
759 jr sp.i.1
760 ld a,0d3h
761 jr sp.i.1
762 ld a,0d4h
763 jr sp.i.1
764 ld a,0d5h
765 jr sp.i.1
766 ld a,0d6h
767 jr sp.i.1
768 ld a,0d7h
769 jr sp.i.1
770 ld a,0d8h
771 sp.i.1:
772 ; out (80h),a
773 halt
774
775 ; ---------------------------------------------------------
776
777 if CPU_Z80
778
779 ; Get IFF2
780 ; This routine may not be loaded in page zero
781 ;
782 ; return Carry clear, if INTs are enabled.
783 ;
784 global getiff
785 getiff:
786 xor a ;clear accu and carry
787 push af ;stack bottom := 00xxh
788 pop af
789 ld a,i ;P flag := IFF2
790 ret pe ;exit carry clear, if enabled
791 dec sp
792 dec sp ;has stack bottom been overwritten?
793 pop af
794 and a ;if not 00xxh, INTs were
795 ret nz ;actually enabled
796 scf ;Otherwise, they really are disabled
797 ret
798
799 ;----------------------------------------------------------------------
800
801 global selbnk
802
803 ; a: bank (0..2)
804
805 selbnk:
806 push bc
807 ld c,a
808 call getiff
809 push af
810
811 ld a,c
812 di
813 ld (@cbnk),a
814 ld a,5
815 out (SIOAC),a
816 ld a,(mm_sio0)
817 rla
818 srl c
819 rra
820 out (SIOAC),a
821 ld (mm_sio0),a
822
823 ld a,5
824 out (SIOBC),a
825 ld a,(mm_sio1)
826 rla
827 srl c
828 rra
829 out (SIOBC),a
830 ld (mm_sio1),a
831 pop af
832 pop bc
833 ret c ;INTs were disabled
834 ei
835 ret
836
837 ;----------------------------------------------------------------------
838
839 ; c: bank (0..2)
840
841 if 0
842
843 selbnk:
844 ld a,(@cbnk)
845 xor c
846 and 3
847 ret z ;no change
848
849 call getiff
850 push af
851 ld a,c
852 di
853 ld (@cbnk),a
854 ld a,5
855 out (SIOAC),a
856 ld a,(mm_sio0)
857 rla
858 srl c
859 rra
860 out (SIOAC),a
861 ld (mm_sio0),a
862
863 ld a,5
864 out (SIOBC),a
865 ld a,(mm_sio1)
866 rla
867 srl c
868 rra
869 out (SIOBC),a
870 ld (mm_sio1),a
871 pop af
872 ret nc ;INTs were disabled
873 ei
874 ret
875
876 endif
877
878 ;----------------------------------------------------------------------
879
880 if 0
881 ex af,af'
882 push af
883 ex af,af'
884
885 rra
886 jr nc,stbk1
887 ex af,af'
888 ld a,5
889 out (SIOAC),a
890 ld a,(mm_sio0)
891 rla
892 srl c
893 rra
894 out (SIOAC),a
895 ld (mm_sio1),a
896 ex af,af'
897
898 stbk1:
899 rra
900 jr nc,stbk2
901 ex af,af'
902 ld a,5
903 out (SIOBC),a
904 ld a,(mm_sio1)
905 rla
906 srl c
907 rra
908 out (SIOBC),a
909 ld (mm_sio1),a
910 ex af,af'
911
912 stbk2:
913 endif
914
915 global @cbnk
916 global mm_sio0, mm_sio1
917
918 @cbnk: db 0 ; current bank (0..2)
919 mm_sio0:
920 ds 1
921 mm_sio1:
922 ds 1
923
924
925 endif
926
927 ;----------------------------------------------------------------------
928
929 curph defl $
930 .dephase
931 sysrame:
932 .phase curph
933 tim_ms: db 0
934 tim_s: dw 0
935 .dephase
936
937 ;-----------------------------------------------------
938
939
940 cseg
941
942 ;.phase 0ffc0h
943 ;ivtab equ 0ffc0h ; 0ffc0h ;int vector table
944 ;.dephase
945
946 ;.phase 0fffah
947 mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack
948 ;ds 4
949 ;.dephase
950
951
952 end
Z180 Stamp Monitor