avr/z80-if.c

   1 /*
   2  * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 /**
   8  *
   9  * Pin assignments
  10  *
  11  * | Z180-Sig   |   AVR-Port    | Dir   |
  12  * +------------+---------------+-------+
  13  * |    A0      | PA    0       |  O    |
  14  * |    A1      | PA    1       |  O    |
  15  * |    A2      | PA    2       |  O    |
  16  * |    A3      | PA    3       |  O    |
  17  * |    A4      | PA    4       |  O    |
  18  * |    A5      | PA    5       |  O    |
  19  * |    A6      | PA    6       |  O    |
  20  * |    A7      | PA    7       |  O    |
  21  * |    A8      | PC    0       |  O    |
  22  * |    A9      | PC    1       |  O    |
  23  * |    A10     | PC    2       |  O    |
  24  * |    A11     | PC    3       |  O    |
  25  * |    A12     | PC    4       |  O    |
  26  * |    A13     | PC    5       |  O    |
  27  * |    A14     | PC    6       |  O    |
  28  * |    A15     | PC    7       |  O    |
  29  * |    A16     | PE    2       |  O    |
  30  * |    A17     | PE    3       |  O    |
  31  * |    A18     | PE    4       |  O    |
  32  * |    D0      | PF    0       |  I/O  |
  33  * |    D1      | PF    1       |  I/O  |
  34  * |    D2      | PF    2       |  I/O  |
  35  * |    D3      | PF    3       |  I/O  |
  36  * |    D4      | PF    4       |  I/O  |
  37  * |    D5      | PF    5       |  I/O  |
  38  * |    D6      | PF    6       |  I/O  |
  39  * |    D7      | PF    7       |  I/O  |
  40  * |    RD      | PD    3       |  O    |
  41  * |    WR      | PD    2       |  O    |
  42  * |    MREQ    | PD    4       |  O    |
  43  * |    RST     | PD    5       |  O    |
  44  * |    BUSREQ  | PD    7       |  O    |
  45  * |    BUSACK  | PD    6       |  I    |
  46  * |
  47  * | Optional
  48  * +------------------------------------+
  49  * |    STEP    | PG    0       |  O    |
  50  * |    RUN     | PG    1       |  O    |
  51  * |    WAIT    | PG    2       |  I    |
  52
  53  */
  54
  55
  56 #include "z80-if.h"
  57 #include <util/atomic.h>
  58 #include "debug.h"
  59 #include "config.h"
  60 #include "env.h"
  61
  62
  63 //#define P_ZCLK                PORTB
  64 //#define ZCLK          5
  65 //#define DDR_ZCLK      DDRB
  66 #define P_MREQ          PORTD
  67 #define MREQ            4
  68 #define DDR_MREQ        DDRD
  69 #define P_RD            PORTD
  70 #define RD              3
  71 #define P_WR            PORTD
  72 #define WR              2
  73 #define P_BUSREQ        PORTD
  74 #define BUSREQ          7
  75 #define DDR_BUSREQ      DDRD
  76 #define P_BUSACK        PORTD
  77 #define PIN_BUSACK      PIND
  78 #define BUSACK          6
  79 #define DDR_BUSACK      DDRD
  80 #define P_RST           PORTD
  81 #define PIN_RST         PIND
  82 #define DDR_RST         DDRD
  83 #define RST             5
  84
  85
  86 #define P_DB            PORTF
  87 #define PIN_DB          PINF
  88 #define DDR_DB          DDRF
  89
  90 #define P_ADL           PORTA
  91 #define P_ADH           PORTC
  92 #define P_ADB           PORTE
  93 #define PIN_ADB         PINE
  94 #define DDR_ADL         DDRA
  95 #define DDR_ADH         DDRC
  96 #define DDR_ADB         DDRE
  97
  98 #define ADB_WIDTH       3
  99 #define ADB_SHIFT       2
 100 //#define ADB_PORT      PORTE
 101
 102
 103 //#define Z80_O_ZCLK    SBIT(P_ZCLK, 5)
 104 #define Z80_O_MREQ      SBIT(P_MREQ, 4)
 105 #define Z80_O_RD        SBIT(P_RD, 3)
 106 #define Z80_O_WR        SBIT(P_WR, 2)
 107 #define Z80_O_BUSREQ    SBIT(P_BUSREQ, 7)
 108 //#define Z80_O_NMI     SBIT(P_NMI, )
 109 #define Z80_O_RST       SBIT(P_RST, 5)
 110 #define Z80_I_RST       SBIT(PIN_RST, 5)
 111 #define Z80_I_BUSACK    SBIT(PIN_BUSACK, 6)
 112 //#define Z80_I_HALT    SBIT(P_HALT, )
 113
 114 /* Optional */
 115 #define P_RUN           PORTG
 116 #define RUN                     1
 117 #define DDR_RUN         DDRG
 118 #define P_STEP          PORTG
 119 #define STEP            0
 120 #define DDR_STEP        DDRG
 121 #define P_WAIT          PORTG
 122 #define WAIT            2
 123 #define DDR_WAIT        DDRG
 124 /* All three signals are on the same Port (PortG) */
 125 #define PORT_SS         PORTG
 126 #define DDR_SS          DDRG
 127 #define PIN_SS          PING
 128 #define Z80_O_RUN       SBIT(PORT_SS, RUN)
 129 #define Z80_O_STEP      SBIT(PORT_SS, STEP)
 130 #define Z80_I_WAIT      SBIT(PORT_SS, WAIT)
 131
 132
 133 #define BUS_TO 20
 134
 135
 136 #define MASK(n) ((1<<(n))-1)
 137 #define SMASK(w,s) (MASK(w) << (s))
 138
 139 void z80_bus_request_or_exit(void)
 140 {
 141         if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
 142                 cmd_error(CMD_RET_FAILURE, EBUSTO, NULL);
 143 }
 144
 145 static zstate_t zstate;
 146 static volatile uint8_t timer;          /* used for bus timeout */
 147 static bool reset_polarity;
 148
 149 /*---------------------------------------------------------*/
 150 /* 10Hz timer interrupt generated by OC5A                  */
 151 /*---------------------------------------------------------*/
 152
 153 ISR(TIMER5_COMPA_vect)
 154 {
 155
 156         uint8_t i = timer;
 157
 158         if (i)
 159                 timer = i - 1;
 160 }
 161
 162 /*--------------------------------------------------------------------------*/
 163
 164
 165 static void z80_addrbus_set_in(void)
 166 {
 167         /* /MREQ, /RD, /WR: Input, no pullup */
 168         DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
 169         Z80_O_MREQ = 0;
 170         Z80_O_RD = 0;
 171         Z80_O_WR = 0;
 172
 173         P_ADL = 0;
 174         DDR_ADL = 0;
 175         P_ADH = 0;
 176         DDR_ADH = 0;
 177         PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT);
 178         DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
 179 }
 180
 181
 182 static void z80_addrbus_set_out(void)
 183 {
 184         /* /MREQ, /RD, /WR: Output and high */
 185         Z80_O_MREQ = 1;
 186         Z80_O_RD = 1;
 187         Z80_O_WR = 1;
 188         DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR);
 189
 190         DDR_ADL = 0xff;
 191         DDR_ADH = 0xff;
 192         DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT);
 193 }
 194
 195
 196 static void z80_dbus_set_in(void)
 197 {
 198         DDR_DB = 0;
 199         P_DB = 0;
 200 }
 201
 202
 203 static void z80_dbus_set_out(void)
 204 {
 205         DDR_DB = 0xff;
 206 }
 207
 208 static void z80_reset_active(void)
 209 {
 210         if (reset_polarity)
 211                 Z80_O_RST = 1;
 212         else
 213                 Z80_O_RST = 0;
 214 }
 215
 216 static void z80_reset_inactive(void)
 217 {
 218         if (reset_polarity)
 219                 Z80_O_RST = 0;
 220         else
 221                 Z80_O_RST = 1;
 222 }
 223
 224 static void z80_reset_pulse(void)
 225 {
 226         z80_reset_active();
 227         _delay_us(10);
 228         z80_reset_inactive();
 229 }
 230
 231
 232 void z80_setup_bus(void)
 233 {
 234         ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 235
 236                 /* /ZRESET: Input, no pullup */
 237                 DDR_RST &= ~_BV(RST);
 238                 Z80_O_RST = 0;
 239
 240                 /* /BUSREQ: Output and high */
 241                 Z80_O_BUSREQ = 1;
 242                 DDR_BUSREQ |= _BV(BUSREQ);
 243
 244                 /* /BUSACK: Input, no pullup */
 245                 DDR_BUSACK &= ~_BV(BUSACK);
 246                 P_BUSACK &= ~_BV(BUSACK);
 247
 248                 z80_addrbus_set_in();
 249                 z80_dbus_set_in();
 250
 251                 if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
 252                         /* /RUN & /STEP: output, /WAIT: input */
 253
 254                         PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP);
 255                         DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
 256                 }
 257
 258                 reset_polarity = Z80_I_RST;
 259                 z80_reset_active();
 260                 DDR_RST |= _BV(RST);
 261
 262                 zstate = RESET;
 263         }
 264
 265         /* Timer 5 */
 266         PRR1 &= ~_BV(PRTIM5);
 267         OCR5A = F_CPU / 1024 / 10 - 1;            /* Timer: 10Hz interval (OC4A) */
 268         TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
 269         TIMSK5 = _BV(OCIE5A);                             /* Enable oca interrupt */
 270
 271 }
 272
 273
 274 zstate_t z80_bus_state(void)
 275 {
 276         return zstate;
 277 }
 278
 279
 280 static void z80_busreq_hpulse(void)
 281 {
 282         z80_dbus_set_in();
 283         z80_addrbus_set_in();
 284
 285 #if 0
 286         ATOMIC_BLOCK(ATOMIC_FORCEON) {
 287                 Z80_O_BUSREQ = 1;
 288                 Z80_O_BUSREQ = 1;       /* 2 AVR clock cycles */
 289                 Z80_O_BUSREQ = 0;       /* 2 AVR clock cycles */
 290         }
 291 #endif
 292
 293 #if 1
 294         ATOMIC_BLOCK(ATOMIC_FORCEON) {
 295                 Z80_O_BUSREQ = 1;
 296
 297                 do {
 298                         if (Z80_I_BUSACK == 1)  {
 299                                 Z80_O_BUSREQ = 0;
 300                                 break;
 301                         }
 302                 } while (1);
 303         }
 304 #endif
 305
 306         if (zstate & ZST_ACQUIRED) {
 307                 timer = BUS_TO;
 308                 while (Z80_I_BUSACK == 1 && timer)
 309                         ;
 310                 if (Z80_I_BUSACK == 0)
 311                         z80_addrbus_set_out();
 312         }
 313 }
 314
 315
 316 /*
 317
 318  +              |               |               |               |               |
 319     +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
 320        +        |               |               |               |               |
 321           +     |       0       |       1       |       2       |       3       |
 322 Event        +  |               |               |               |               |
 323 ----------------+---------------+---------------+---------------+---------------+
 324                 |               |               |               |               |
 325 Reset           |       0       |       0       |       0       |       0       |
 326                 |               |               |               |               |
 327                 |               |               |               |               |
 328 Request         |       1       |               |       3       |               |
 329                 |               |               |               |               |
 330                 |               |               |               |               |
 331 Release         |               |       0       |               |       2       |
 332                 |               |               |               |               |
 333                 |               |               |               |               |
 334 Run             |       2       |       3       |               |               |
 335                 |               |               |               |               |
 336                 |               |               |               |               |
 337 Restart         |               |               |       2       |       3       |
 338                 |               |               |               |               |
 339                 |               |               |               |               |
 340 M_Cycle         |               |               |               |       3       |
 341                 |               |               |               |               |
 342                 |               |               |               |               |
 343 */
 344
 345 zstate_t z80_bus_cmd(bus_cmd_t cmd)
 346 {
 347         switch (cmd) {
 348
 349         case Reset:
 350                 z80_dbus_set_in();
 351                 z80_addrbus_set_in();
 352                 z80_reset_active();
 353                 Z80_O_BUSREQ = 1;
 354                 timer = BUS_TO;
 355                 while (Z80_I_BUSACK == 0 && timer)
 356                         ;
 357                 zstate = RESET;
 358                 break;
 359
 360         case Request:
 361                 switch (zstate) {
 362                 case RESET:
 363                         Z80_O_BUSREQ = 0;
 364                         z80_reset_inactive();
 365                         timer = BUS_TO;
 366                         while (Z80_I_BUSACK == 1 && timer)
 367                                 ;
 368                         if (Z80_I_BUSACK == 0) {
 369                                 z80_addrbus_set_out();
 370                                 zstate = RESET_AQRD;
 371                         } else {
 372                                 z80_reset_active();
 373                                 Z80_O_BUSREQ = 1;
 374                         }
 375                         break;
 376
 377                 case RUNNING:
 378                         Z80_O_BUSREQ = 0;
 379                         timer = BUS_TO;
 380                         while (Z80_I_BUSACK == 1 && timer)
 381                                 ;
 382                         if (Z80_I_BUSACK == 0) {
 383                                 z80_addrbus_set_out();
 384                                 zstate = RUNNING_AQRD;
 385                         } else {
 386                                 Z80_O_BUSREQ = 1;
 387                         }
 388                         break;
 389
 390                 default:
 391                         break;
 392                 }
 393                 break;
 394
 395         case Release:
 396                 switch (zstate) {
 397                 case RESET_AQRD:
 398                         z80_dbus_set_in();
 399                         z80_addrbus_set_in();
 400                         z80_reset_active();
 401                         Z80_O_BUSREQ = 1;
 402                         timer = BUS_TO;
 403                         while (Z80_I_BUSACK == 0 && timer)
 404                                 ;
 405                         zstate = RESET;
 406                         break;
 407                 case RUNNING_AQRD:
 408                         z80_dbus_set_in();
 409                         z80_addrbus_set_in();
 410                         Z80_O_BUSREQ = 1;
 411                         timer = BUS_TO;
 412                         while (Z80_I_BUSACK == 0 && timer)
 413                                 ;
 414                         zstate = RUNNING;
 415                         break;
 416                 default:
 417                         break;
 418                 }
 419                 break;
 420
 421         case Run:
 422                 switch (zstate) {
 423                 case RESET:
 424                         _delay_ms(20);          /* TODO: */
 425                         z80_reset_inactive();
 426                         zstate = RUNNING;
 427                         break;
 428
 429                 case RESET_AQRD:
 430                         z80_dbus_set_in();
 431                         z80_addrbus_set_in();
 432                         z80_reset_pulse();
 433                         z80_addrbus_set_out();
 434                         zstate = RUNNING_AQRD;
 435                         break;
 436                 default:
 437                         break;
 438                 }
 439                 break;
 440
 441         case Restart:
 442                 switch (zstate) {
 443                 case RUNNING:
 444                 case RUNNING_AQRD:
 445                         z80_reset_pulse();
 446                         break;
 447                 default:
 448                         break;
 449                 }
 450                 break;
 451
 452         case M_Cycle:
 453                 switch (zstate) {
 454                 case RUNNING_AQRD:
 455                         z80_busreq_hpulse();    /* TODO: */
 456                         break;
 457                 default:
 458                         break;
 459                 }
 460         }
 461         return zstate;
 462 }
 463
 464
 465 /*--------------------------------------------------------------------------*/
 466
 467 static
 468 //inline __attribute__ ((always_inline))
 469 void z80_setaddress(uint32_t addr)
 470 {
 471         P_ADL = addr;
 472         P_ADH = (addr & 0xff00) >> 8;
 473         PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
 474 }
 475
 476 int32_t z80_memsize_detect(void)
 477 {
 478         const uint8_t PATTERN_1 = 0x55;
 479         const uint8_t PATTERN_2 = ~PATTERN_1;
 480         uint32_t addr;
 481
 482         if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
 483                 return  -EBUSTO;
 484
 485         uint8_t ram_0 = z80_read(0);
 486         uint8_t ram_1 = z80_read(1);
 487
 488         z80_write(0, ram_0 ^ 0xff);
 489         z80_write(1, ram_1);
 490         if ((z80_read(0) ^ ram_0) != 0xff) {
 491                 addr = 0;
 492         } else {
 493                 z80_write(0, PATTERN_1);
 494                 for (addr=1; addr < CONFIG_SYS_RAMSIZE_MAX; addr <<= 1) {
 495                         uint8_t ram_i = z80_read(addr);
 496                         z80_write(addr, PATTERN_2);
 497                         if (z80_read(0) != PATTERN_1 || z80_read(addr) != PATTERN_2)
 498                                 break;
 499                         z80_write(addr, ram_i);
 500                 }
 501         }
 502
 503         z80_write(0, ram_0);
 504         z80_bus_cmd(Release);
 505
 506         return addr;
 507 }
 508
 509 /*--------------------------------------------------------------------------*/
 510
 511 void z80_write(uint32_t addr, uint8_t data)
 512 {
 513         z80_setaddress(addr);
 514         Z80_O_MREQ = 0;
 515         z80_dbus_set_out();
 516         P_DB = data;
 517         P_DB = data;
 518         Z80_O_WR = 0;
 519         Z80_O_WR = 0;
 520         Z80_O_WR = 1;
 521         Z80_O_MREQ = 1;
 522 }
 523
 524 uint8_t z80_read(uint32_t addr)
 525 {
 526         uint8_t data;
 527
 528         z80_setaddress(addr);
 529         Z80_O_MREQ = 0;
 530         z80_dbus_set_in();
 531         Z80_O_RD = 0;
 532         Z80_O_RD = 0;
 533         Z80_O_RD = 0;
 534         data = PIN_DB;
 535         Z80_O_RD = 1;
 536         Z80_O_MREQ = 1;
 537
 538         return data;
 539 }
 540
 541
 542 void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
 543 {
 544         z80_dbus_set_out();
 545         Z80_O_MREQ = 0;
 546         P_DB = data;
 547         while(length--) {
 548                 z80_setaddress(addr++);
 549                 Z80_O_WR = 0;
 550                 Z80_O_WR = 0;
 551                 Z80_O_WR = 1;
 552         }
 553         Z80_O_MREQ = 1;
 554 }
 555
 556 void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
 557 {
 558         uint8_t data;
 559
 560         z80_dbus_set_out();
 561         Z80_O_MREQ = 0;
 562         while(length--) {
 563                 z80_setaddress(dest++);
 564                 data = *src++;
 565                 P_DB = data;
 566                 P_DB = data;
 567                 Z80_O_WR = 0;
 568                 Z80_O_WR = 0;
 569                 Z80_O_WR = 1;
 570         }
 571         Z80_O_MREQ = 1;
 572 }
 573
 574 void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
 575 {
 576         uint8_t data;
 577
 578         z80_dbus_set_out();
 579         Z80_O_MREQ = 0;
 580         while(length--) {
 581                 z80_setaddress(dest++);
 582                 data = *src++;
 583                 P_DB = data;
 584                 P_DB = data;
 585                 Z80_O_WR = 0;
 586                 Z80_O_WR = 0;
 587                 Z80_O_WR = 1;
 588         }
 589         Z80_O_MREQ = 1;
 590 }
 591
 592 void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
 593 {
 594         uint8_t data;
 595
 596         Z80_O_MREQ = 0;
 597         z80_dbus_set_in();
 598         while(length--) {
 599                 z80_setaddress(src++);
 600                 Z80_O_RD = 0;
 601                 Z80_O_RD = 0;
 602                 Z80_O_RD = 0;
 603                 data = PIN_DB;
 604                 Z80_O_RD = 1;
 605                 *dest++ = data;
 606         }
 607         Z80_O_MREQ = 1;
 608 }
 609
 610 /*--------------------------------------------------------------------------*/
 611
 612 /*
 613   0179'                         rx.bs_mask:     ds      1               ; (buf_len - 1)
 614   017A'                         rx.in_idx:      ds      1               ;
 615   017B'                         rx.out_idx:     ds      1               ;
 616   017C'                         rx.buf:         ds      rx.buf_len      ;
 617   018B'                         rx.buf_end      equ     $-1             ; last byte (start+len-1)
 618
 619   018C'                         tx.bs_mask:     ds      1               ; (buf_len - 1)
 620   018D'                         tx.in_idx:      ds      1               ;
 621   018E'                         tx.out_idx:     ds      1               ;
 622   018F'                         tx.buf:         ds      tx.buf_len      ;
 623   019E'                         tx.buf_end      equ     $-1             ; last byte
 624 */
 625
 626
 627 typedef struct __attribute__((packed)) {
 628         uint8_t mask;
 629         uint8_t in_idx;
 630         uint8_t out_idx;
 631         uint8_t buf[];
 632 } zfifo_t;
 633
 634
 635
 636 #define FIFO_BUFSIZE_MASK       -3
 637 #define FIFO_INDEX_IN           -2
 638 #define FIFO_INDEX_OUT          -1
 639
 640
 641 static struct {
 642         uint32_t base;
 643         uint8_t idx_out,
 644                 idx_in,
 645                 mask;
 646         } fifo_dsc[NUM_FIFOS];
 647
 648
 649 void z80_memfifo_init(const fifo_t f, uint32_t addr)
 650 {
 651         fifo_dsc[f].base = addr;
 652
 653
 654         if (addr != 0) {
 655                 z80_bus_cmd(Request);
 656                 fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
 657                 fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
 658                 fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
 659                 z80_bus_cmd(Release);
 660
 661                 if (fifo_dsc[f].idx_in != 0 || fifo_dsc[f].idx_out != 0) {
 662                         DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
 663                                         f, addr, fifo_dsc[f].idx_in, fifo_dsc[f].idx_out, fifo_dsc[f].mask);
 664                 }
 665         }
 666 }
 667
 668
 669 int z80_memfifo_is_empty(const fifo_t f)
 670 {
 671         int rc = 1;
 672
 673         if (fifo_dsc[f].base != 0) {
 674
 675                 uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
 676                 uint8_t idx;
 677
 678                 z80_bus_cmd(Request);
 679                 idx = z80_read(adr);
 680                 z80_bus_cmd(Release);
 681                 rc = idx == fifo_dsc[f].idx_out;
 682         }
 683
 684         return rc;
 685 }
 686
 687 int z80_memfifo_is_full(const fifo_t f)
 688 {
 689         int rc = 0;
 690
 691         if (fifo_dsc[f].base != 0) {
 692                 z80_bus_cmd(Request);
 693                 rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
 694                         == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
 695                 z80_bus_cmd(Release);
 696         }
 697         return rc;
 698 }
 699
 700
 701 uint8_t z80_memfifo_getc_wait(const fifo_t f)
 702 {
 703         uint8_t rc, idx;
 704
 705         while (z80_memfifo_is_empty(f))
 706                 ;
 707
 708         z80_bus_cmd(Request);
 709         idx = fifo_dsc[f].idx_out;
 710         rc = z80_read(fifo_dsc[f].base+idx);
 711         fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
 712         z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
 713         z80_bus_cmd(Release);
 714
 715         return rc;
 716 }
 717
 718 int z80_memfifo_getc(const fifo_t f)
 719 {
 720         int rc = -1;
 721
 722         if (fifo_dsc[f].base != 0) {
 723                 uint8_t idx = fifo_dsc[f].idx_out;
 724                 z80_bus_cmd(Request);
 725                 if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
 726                         rc = z80_read(fifo_dsc[f].base+idx);
 727                         fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
 728                         z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
 729                 }
 730                 z80_bus_cmd(Release);
 731         }
 732
 733         return rc;
 734 }
 735
 736
 737 void z80_memfifo_putc(fifo_t f, uint8_t val)
 738 {
 739         int idx;
 740
 741         while (z80_memfifo_is_full(f))
 742                 ;
 743
 744         z80_bus_cmd(Request);
 745         idx = fifo_dsc[f].idx_in;
 746         z80_write(fifo_dsc[f].base+idx, val);
 747         fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
 748         z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
 749         z80_bus_cmd(Release);
 750 }
 751
 752 /*--------------------------------------------------------------------------*/
 753
 754 void z80_load_mem(int_fast8_t verbosity,
 755                                 const FLASH unsigned char data[],
 756                                 const FLASH unsigned long *sections,
 757                                 const FLASH unsigned long address[],
 758                                 const FLASH unsigned long length_of_sections[])
 759 {
 760         uint32_t sec_base = 0;
 761
 762         if (verbosity > 1)
 763                 printf_P(PSTR("Loading Z180 memory... \n"));
 764
 765         for (unsigned sec = 0; sec < *sections; sec++) {
 766                 if (verbosity > 0) {
 767                         printf_P(PSTR("   From: 0x%.5lX to: 0x%.5lX    (%5li bytes)\n"),
 768                                         address[sec],
 769                                         address[sec]+length_of_sections[sec] - 1,
 770                                         length_of_sections[sec]);
 771                 }
 772
 773                 z80_write_block_P((const FLASH unsigned char *) &data[sec_base],  /* src */
 774                                 address[sec],                  /* dest */
 775                                 length_of_sections[sec]);      /* len */
 776                 sec_base += length_of_sections[sec];
 777         }
 778 }