z180/init.180

   1         page    255
   2         .z80
   3
   4         extrn ddtz,bpent
   5         extrn $stack
   6         extrn charini,?const,?conin
   7         extrn ?cono,?conos
   8         extrn romend
   9
  10
  11         global  iobyte
  12         global  isv_sw
  13
  14         include config.inc
  15     if CPU_Z180
  16         include z180reg.inc
  17         include z180.lib
  18     endif
  19
  20
  21
  22
  23 ;----------------------------------------------------------------------
  24
  25         cseg
  26 romstart equ    $
  27
  28         org     romstart+0
  29         jp start
  30
  31 iobyte: db      2
  32
  33 ; restart vectors
  34
  35 rsti    defl    1
  36         rept    7
  37         org     8*rsti + romstart
  38         jp bpent
  39 rsti    defl rsti+1
  40         endm
  41
  42 ;----------------------------------------------------------------------
  43 ; Config space
  44 ;
  45
  46         org     romstart+40h
  47
  48         dw      0
  49         db      0
  50
  51
  52     if ROMSYS
  53 $crom:  defb c$rom              ;
  54     else
  55         db      0               ;
  56     endif
  57
  58 INIWAITS defl   CWAITIO
  59     if  ROMSYS
  60 INIWAITS defl   INIWAITS+CWAITROM
  61     endif
  62
  63 ;----------------------------------------------------------------------
  64
  65         org     romstart+50h
  66 start:
  67         jp      cstart
  68         jp      wstart
  69         jp      ?const
  70         jp      ?conin
  71         jp      ?cono
  72         jp      ?conos
  73         jp      charini
  74
  75 ;----------------------------------------------------------------------
  76
  77 hwini0:
  78     if CPU_Z180
  79         db      3               ;count
  80         db      rcr,CREFSH      ;configure DRAM refresh
  81         db      dcntl,INIWAITS  ;wait states
  82         db      cbar,SYS$CBAR
  83     endif
  84         db     0
  85
  86     if CPU_Z180
  87 dmclrt:                         ;clear ram per dma
  88         db      dmct_e-dmclrt-2 ;
  89         db      sar0l           ;first port
  90         dw      nullbyte        ;src (fixed)
  91 nullbyte:
  92         db      000h            ;src
  93         dw      romend          ;dst (inc), start after "rom" code
  94         db      00h             ;dst
  95         dw      0-romend        ;count (64k)
  96 dmct_e:
  97         db      0
  98     endif
  99
 100
 101 cstart:
 102     if CPU_Z180
 103
 104         push af
 105         in0 a,(itc)             ;Illegal opcode trap?
 106         jp m,??st01
 107         ld a,i                  ;I register == 0 ?
 108         jr z,hw_reset           ;    yes, harware reset
 109
 110 ??st01:
 111         ; TODO: SYS$CBR
 112         ld      a,(syscbr)
 113         out0    (cbr),a
 114         pop af                  ;restore registers
 115         jp bpent                ;
 116
 117 hw_reset:
 118         di                      ;0058
 119         ld      a,CREFSH
 120         out0    (rcr),a         ;       configure DRAM refresh
 121         ld      a,CWAITIO
 122         out0    (dcntl),a       ;       wait states
 123
 124         ld      a,M_NCD         ;No Clock Divide
 125         out0    (ccr),a
 126 ;       ld      a,M_X2CM        ;X2 Clock Multiplier
 127 ;       out0    (cmr),a
 128     else
 129         di
 130         xor     a
 131         ld      (@cbnk),a
 132     endif
 133
 134 ; check warm start mark
 135
 136         ld ix,mark_55AA         ; top of common area
 137         ld a,0aah               ;
 138         cp (ix+000h)            ;
 139         jr nz,kstart            ;
 140         cp (ix+002h)            ;
 141         jr nz,kstart            ;
 142         cpl                     ;
 143         cp (ix+001h)            ;
 144         jr nz,kstart            ;
 145         cp (ix+003h)            ;
 146         jr nz,kstart            ;
 147         ld sp,$stack            ; mark found, check
 148         jp z,wstart             ; check ok,
 149
 150 ; ram not ok, initialize    --  kstart --
 151
 152 kstart:
 153     if CPU_Z180
 154         ld      a,SYS$CBAR
 155         out0    (cbar),a
 156         ld      a,SYS$CBR
 157         out0    (cbr),a
 158     endif
 159
 160         ld      sp,$stack       ;01e1
 161
 162 ; Clear RAM using DMA0
 163
 164     if CPU_Z180
 165      if 0
 166
 167         ld      hl,dmclrt       ;load DMA registers
 168         call    ioiniml
 169         ld      a,0cbh          ;01ef   dst +1, src fixed, burst
 170         out0    (dmode),a       ;01f1
 171
 172         ld      b,512/64
 173         ld      a,062h          ;01f4   enable dma0,
 174 ??cl_1:
 175         out0    (dstat),a       ;01f9   clear (up to) 64k
 176         djnz    ??cl_1          ;       end of RAM?
 177
 178      endif
 179     endif
 180
 181         ld      hl,055AAh       ;set warm start mark
 182         ld      (mark_55AA),hl
 183         ld      (mark_55AA+2),hl
 184
 185 ;       --  wstart  --
 186
 187 wstart:
 188         call    sysram_init     ;027f
 189         call    ivtab_init
 190     if CPU_Z180
 191         call    prt0_init
 192     endif
 193
 194         call    charini
 195         call    bufferinit
 196
 197     if CPU_Z80
 198         ld      a,0
 199         call    selbnk
 200     endif
 201
 202         im 2                    ;?030e
 203         ei                      ;0282
 204
 205         call ?const             ;0284
 206         call ?const             ;0287
 207         or a                    ;028a
 208         call nz,?conin          ;028d
 209
 210     if CPU_Z180
 211         ld e,0                  ;Sys$Bank
 212     else
 213 ; TODO:
 214     endif
 215         jp ddtz                 ;0290
 216
 217
 218     if CPU_Z180
 219 ; TODO: SYS$CBR
 220 syscbr: db      1
 221     endif
 222
 223 ;
 224 ;----------------------------------------------------------------------
 225 ;
 226
 227 ;TODO: Make a ringbuffer module.
 228
 229         global  buf.init
 230
 231 buf.init:
 232         ld      (ix+o.in_idx),0
 233         ld      (ix+o.out_idx),0
 234         ld      (ix+o.mask),a
 235         ret
 236
 237 ;----------------------------------------------------------------------
 238
 239         extrn   msginit,msg.sout
 240         extrn   mtx.fifo,mrx.fifo
 241         extrn   co.fifo,ci.fifo
 242
 243
 244 bufferinit:
 245     if CPU_Z180
 246         call    msginit
 247
 248         ld      hl,buffers
 249         ld      b,buftablen
 250 bfi_1:
 251         ld      a,(hl)
 252         inc     hl
 253         ld      (bufdat+0),a
 254         ld      e,(hl)
 255         inc     hl
 256         ld      d,(hl)
 257         inc     hl
 258         ex      de,hl
 259
 260         or      a
 261         jr      nz,bfi_2
 262         call    hwl2phy
 263         ld      (40h+0),hl
 264         ld      (40h+2),a
 265         out     (AVRINT5),a
 266         jr      bfi_3
 267 bfi_2:
 268         call    hwl2phy
 269         ld      (bufdat+1),hl
 270         ld      (bufdat+3),a
 271         ld      hl,inimsg
 272         call    msg.sout
 273 bfi_3:
 274         ex      de,hl
 275         djnz    bfi_1
 276         ret
 277
 278     else ;CPU_Z180
 279
 280         call    msginit
 281
 282         ld      hl,buffers
 283         ld      b,buftablen
 284 bfi_1:
 285         ld      a,(hl)
 286         inc     hl
 287         ld      (bufdat+0),a
 288         ld      e,(hl)
 289         inc     hl
 290         ld      d,(hl)
 291         inc     hl
 292         ex      de,hl
 293
 294         or      a
 295         jr      nz,bfi_2
 296
 297         ld      a,(@cbnk)
 298         call    bnk2phy
 299
 300         ld      (40h+0),hl
 301         ld      (40h+2),a
 302         out     (AVRINT5),a
 303         jr      bfi_3
 304 bfi_2:
 305
 306         ld      a,(@cbnk)
 307         call    bnk2phy
 308
 309         ld      (bufdat+1),hl
 310         ld      (bufdat+3),a
 311         ld      hl,inimsg
 312         call    msg.sout
 313 bfi_3:
 314         ex      de,hl
 315         djnz    bfi_1
 316         ret
 317     endif
 318
 319 buffers:
 320         db      0
 321         dw      mtx.fifo
 322         db      1
 323         dw      mrx.fifo
 324         db      2
 325         dw      co.fifo
 326         db      3
 327         dw      ci.fifo
 328 buftablen equ   ($ - buffers)/3
 329
 330 inimsg:
 331         db      inimsg_e - $ -1
 332         db      0AEh
 333         db      inimsg_e - $ -1
 334         db      0
 335 bufdat:
 336         db      0
 337         dw      0
 338         db      0
 339 inimsg_e:
 340
 341
 342 ;
 343 ;----------------------------------------------------------------------
 344 ;
 345
 346 sysram_init:
 347         ld hl,sysramw
 348         ld de,topcodsys
 349         ld bc,sysrame-sysramw
 350         ldir
 351
 352         ret
 353
 354 ;----------------------------------------------------------------------
 355
 356 ivtab_init:
 357         ld      hl,ivtab        ;
 358         ld      a,h             ;
 359         ld      i,a             ;
 360     if CPU_Z180
 361         out0    (il),l          ;
 362     endif
 363
 364 ; Let all vectors point to spurious int routines.
 365
 366         ld      d,high sp.int0
 367         ld      a,low  sp.int0
 368         ld      b,9
 369 ivt_i1:
 370         ld      (hl),a
 371         inc     l
 372         ld      (hl),d
 373         inc     l
 374         add     a,sp.int.len
 375         djnz    ivt_i1
 376         ret
 377
 378 ;----------------------------------------------------------------------
 379
 380     if CPU_Z180
 381 prt0_init:
 382         ld      a,i
 383         ld      h,a
 384         in0     a,(il)
 385         and     0E0h
 386         or      IV$PRT0
 387         ld      l,a
 388         ld      (hl),low  iprt0
 389         inc     hl
 390         ld      (hl),high iprt0
 391         ld      hl,prt0itab
 392         call    ioiniml
 393         ret
 394
 395 prt0itab:
 396         db      prt0it_e-prt0itab-2
 397         db      tmdr0l
 398         dw      PRT_TC10MS
 399         dw      PRT_TC10MS
 400         db      M_TIE0+M_TDE0   ;enable timer 0 interrupt and down count.
 401 prt0it_e:
 402         db      0
 403     endif
 404
 405
 406 ;
 407 ;----------------------------------------------------------------------
 408 ;
 409
 410     if CPU_Z180
 411 io.ini:
 412      if 0
 413         push    bc
 414         ld      b,0             ;high byte port adress
 415 ioi_nxt:
 416         ld      a,(hl)          ;count
 417         inc     hl
 418         or      a
 419         jr      z,ioi_e
 420
 421         ld      c,(hl)          ;port address
 422         inc     hl
 423 ioi_r:
 424         outi
 425         inc     b               ;outi decrements b
 426         dec     a
 427         jr      nz,ioi_r
 428         jr      ioi_nxt
 429 ioi_e:
 430         pop     bc
 431         ret
 432
 433      else ;(if 1/0)
 434
 435         push    bc
 436         jr      ioi_nxt
 437 ioi_l:
 438         ld      c,(hl)          ;port address
 439         inc     hl
 440         inc     c
 441 ioi_r:
 442         dec     c               ;otim increments c
 443         otim
 444         jr      z,ioi_r
 445 ioi_nxt:
 446         ld      b,(hl)          ;count
 447         inc     hl
 448         inc     b               ;stop if count == 0
 449         djnz    ioi_l
 450         pop     bc
 451         ret
 452
 453      endif ;(1/0)
 454
 455     else
 456
 457 io.ini:
 458         push    bc
 459         jr      ioi_nxt
 460 ioi_l:
 461         ld      c,(hl)          ;port address
 462         inc     hl
 463         otir
 464 ioi_nxt:
 465         ld      b,(hl)          ;count
 466         inc     hl
 467         inc     b
 468         djnz    ioi_l
 469     endif
 470         pop     bc
 471         ret
 472
 473 ;----------------------------------------------------------------------
 474
 475     if CPU_Z180
 476
 477         global ioiniml
 478
 479 ioiniml:
 480         push    bc
 481         xor     a
 482 ioml_lp:
 483         ld      b,(hl)
 484         inc     hl
 485         cp      b
 486         jr      z,ioml_e
 487
 488         ld      c,(hl)
 489         inc     hl
 490         otimr
 491         jr      ioml_lp
 492 ioml_e:
 493         pop     bc
 494         ret     z
 495     endif
 496
 497 io.ini.l:
 498 ;
 499
 500
 501
 502 ;----------------------------------------------------------------------
 503 ;
 504     if CPU_Z180
 505
 506 ;--------------------------------------------------------------------
 507 ; Return the BBR value for the given bank number
 508 ;
 509 ; in  a: Bank number
 510 ; out a: bbr value
 511
 512 bnk2log:
 513         or      a               ;
 514         ret     z               ; Bank 0 is at physical address 0
 515
 516         push    bc              ;
 517         ld      b,a             ;
 518         ld      c,CA            ;
 519         mlt     bc              ;
 520         ld      a,c             ;
 521         add     a,10h           ;
 522         pop     bc              ;
 523         ret                     ;
 524
 525 ;--------------------------------------------------------------
 526
 527 ;in  hl: Log. Address
 528 ;     a: Bank number
 529 ;
 530 ;out ahl: Phys. (linear) Address
 531
 532
 533 bnk2phy:
 534         call    bnk2log
 535         ; fall thru
 536
 537 ;--------------------------------------------------------------
 538 ;
 539 ; hl: Log. Address
 540 ;  a: Bank base (bbr)
 541 ;
 542 ;            2           0       0
 543 ;            0   6       8       0
 544 ; hl              hhhhhhhhllllllll
 545 ;  a    +     bbbbbbbb
 546 ;
 547 ; OP: ahl = (a<<12) + (h<<8) + l
 548 ;
 549 ;out ahl: Phys. (linear) Address
 550
 551 log2phy:
 552         push    bc              ;
 553 l2p_i:
 554         ld      c,a             ;
 555         ld      b,16            ;
 556         mlt     bc              ; bc = a<<4
 557         ld      a,c             ;
 558         add     a,h             ;
 559         ld      h,a             ;
 560         ld      a,b             ;
 561         adc     a,0             ;
 562         pop     bc              ;
 563         ret                     ;
 564
 565 ;--------------------------------------------------------------
 566 ;
 567 ; hl: Log. Address
 568 ;
 569 ;
 570 ; OP: ahl = (bankbase<<12) + (d<<8) + e
 571 ;
 572 ;out ahl: Phys. (linear) Address
 573
 574
 575 hwl2phy:
 576         push    bc              ;
 577         in0     c,(cbar)        ;
 578         ld      a,h             ;
 579         or      00fh            ; log. addr in common1?
 580         cp      c
 581         jr      c,hlp_1
 582
 583         in0     a,(cbr)         ; yes, cbr is address base
 584         jr      hl2p_x
 585 hlp_1:
 586         ld      b,16            ; log. address in baked area?
 587         mlt     bc
 588         ld      a,h
 589         cp      c
 590         jr      c,hlp_2
 591         in0     a,(bbr)         ; yes, bbr is address base
 592         jr      hl2p_x
 593 hlp_2:
 594         xor     a               ; common1
 595 hl2p_x:
 596         jr      nz,l2p_i
 597
 598         pop     bc              ; bank part is 0, no translation
 599         ret                     ;
 600
 601
 602
 603     else        ;CPU_Z180
 604
 605 ;----------------------------------------------------------------------
 606 ;
 607
 608 bnk2phy:
 609         sla     h
 610         jr      nc,b2p_1                ;A15=1 --> common
 611         ld      a,3
 612 b2p_1:
 613         srl     a
 614         rr      h
 615         ret
 616
 617     endif
 618
 619 ;--------------------------------------------------------------
 620 ;
 621 ;return:
 622 ; hl = hl + a
 623 ; Flags undefined
 624 ;
 625
 626 add_hl_a:
 627         add a,l
 628         ld l,a
 629         ret nc
 630         inc h
 631         ret
 632
 633 ; ---------------------------------------------------------
 634
 635 sysramw:
 636
 637         .phase isvsw_loc
 638 topcodsys:
 639
 640 ; Trampoline for interrupt routines in banked ram.
 641 ; Switch stack pointer to "system" stack in top ram
 642 ; Save cbar
 643
 644 isv_sw:                         ;
 645         ex (sp),hl              ;save hl, 'return adr' in hl
 646         push de                 ;
 647         push af                 ;
 648         ex de,hl                ;'return address' in de
 649         ld hl,0                 ;
 650         add hl,sp               ;
 651         ld a,h                  ;
 652         cp 0f8h                 ;
 653         jr nc,isw_1             ;stack allready in top ram
 654         ld sp,$stack            ;
 655 isw_1:
 656         push hl                 ;save user stack pointer
 657         in0 h,(cbar)            ;
 658         push hl                 ;
 659         ld a,SYS$CBAR           ;
 660         out0 (cbar),a           ;
 661         ex de,hl                ;
 662         ld e,(hl)               ;
 663         inc hl                  ;
 664         ld d,(hl)               ;
 665         ex de,hl                ;
 666         push bc                 ;
 667         call jphl               ;
 668
 669         pop bc                  ;
 670         pop hl                  ;
 671         out0 (cbar),h           ;
 672         pop hl                  ;
 673         ld sp,hl                ;
 674         pop af                  ;
 675         pop de                  ;
 676         pop hl                  ;
 677         ei                      ;
 678         ret                     ;
 679 jphl:
 680         jp (hl)                 ;
 681
 682 ; ---------------------------------------------------------
 683
 684     if CPU_Z180
 685
 686 iprt0:
 687         push    af
 688         push    hl
 689         in0     a,(tcr)
 690         in0     a,(tmdr0l)
 691         in0     a,(tmdr0h)
 692         ld      a,(tim_ms)
 693         inc     a
 694         cp      100
 695         jr      nz,iprt_1
 696         xor     a
 697         ld      hl,(tim_s)
 698         inc     hl
 699         ld      (tim_s),hl
 700 iprt_1:
 701         ld      (tim_ms),a
 702         pop     hl
 703         pop     af
 704         ei
 705         ret
 706
 707     endif
 708
 709 ; ---------------------------------------------------------
 710
 711 sp.int0:
 712         ld      a,0d0h
 713         jr      sp.i.1
 714 sp.int.len equ  $-sp.int0
 715         ld      a,0d1h
 716         jr      sp.i.1
 717         ld      a,0d2h
 718         jr      sp.i.1
 719         ld      a,0d3h
 720         jr      sp.i.1
 721         ld      a,0d4h
 722         jr      sp.i.1
 723         ld      a,0d5h
 724         jr      sp.i.1
 725         ld      a,0d6h
 726         jr      sp.i.1
 727         ld      a,0d7h
 728         jr      sp.i.1
 729         ld      a,0d8h
 730 sp.i.1:
 731 ;       out     (80h),a
 732         halt
 733
 734 ; ---------------------------------------------------------
 735
 736     if CPU_Z80
 737
 738 ; Get IFF2
 739 ; This routine may not be loaded in page zero
 740 ;
 741 ; return Carry clear, if INTs are enabled.
 742 ;
 743         global getiff
 744 getiff:
 745         xor     a               ;clear accu and carry
 746         push    af              ;stack bottom := 00xxh
 747         pop     af
 748         ld      a,i             ;P flag := IFF2
 749         ret     pe              ;exit carry clear, if enabled
 750         dec     sp
 751         dec     sp              ;has stack bottom been overwritten?
 752         pop     af
 753         and     a               ;if not 00xxh, INTs were
 754         ret     nz              ;actually enabled
 755         scf                     ;Otherwise, they really are disabled
 756         ret
 757
 758 ;----------------------------------------------------------------------
 759
 760         global  selbnk
 761
 762 ; a: bank (0..2)
 763
 764 selbnk:
 765         push    bc
 766         ld      c,a
 767         call    getiff
 768         push    af
 769
 770         ld      a,c
 771         di
 772         ld      (@cbnk),a
 773         ld      a,5
 774         out     (SIOAC),a
 775         ld      a,(mm_sio0)
 776         rla
 777         srl     c
 778         rra
 779         out     (SIOAC),a
 780         ld      (mm_sio0),a
 781
 782         ld      a,5
 783         out     (SIOBC),a
 784         ld      a,(mm_sio1)
 785         rla
 786         srl     c
 787         rra
 788         out     (SIOBC),a
 789         ld      (mm_sio1),a
 790         pop     af
 791         pop     bc
 792         ret     c                       ;INTs were disabled
 793         ei
 794         ret
 795
 796 ;----------------------------------------------------------------------
 797
 798 ; c: bank (0..2)
 799
 800     if 0
 801
 802 selbnk:
 803         ld      a,(@cbnk)
 804         xor     c
 805         and     3
 806         ret     z               ;no change
 807
 808         call    getiff
 809         push    af
 810         ld      a,c
 811         di
 812         ld      (@cbnk),a
 813         ld      a,5
 814         out     (SIOAC),a
 815         ld      a,(mm_sio0)
 816         rla
 817         srl     c
 818         rra
 819         out     (SIOAC),a
 820         ld      (mm_sio0),a
 821
 822         ld      a,5
 823         out     (SIOBC),a
 824         ld      a,(mm_sio1)
 825         rla
 826         srl     c
 827         rra
 828         out     (SIOBC),a
 829         ld      (mm_sio1),a
 830         pop     af
 831         ret     nc                      ;INTs were disabled
 832         ei
 833         ret
 834
 835     endif
 836
 837 ;----------------------------------------------------------------------
 838
 839     if 0
 840         ex      af,af'
 841         push    af
 842         ex      af,af'
 843
 844         rra
 845         jr      nc,stbk1
 846         ex      af,af'
 847         ld      a,5
 848         out     (SIOAC),a
 849         ld      a,(mm_sio0)
 850         rla
 851         srl     c
 852         rra
 853         out     (SIOAC),a
 854         ld      (mm_sio1),a
 855         ex      af,af'
 856
 857 stbk1:
 858         rra
 859         jr      nc,stbk2
 860         ex      af,af'
 861         ld      a,5
 862         out     (SIOBC),a
 863         ld      a,(mm_sio1)
 864         rla
 865         srl     c
 866         rra
 867         out     (SIOBC),a
 868         ld      (mm_sio1),a
 869         ex      af,af'
 870
 871 stbk2:
 872     endif
 873
 874         global  @cbnk
 875         global  mm_sio0, mm_sio1
 876
 877 @cbnk:  db      0               ; current bank (0..2)
 878 mm_sio0:
 879         ds      1
 880 mm_sio1:
 881         ds      1
 882
 883
 884     endif
 885
 886 ;----------------------------------------------------------------------
 887
 888 curph   defl    $
 889         .dephase
 890 sysrame:
 891         .phase curph
 892 tim_ms: db      0
 893 tim_s:  dw      0
 894         .dephase
 895
 896 ;-----------------------------------------------------
 897
 898
 899         cseg
 900
 901         ;.phase 0ffc0h
 902 ;ivtab  equ     0ffc0h          ; 0ffc0h        ;int vector table
 903         ;.dephase
 904
 905         ;.phase 0fffah
 906 mark_55AA equ 0 - 2 - 4         ;2 byte for trap stack
 907         ;ds     4
 908         ;.dephase
 909
 910
 911         end
 912