avr/z180-serv.c

   1 #include "common.h"
   2 #include <util/atomic.h>
   3
   4 #include "background.h"
   5 #include "serial.h"
   6 #include "z80-if.h"
   7 #include "debug.h"
   8 #include "z180-serv.h"
   9
  10
  11
  12 /*--------------------------------------------------------------------------*/
  13
  14
  15 uint8_t z80_get_byte(uint32_t adr)
  16 {
  17         uint8_t data;
  18
  19         z80_bus_cmd(Request);
  20         data = z80_read(adr);
  21         z80_bus_cmd(Release);
  22
  23         return data;
  24 }
  25
  26
  27 /*--------------------------------------------------------------------------*/
  28
  29 struct msg_item {
  30         uint8_t fct;
  31         uint8_t sub_min, sub_max;
  32         void (*func)(uint8_t, int, uint8_t *);
  33 };
  34
  35 uint32_t msg_to_addr(uint8_t *msg)
  36 {
  37         union {
  38                 uint32_t as32;
  39                 uint8_t as8[4];
  40         } addr;
  41
  42         addr.as8[0] = msg[0];
  43         addr.as8[1] = msg[1];
  44         addr.as8[2] = msg[2];
  45         addr.as8[3] = 0;
  46
  47         return addr.as32;
  48 }
  49
  50
  51 void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
  52 {
  53         (void)len;
  54
  55         z80_memfifo_init(subf, msg_to_addr(msg));
  56 }
  57
  58
  59 void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
  60 {
  61         (void)subf;
  62
  63         while (len--)
  64                 putchar(*msg++);
  65 }
  66
  67
  68 const FLASH struct msg_item z80_messages[] =
  69 {
  70         { 0,                    /* fct nr. */
  71           1, 3,                 /* sub fct nr. from, to */
  72           do_msg_ini_memfifo},
  73         { 1,
  74           1, 1,
  75           do_msg_char_out},
  76         { 0xff,                         /* end mark */
  77           0, 0,
  78           0},
  79
  80 };
  81
  82
  83
  84
  85 void do_message(int len, uint8_t *msg)
  86 {
  87         uint8_t fct, sub_fct;
  88         int_fast8_t i = 0;
  89
  90         if (len >= 2) {
  91                 fct = *msg++;
  92                 sub_fct = *msg++;
  93                 len -= 2;
  94
  95                 while (fct != z80_messages[i].fct) {
  96                         if (z80_messages[i].fct == 0xff) {
  97                                 DBG_P(1, "do_message: Unknown function: %i, %i\n",
  98                                                 fct, sub_fct);
  99                                 return; /* TODO: unknown message # */
 100                         }
 101
 102                         ++i;
 103                 }
 104
 105                 while (fct == z80_messages[i].fct) {
 106                         if (sub_fct >= z80_messages[i].sub_min &&
 107                                         sub_fct <= z80_messages[i].sub_max )
 108                                 break;
 109                         ++i;
 110                 }
 111
 112                 if (z80_messages[i].fct != fct) {
 113                         DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
 114                                         fct, sub_fct);
 115                         return; /* TODO: unknown message sub# */
 116                 }
 117
 118                 (z80_messages[i].func)(sub_fct, len, msg);
 119
 120
 121         } else {
 122                 /* TODO: error */
 123                 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
 124         }
 125 }
 126
 127
 128
 129 #define CTRBUF_LEN 256
 130
 131 void check_msg_fifo(void)
 132 {
 133         int ch;
 134         static int_fast8_t state;
 135         static int msglen,idx;
 136         static uint8_t buffer[CTRBUF_LEN];
 137
 138         while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
 139                 switch (state) {
 140                 case 0:         /* wait for start of message */
 141                         if (ch == 0xAE) { /* TODO: magic number */
 142                                 msglen = 0;
 143                                 idx = 0;
 144                                 state = 1;
 145                         }
 146                         break;
 147                 case 1:         /* get msg len */
 148                         if (ch > 0 && ch <= CTRBUF_LEN) {
 149                                 msglen = ch;
 150                                 state = 2;
 151                         } else
 152                                 state = 0;
 153                         break;
 154                 case 2:         /* get message */
 155                         buffer[idx++] = ch;
 156                         if (idx == msglen) {
 157                                 do_message(msglen, buffer);
 158                                 state = 0;
 159                         }
 160                         break;
 161                 }
 162         }
 163 }
 164
 165
 166 int msg_handling(int state)
 167 {
 168         uint8_t pending;
 169
 170         ATOMIC_BLOCK(ATOMIC_FORCEON) {
 171                 pending = (Stat & S_MSG_PENDING) != 0;
 172                 Stat &= ~S_MSG_PENDING;
 173         }
 174
 175         if (pending) {
 176                 switch (state) {
 177                 case 0:
 178                         z80_bus_cmd(Request);
 179                         uint32_t addr = z80_read(0x40) +
 180                                 ((uint16_t) z80_read(0x41) << 8) +
 181                                 ((uint32_t) z80_read(0x42) << 16);
 182                         z80_bus_cmd(Release);
 183                         if (addr != 0) {
 184                                 z80_memfifo_init(fifo_msgin, addr);
 185                                 state = 1;
 186                         }
 187                         break;
 188                 case 1:
 189                         check_msg_fifo();
 190                         break;
 191                 }
 192         }
 193
 194         return state;
 195 }
 196
 197
 198 static int handle_msg_handling;
 199
 200 void setup_z180_serv(void)
 201 {
 202
 203         handle_msg_handling = bg_register(msg_handling, 0);
 204 }
 205
 206 void restart_z180_serv(void)
 207 {
 208         z80_bus_cmd(Request);
 209         z80_write(0x40, 0);
 210         z80_write(0x41, 0);
 211         z80_write(0x42, 0);
 212         z80_bus_cmd(Release);
 213
 214         for (int i = 0; i < NUM_FIFOS; i++)
 215                 z80_memfifo_init(i, 0);
 216         bg_setstat(handle_msg_handling, 0);
 217 }
 218
 219 /*--------------------------------------------------------------------------*/
 220
 221 #if 0
 222 void dump_mem(const FLASH uint8_t *addr, uint32_t len)
 223 {
 224         DBG_P(1, "hdrom dump:");
 225         while (len) {
 226                 DBG_P(1, "\n    %.5x:", addr);
 227                 for (unsigned i = 0; i<16; i++)
 228                         DBG_P(1, " %.2x", *addr++);
 229                 len -= len > 16 ? 16 : len;
 230         }
 231         DBG_P(1, "\n");
 232 }
 233 #endif
 234 /*--------------------------------------------------------------------------*/
 235
 236
 237 const FLASH uint8_t iniprog[] = {
 238         0xAF,                   // xor     a
 239         0xED, 0x39, 0x36,       // out0    (rcr),a         ;disable  DRAM refresh
 240         0x3E, 0x30,             // ld      a,030h
 241         0xED, 0x39, 0x32        //out0    (dcntl),a       ;0 mem, max i/0 wait states
 242 };
 243
 244 const FLASH uint8_t sertest[] = {
 245         0xAF,              //   xor     a
 246         0xED, 0x39, 0x36,  //   out0    (rcr),a         ;disable  DRAM refresh
 247         0x3E, 0x30,        //   ld      a,030h
 248         0xED, 0x39, 0x32,  //   out0    (dcntl),a       ;0 mem, max i/0 wait states
 249         0x3E, 0x80,        //   ld      a,M_MPBT                ;no MP, PS=10, DR=16, SS=0
 250         0xED, 0x39, 0x03,  //   out0    (cntlb1),a
 251         0x3E, 0x64,        //   ld      a,M_RE + M_TE + M_MOD2  ;
 252         0xED, 0x39, 0x01,  //   out0    (cntla1),a
 253         0x3E, 0x00,        //   ld      a,0
 254         0xED, 0x39, 0x05,  //   out0    (stat1),a       ;Enable rx interrupts
 255         0xED, 0x38, 0x05,  //l0:in0     a,(stat1)
 256         0xE6, 0x80,        //   and     80h
 257         0x28, 0xF9,        //   jr      z,l0
 258         0xED, 0x00, 0x09,  //   in0     b,(rdr1)
 259         0xED, 0x38, 0x05,  //l1:in0     a,(stat1)
 260         0xE6, 0x02,        //   and     02h
 261         0x28, 0xF9,        //   jr      z,l1
 262         0xED, 0x01, 0x07,  //   out0    (tdr1),b
 263         0x18, 0xEA,        //   jr      l0
 264 };
 265
 266 const FLASH uint8_t test1[] = {
 267         0xAF,              //   xor     a
 268         0xED, 0x39, 0x36,  //   out0    (rcr),a         ;disable  DRAM refresh
 269         0x3E, 0x30,        //   ld      a,030h
 270         0xED, 0x39, 0x32,  //   out0    (dcntl),a       ;0 mem, max i/0 wait states
 271         0x21, 0x1E, 0x00,  //   ld      hl,dmclrt       ;load DMA registers
 272         0x06, 0x08,        //   ld      b,dmct_e-dmclrt
 273         0x0E, 0x20,        //   ld      c,sar0l
 274         0xED, 0x93,        //   otimr
 275         0x3E, 0xC3,        //   ld      a,0c3h          ;dst +1, src +1, burst
 276         0xED, 0x39, 0x31,  //   out0    (dmode),a       ;
 277         0x3E, 0x62,        //   ld      a,062h          ;enable dma0,
 278         0xED, 0x39, 0x30,  //cl_1:      out0    (dstat),a       ;copy 64k
 279         0x18, 0xFB,        //   jr      cl_1            ;
 280         0x00, 0x00,        //dmclrt:    dw      0               ;src (inc)
 281         0x00,              //   db      0               ;src
 282         0x00, 0x00,        //   dw      0               ;dst (inc),
 283         0x00,              //   db      0               ;dst
 284         0x00, 0x00,        //   dw      0               ;count (64k)
 285 };
 286
 287
 288