avr/z180-serv.c

   1 /*
   2  * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include "common.h"
   8 #include <util/atomic.h>
   9
  10 #include "background.h"
  11 #include "serial.h"
  12 #include "z80-if.h"
  13 #include "debug.h"
  14 #include "z180-serv.h"
  15
  16 /*--------------------------------------------------------------------------*/
  17
  18
  19 uint8_t z80_get_byte(uint32_t adr)
  20 {
  21         uint8_t data;
  22
  23         z80_bus_cmd(Request);
  24         data = z80_read(adr);
  25         z80_bus_cmd(Release);
  26
  27         return data;
  28 }
  29
  30
  31 /*--------------------------------------------------------------------------*/
  32
  33 struct msg_item {
  34         uint8_t fct;
  35         uint8_t sub_min, sub_max;
  36         void (*func)(uint8_t, int, uint8_t *);
  37 };
  38
  39 uint32_t msg_to_addr(uint8_t *msg)
  40 {
  41         union {
  42                 uint32_t as32;
  43                 uint8_t as8[4];
  44         } addr;
  45
  46         addr.as8[0] = msg[0];
  47         addr.as8[1] = msg[1];
  48         addr.as8[2] = msg[2];
  49         addr.as8[3] = 0;
  50
  51         return addr.as32;
  52 }
  53
  54
  55 void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
  56 {
  57         (void)len;
  58
  59         z80_memfifo_init(subf, msg_to_addr(msg));
  60 }
  61
  62
  63 void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
  64 {
  65         (void)subf;
  66
  67         while (len--)
  68                 putchar(*msg++);
  69 }
  70
  71
  72 const FLASH struct msg_item z80_messages[] =
  73 {
  74         { 0,                    /* fct nr. */
  75           1, 3,                 /* sub fct nr. from, to */
  76           do_msg_ini_memfifo},
  77         { 1,
  78           1, 1,
  79           do_msg_char_out},
  80         { 0xff,                         /* end mark */
  81           0, 0,
  82           0},
  83
  84 };
  85
  86
  87
  88
  89 void do_message(int len, uint8_t *msg)
  90 {
  91         uint8_t fct, sub_fct;
  92         int_fast8_t i = 0;
  93
  94         if (len >= 2) {
  95                 fct = *msg++;
  96                 sub_fct = *msg++;
  97                 len -= 2;
  98
  99                 while (fct != z80_messages[i].fct) {
 100                         if (z80_messages[i].fct == 0xff) {
 101                                 DBG_P(1, "do_message: Unknown function: %i, %i\n",
 102                                                 fct, sub_fct);
 103                                 return; /* TODO: unknown message # */
 104                         }
 105
 106                         ++i;
 107                 }
 108
 109                 while (fct == z80_messages[i].fct) {
 110                         if (sub_fct >= z80_messages[i].sub_min &&
 111                                         sub_fct <= z80_messages[i].sub_max )
 112                                 break;
 113                         ++i;
 114                 }
 115
 116                 if (z80_messages[i].fct != fct) {
 117                         DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
 118                                         fct, sub_fct);
 119                         return; /* TODO: unknown message sub# */
 120                 }
 121
 122                 (z80_messages[i].func)(sub_fct, len, msg);
 123
 124
 125         } else {
 126                 /* TODO: error */
 127                 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
 128         }
 129 }
 130
 131
 132
 133 #define CTRBUF_LEN 256
 134
 135 void check_msg_fifo(void)
 136 {
 137         int ch;
 138         static int_fast8_t state;
 139         static int msglen,idx;
 140         static uint8_t buffer[CTRBUF_LEN];
 141
 142         while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
 143                 switch (state) {
 144                 case 0:         /* wait for start of message */
 145                         if (ch == 0xAE) { /* TODO: magic number */
 146                                 msglen = 0;
 147                                 idx = 0;
 148                                 state = 1;
 149                         }
 150                         break;
 151                 case 1:         /* get msg len */
 152                         if (ch > 0 && ch <= CTRBUF_LEN) {
 153                                 msglen = ch;
 154                                 state = 2;
 155                         } else
 156                                 state = 0;
 157                         break;
 158                 case 2:         /* get message */
 159                         buffer[idx++] = ch;
 160                         if (idx == msglen) {
 161                                 do_message(msglen, buffer);
 162                                 state = 0;
 163                         }
 164                         break;
 165                 }
 166         }
 167 }
 168
 169
 170 int msg_handling(int state)
 171 {
 172         uint8_t pending;
 173
 174         ATOMIC_BLOCK(ATOMIC_FORCEON) {
 175                 pending = (Stat & S_MSG_PENDING) != 0;
 176                 Stat &= ~S_MSG_PENDING;
 177         }
 178
 179         if (pending) {
 180                 switch (state) {
 181                 case 0:
 182                         z80_bus_cmd(Request);
 183                         uint32_t addr = z80_read(0x40) +
 184                                 ((uint16_t) z80_read(0x41) << 8) +
 185                                 ((uint32_t) z80_read(0x42) << 16);
 186                         z80_bus_cmd(Release);
 187                         if (addr != 0) {
 188                                 z80_memfifo_init(fifo_msgin, addr);
 189                                 state = 1;
 190                         }
 191                         break;
 192                 case 1:
 193                         check_msg_fifo();
 194                         break;
 195                 }
 196         }
 197
 198         return state;
 199 }
 200
 201
 202 static int handle_msg_handling;
 203
 204 void setup_z180_serv(void)
 205 {
 206
 207         handle_msg_handling = bg_register(msg_handling, 0);
 208 }
 209
 210 void restart_z180_serv(void)
 211 {
 212         z80_bus_cmd(Request);
 213         z80_write(0x40, 0);
 214         z80_write(0x41, 0);
 215         z80_write(0x42, 0);
 216         z80_bus_cmd(Release);
 217
 218         for (int i = 0; i < NUM_FIFOS; i++)
 219                 z80_memfifo_init(i, 0);
 220         bg_setstat(handle_msg_handling, 0);
 221 }
 222
 223 /*--------------------------------------------------------------------------*/
 224
 225 const FLASH uint8_t iniprog[] = {
 226         0xAF,                   // xor     a
 227         0xED, 0x39, 0x36,       // out0    (rcr),a         ;disable  DRAM refresh
 228         0x3E, 0x30,             // ld      a,030h
 229         0xED, 0x39, 0x32        //out0    (dcntl),a       ;0 mem, max i/0 wait states
 230 };
 231
 232 const FLASH uint8_t sertest[] = {
 233         0xAF,              //   xor     a
 234         0xED, 0x39, 0x36,  //   out0    (rcr),a         ;disable  DRAM refresh
 235         0x3E, 0x30,        //   ld      a,030h
 236         0xED, 0x39, 0x32,  //   out0    (dcntl),a       ;0 mem, max i/0 wait states
 237         0x3E, 0x80,        //   ld      a,M_MPBT                ;no MP, PS=10, DR=16, SS=0
 238         0xED, 0x39, 0x03,  //   out0    (cntlb1),a
 239         0x3E, 0x64,        //   ld      a,M_RE + M_TE + M_MOD2  ;
 240         0xED, 0x39, 0x01,  //   out0    (cntla1),a
 241         0x3E, 0x00,        //   ld      a,0
 242         0xED, 0x39, 0x05,  //   out0    (stat1),a       ;Enable rx interrupts
 243         0xED, 0x38, 0x05,  //l0:in0     a,(stat1)
 244         0xE6, 0x80,        //   and     80h
 245         0x28, 0xF9,        //   jr      z,l0
 246         0xED, 0x00, 0x09,  //   in0     b,(rdr1)
 247         0xED, 0x38, 0x05,  //l1:in0     a,(stat1)
 248         0xE6, 0x02,        //   and     02h
 249         0x28, 0xF9,        //   jr      z,l1
 250         0xED, 0x01, 0x07,  //   out0    (tdr1),b
 251         0x18, 0xEA,        //   jr      l0
 252 };
 253
 254 const FLASH uint8_t test1[] = {
 255         0xAF,              //   xor     a
 256         0xED, 0x39, 0x36,  //   out0    (rcr),a         ;disable  DRAM refresh
 257         0x3E, 0x30,        //   ld      a,030h
 258         0xED, 0x39, 0x32,  //   out0    (dcntl),a       ;0 mem, max i/0 wait states
 259         0x21, 0x1E, 0x00,  //   ld      hl,dmclrt       ;load DMA registers
 260         0x06, 0x08,        //   ld      b,dmct_e-dmclrt
 261         0x0E, 0x20,        //   ld      c,sar0l
 262         0xED, 0x93,        //   otimr
 263         0x3E, 0xC3,        //   ld      a,0c3h          ;dst +1, src +1, burst
 264         0xED, 0x39, 0x31,  //   out0    (dmode),a       ;
 265         0x3E, 0x62,        //   ld      a,062h          ;enable dma0,
 266         0xED, 0x39, 0x30,  //cl_1:      out0    (dstat),a       ;copy 64k
 267         0x18, 0xFB,        //   jr      cl_1            ;
 268         0x00, 0x00,        //dmclrt:    dw      0               ;src (inc)
 269         0x00,              //   db      0               ;src
 270         0x00, 0x00,        //   dw      0               ;dst (inc),
 271         0x00,              //   db      0               ;dst
 272         0x00, 0x00,        //   dw      0               ;count (64k)
 273 };