5 * | Z180-Sig | STM32-Port | Buffer | Dir |Special Function |
6 * | -------- | ---------- | ------ | --- | --------------- |
17 * | A10 |C 2 |P |O | |
18 * | A11 |C 3 |P |O | |
19 * | A12 |C 4 |P |O | |
20 * | A13 |C 5 |P |O | |
23 * | A16 |C 10 | |O | |
24 * | A17 |C 11 | |O | |
25 * | A18 |C 12 | |O | |
26 * | D0 |B 8 | |I/O | |
27 * | D1 |B 9 | |I/O | |
28 * | D2 |B 10 | |I/O | |
29 * | D3 |B 11 | |I/O | |
30 * | D4 |B 12 | |I/O | |
31 * | D5 |B 13 | |I/O | |
32 * | D6 |B 14 | |I/O | |
33 * | D7 |B 15 | |I/O | |
34 * | ME |C 13 |P |O | |
37 * | BUSREQ |D 2 | |O | |
38 * | IOCS1 |A 11 | |I |TIM1_CH4 |
39 * | BUSACK |A 12 | |I | |
40 * | HALT |A 12 | |I | |
42 * | RST |B 6 | |O |TIM16_CH1N |
44 * | |A 9 | | |af1 USART1_TX |
45 * | |A 10 | | |af1 USART1_RX |
46 * | |A 15 | |JTDI | remap SPI1_NSS' |
47 * | |B 3 | |JTDO |remap SPI1_SCK' |
48 * | |B 4 | |NJTRST |remap SPI1_MISO' |
49 * | |B 5 | | |remap SPI1_MOSI' |
50 * | |C 14 | | |af1 OSC32 |
51 * | |C 15 | | |af1 OSC32 |
55 AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees
63 #include <libopencm3/stm32/gpio.h>
64 #include <libopencm3/stm32/rcc.h>
65 #include <libopencm3/stm32/timer.h>
66 #include <libopencm3/stm32/dma.h>
71 /* Number of array elements */
72 #define NELEMS(x) (sizeof x/sizeof *x)
77 #define CONCAT(x,y) x ## y
78 #define EVALUATOR(x,y) CONCAT(x,y)
80 #define GPIO_(X) CONCAT(GPIO, X)
91 #define P_BUSREQ GPIOD
93 #define P_BUSACK GPIOA
95 //#define P_HALT GPIOA
107 #define ADp1_PORT GPIOA
109 #define ADp2_OFS ADp1_WIDTH
112 #define ADp2_PORT GPIOC
114 #define ADp3_OFS (ADp2_OFS+ADp2_WIDTH)
116 #define ADp3_SHIFT 10
117 #define ADp3_PORT GPIOC
119 #define ADunbuff1_WIDTH 1
120 #define ADunbuff1_SHIFT 8
121 #define ADunbuff1_PORT GPIOA
123 #define ADunbuff2_WIDTH 2
124 #define ADunbuff2_SHIFT 6
125 #define ADunbuff2_PORT GPIOC
127 #define ADunbuff3_WIDTH 3
128 #define ADunbuff3_SHIFT 10
129 #define ADunbuff3_PORT GPIOC
134 #define DB_PORT GPIOB
136 #define GPIO_ME GPIO_(ME)
137 #define GPIO_RD GPIO_(RD)
138 #define GPIO_WR GPIO_(WR)
139 #define GPIO_BUSREQ GPIO_(BUSREQ)
140 #define GPIO_BUSACK GPIO_(BUSACK)
141 //#define GPIO_HALT GPIO_(HALT)
142 #define GPIO_IOCS1 GPIO_(IOCS1)
143 #define GPIO_NMI GPIO_(NMI)
144 #define GPIO_RST GPIO_(RST)
146 #define Z80_O_ME BBIO_PERIPH(P_ME+ODR, ME)
147 #define Z80_O_RD BBIO_PERIPH(P_RD+ODR, RD)
148 #define Z80_O_WR BBIO_PERIPH(P_WR+ODR, WR)
149 #define Z80_O_BUSREQ BBIO_PERIPH(P_BUSREQ+ODR, BUSREQ)
150 #define Z80_O_NMI BBIO_PERIPH(P_NMI+ODR, NMI)
151 #define Z80_O_RST BBIO_PERIPH(P_RST+ODR, RST)
153 #define Z80_I_BUSACK BBIO_PERIPH(P_BUSACK+IDR, BUSACK)
154 //#define Z80_I_HALT BBIO_PERIPH(P_HALT+IDR, HALT)
157 #define MASK(n) ((1<<n)-1)
159 #define IOFIELD_SET(src, ofs, width, shift) \
160 ((((src>>ofs) & MASK(width)) << shift) | ((((~src>>ofs) & MASK(width)) << shift) << 16))
162 #define IOFIELD_GET(src, width, shift) \
163 ((src>>shift) & MASK(width))
165 #define CNF_MODE_I_F (GPIO_CNF_INPUT_FLOAT<<2 |GPIO_MODE_INPUT)
166 #define CNF_MODE_O_PP (GPIO_CNF_OUTPUT_PUSHPULL<<2 | GPIO_MODE_OUTPUT_10_MHZ)
168 #define DB_MODE_INPUT ( (CNF_MODE_I_F << (4 * 0)) \
169 | (CNF_MODE_I_F << (4 * 1)) \
170 | (CNF_MODE_I_F << (4 * 2)) \
171 | (CNF_MODE_I_F << (4 * 3)) \
172 | (CNF_MODE_I_F << (4 * 4)) \
173 | (CNF_MODE_I_F << (4 * 5)) \
174 | (CNF_MODE_I_F << (4 * 6)) \
175 | (CNF_MODE_I_F << (4 * 7)))
177 #define DB_MODE_OUTPUT ( (CNF_MODE_O_PP << (4 * 0)) \
178 | (CNF_MODE_O_PP << (4 * 1)) \
179 | (CNF_MODE_O_PP << (4 * 2)) \
180 | (CNF_MODE_O_PP << (4 * 3)) \
181 | (CNF_MODE_O_PP << (4 * 4)) \
182 | (CNF_MODE_O_PP << (4 * 5)) \
183 | (CNF_MODE_O_PP << (4 * 6)) \
184 | (CNF_MODE_O_PP << (4 * 7)))
187 /*--------------------------------------------------------------------------*/
189 static void tim16_setup(void)
191 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM16RST
;
192 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM16RST
;
194 TIM16_BDTR
= TIM_BDTR_MOE
;
197 | TIM_CCMR1_OC1M_FORCE_LOW
198 | TIM_CCMR1_CC1S_OUT
;
200 TIM16_CCER
= TIM_CCER_CC1NE
203 TIM16_ARR
= 48; /* default */
204 TIM16_CCR1
= 1; /* */
207 /*--------------------------------------------------------------------------*/
209 static void tim16_set(int mode
)
213 cc_mode
= TIM_CCMR1_CC1S_OUT
;
215 TIM16_CR1
= TIM_CR1_OPM
;
218 cc_mode
|= TIM_CCMR1_OC1M_FORCE_LOW
;
220 cc_mode
|= TIM_CCMR1_OC1M_FORCE_HIGH
;
223 cc_mode
|= TIM_CCMR1_OC1M_PWM2
;
226 TIM16_CCMR1
= cc_mode
;
229 TIM16_CR1
|= TIM_CR1_CEN
;
232 /*--------------------------------------------------------------------------*/
237 * A0..A6, A8..A13 are buffered. No need to disable.
238 * A7, A14..A18: set to input.
241 static void z80_setup_adrbus_tristate(void)
244 gpio_set_mode(ADunbuff1_PORT
, GPIO_MODE_INPUT
,
245 GPIO_CNF_INPUT_FLOAT
, MASK(ADunbuff1_WIDTH
) << ADunbuff1_SHIFT
);
246 gpio_set_mode(ADunbuff2_PORT
, GPIO_MODE_INPUT
, GPIO_CNF_INPUT_FLOAT
,
247 (MASK(ADunbuff2_WIDTH
) << ADunbuff2_SHIFT
) | (MASK(ADunbuff3_WIDTH
) << ADunbuff3_SHIFT
));
249 GPIO_CRH(GPIOA
) = (GPIO_CRH(GPIOA
) & ~(0x0f << (4 * 0)))
250 | (CNF_MODE_I_F
<< (4 * 0));
251 GPIO_CRL(GPIOC
) = (GPIO_CRL(GPIOC
) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
252 | ((CNF_MODE_I_F
<< (4 * 6)) | (CNF_MODE_I_F
<< (4 * 7)));
253 GPIO_CRH(GPIOC
) = (GPIO_CRH(GPIOC
) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
254 | ((CNF_MODE_I_F
<< (4*2)) | (CNF_MODE_I_F
<< (4*3)) | (CNF_MODE_I_F
<< (4*4)));
259 static void z80_setup_adrbus_active(void)
262 gpio_set_mode(ADunbuff1_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
263 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADunbuff1_WIDTH
) << ADunbuff1_SHIFT
);
264 gpio_set_mode(ADunbuff2_PORT
, GPIO_MODE_OUTPUT_10_MHZ
, GPIO_CNF_OUTPUT_PUSHPULL
,
265 (MASK(ADunbuff2_WIDTH
) << ADunbuff2_SHIFT
) | (MASK(ADunbuff3_WIDTH
) << ADunbuff3_SHIFT
));
267 GPIO_CRH(GPIOA
) = (GPIO_CRH(GPIOA
) & ~(0x0f << (4 * 0)))
268 | (CNF_MODE_O_PP
<< (4 * 0));
269 GPIO_CRL(GPIOC
) = (GPIO_CRL(GPIOC
) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
270 | ((CNF_MODE_O_PP
<< (4 * 6)) | (CNF_MODE_O_PP
<< (4 * 7)));
271 GPIO_CRH(GPIOC
) = (GPIO_CRH(GPIOC
) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
272 | ((CNF_MODE_O_PP
<< (4*2)) | (CNF_MODE_O_PP
<< (4*3)) | (CNF_MODE_O_PP
<< (4*4)));
277 static void z80_setup_dbus_in(void)
279 GPIO_CRH(DB_PORT
) = DB_MODE_INPUT
;
282 static void z80_setup_dbus_out(void)
284 GPIO_CRH(DB_PORT
) = DB_MODE_OUTPUT
;
288 static void z80_setaddress(uint32_t addr
)
290 GPIO_BSRR(ADp1_PORT
) = IOFIELD_SET(addr
, ADp1_OFS
, ADp1_WIDTH
, ADp1_SHIFT
);
291 GPIO_BSRR(ADp2_PORT
) = IOFIELD_SET(addr
, ADp2_OFS
, ADp2_WIDTH
, ADp2_SHIFT
);
292 GPIO_BSRR(ADp3_PORT
) = IOFIELD_SET(addr
, ADp3_OFS
, ADp3_WIDTH
, ADp3_SHIFT
);
295 void z80_setup_bus(void)
299 gpio_set_mode(P_RST
, GPIO_MODE_OUTPUT_10_MHZ
,
300 GPIO_CNF_OUTPUT_ALTFN_PUSHPULL
, GPIO_RST
);
302 gpio_set_mode(P_BUSREQ
, GPIO_MODE_OUTPUT_10_MHZ
,
303 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_BUSREQ
);
305 gpio_set_mode(P_NMI
, GPIO_MODE_OUTPUT_10_MHZ
,
306 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_NMI
);
310 gpio_set_mode(P_ME
, GPIO_MODE_OUTPUT_2_MHZ
,
311 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_ME
);
312 gpio_set_mode(P_RD
, GPIO_MODE_OUTPUT_10_MHZ
,
313 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_RD
| GPIO_WR
);
316 //while(Z80_I_BUSACK == 1);
318 gpio_set_mode(ADp1_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
319 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp1_WIDTH
) << ADp1_SHIFT
);
320 gpio_set_mode(ADp2_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
321 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp2_WIDTH
) << ADp2_SHIFT
);
322 gpio_set_mode(ADp3_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
323 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp3_WIDTH
) << ADp3_SHIFT
);
328 void z80_request_bus(void)
331 while(Z80_I_BUSACK
== 1);
332 z80_setup_adrbus_active();
335 void z80_release_bus(void)
338 z80_setup_adrbus_tristate();
340 while(Z80_I_BUSACK
== 0);
343 void z80_reset(level_t level
)
345 int x
= level
? -1 : 0;
349 // Z80_O_RST = level;
352 void z80_reset_pulse(void)
357 void z80_busreq(level_t level
)
359 Z80_O_BUSREQ
= level
;
363 int z80_stat_halt(void)
369 void z80_write(uint32_t addr
, uint8_t data
)
371 z80_setaddress(addr
);
373 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
374 z80_setup_dbus_out();
380 uint8_t z80_read(uint32_t addr
)
384 z80_setaddress(addr
);
389 data
= IOFIELD_GET(GPIO_IDR(DB_PORT
),DB_WIDTH
, DB_SHIFT
);
397 void z80_memset(uint32_t addr
, uint8_t data
, int length
)
399 z80_setup_dbus_out();
402 z80_setaddress(addr
++);
403 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
410 void z80_write_block(uint8_t *src
, uint32_t dest
, uint32_t length
)
414 z80_setup_dbus_out();
417 z80_setaddress(dest
++);
419 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
427 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
428 017A' rx.in_idx: ds 1 ;
429 017B' rx.out_idx: ds 1 ;
430 017C' rx.buf: ds rx.buf_len ;
431 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
433 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
434 018D' tx.in_idx: ds 1 ;
435 018E' tx.out_idx: ds 1 ;
436 018F' tx.buf: ds tx.buf_len ;
437 019E' tx.buf_end equ $-1 ; last byte
441 typedef struct __attribute__((packed
)) {
450 #define FIFO_BUFSIZE_MASK -3
451 #define FIFO_INDEX_IN -2
452 #define FIFO_INDEX_OUT -1
460 } fifo_dsc
[NUM_FIFOS
];
463 void z80_memfifo_init(const fifo_t f
, uint32_t adr
)
466 DBG_P(2, "z80_memfifo_init: %i, %lx\n", f
, adr
);
468 fifo_dsc
[f
].base
= adr
;
472 fifo_dsc
[f
].mask
= z80_read(adr
+ FIFO_BUFSIZE_MASK
);
473 fifo_dsc
[f
].idx_in
= z80_read(adr
+ FIFO_INDEX_IN
);
474 fifo_dsc
[f
].idx_out
= z80_read(adr
+ FIFO_INDEX_OUT
);
480 int z80_memfifo_is_empty(const fifo_t f
)
484 if (fifo_dsc
[f
].base
!= 0) {
486 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
492 rc
= idx
== fifo_dsc
[f
].idx_out
;
498 int z80_memfifo_is_full(const fifo_t f
)
502 if (fifo_dsc
[f
].base
!= 0) {
504 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
505 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
511 uint8_t z80_memfifo_getc(const fifo_t f
)
515 while (z80_memfifo_is_empty(f
))
519 idx
= fifo_dsc
[f
].idx_out
;
520 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
521 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
522 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
529 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
533 while (z80_memfifo_is_full(f
))
537 idx
= fifo_dsc
[f
].idx_in
;
538 z80_write(fifo_dsc
[f
].base
+idx
, val
);
539 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
540 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
544 /*--------------------------------------------------------------------------*/
548 //uint8_t idx_out, idx_in;
553 /*--------------------------------------------------------------------------*/
557 static void tim1_setup(void)
559 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM1RST
;
560 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM1RST
;
566 /* | TIM_SMCR_ETF_CK_INT_N_2 */
571 TIM1_DIER
= TIM_DIER_TDE
;
575 | TIM_CCMR1_OC1M_FORCE_LOW
576 | TIM_CCMR1_CC1S_OUT
;
578 TIM1_SMCR
|= TIM_SMCR_SMS_TM
;
583 /*--------------------------------------------------------------------------*/
585 static void tim1_ch4_setup(void)
588 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM1RST
;
589 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM1RST
;
592 | TIM_CCMR2_CC4S_IN_TI2
594 | TIM_CCMR2_IC4PSC_OFF
;
597 /* | TIM_CCER_CC4P */
600 /* Enable DMA for channel 4 */
601 TIM1_DIER
= TIM_DIER_CC4DE
;
604 /*--------------------------------------------------------------------------*/
606 static void dma1_ch4_setup(void)
615 DMA1_CMAR4
= (uint32_t) msg_fifo
.buf
;
617 #if (DB_SHIFT == 0) || (DB_SHIFT == 8)
618 DMA1_CPAR4
= DB_PORT
+ IDR
+ DB_SHIFT
/8;
620 #error "Databus not byte aligned!"
623 DMA1_CNDTR4
= NELEMS(msg_fifo
.buf
);
624 // msg_fifo.count = NELEMS(msg_fifo.buf);
628 DMA1_CCR4
|= DMA_CCR_EN
;
631 /*--------------------------------------------------------------------------*/
633 void z80_setup_msg_fifo(void)
635 gpio_set_mode(P_BUSACK
, GPIO_MODE_INPUT
,
636 GPIO_CNF_INPUT_FLOAT
, GPIO_BUSACK
| GPIO_IOCS1
);
643 void z80_init_msg_fifo(uint32_t addr
)
646 DBG_P(1, "z80_init_msg_fifo: %lx\n", addr
);
649 z80_write(addr
+FIFO_INDEX_OUT
, z80_read(addr
+FIFO_INDEX_IN
));
651 msg_fifo
.base
= addr
;
655 int z80_msg_fifo_getc(void)
659 if (msg_fifo
.count
!= (NELEMS(msg_fifo
.buf
) - DMA1_CNDTR4
)) {
660 c
= msg_fifo
.buf
[msg_fifo
.count
];
661 if (++msg_fifo
.count
== NELEMS(msg_fifo
.buf
))
664 if (msg_fifo
.base
!= 0) {
666 z80_write(msg_fifo
.base
+FIFO_INDEX_OUT
, msg_fifo
.count
);