2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 * | Z180-Sig | STM32-Port |Buffer | Dir | Special Function |
12 * +------------+---------------+-------+-------+-----------------------+
13 * | A0 | A 1 | P | O | |
14 * | A1 | A 2 | P | O | |
15 * | A2 | A 3 | P | O | |
16 * | A3 | A 4 | P | O | |
17 * | A4 | A 5 | P | O | |
18 * | A5 | A 6 | P | O | |
19 * | A6 | A 7 | P | O | |
20 * | A7 | A 8 | | O | |
21 * | A8 | C 0 | P | O | |
22 * | A9 | C 1 | P | O | |
23 * | A10 | C 2 | P | O | |
24 * | A11 | C 3 | P | O | |
25 * | A12 | C 4 | P | O | |
26 * | A13 | C 5 | P | O | |
27 * | A14 | C 6 | | O | |
28 * | A15 | C 7 | | O | |
29 * | A16 | C 10 | | O | |
30 * | A17 | C 11 | | O | |
31 * | A18 | C 12 | | O | |
32 * | D0 | B 8 | | I/O | |
33 * | D1 | B 9 | | I/O | |
34 * | D2 | B 10 | | I/O | |
35 * | D3 | B 11 | | I/O | |
36 * | D4 | B 12 | | I/O | |
37 * | D5 | B 13 | | I/O | |
38 * | D6 | B 14 | | I/O | |
39 * | D7 | B 15 | | I/O | |
40 * | ME | C 13 | P | O | |
41 * | RD | B 0 | P | O | |
42 * | WR | B 1 | P | O | |
43 * | BUSREQ | D 2 | | O | |
44 * | IOCS1 | A 11 | | I | TIM1_CH4 |
45 * | BUSACK | A 12 | | I | |
46 * | HALT | A 12 | | I | |
47 * | NMI | B 7 | | O | |
48 * | RST | B 6 | | O | TIM16_CH1N |
50 * | | A 9 | | | af1 USART1_TX |
51 * | | A 10 | | | af1 USART1_RX |
52 * | | A 15 | | JTDI | remap SPI1_NSS' |
53 * | | B 3 | | JTDO | remap SPI1_SCK' |
54 * | | B 4 | |NJTRST | remap SPI1_MISO' |
55 * | | B 5 | | | remap SPI1_MOSI' |
56 * | | C 14 | | | af1 OSC32 |
57 * | | C 15 | | | af1 OSC32 |
61 AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees
70 * | Z180-Sig | STM32-Port | Buffer | Dir |Special Function |
71 * | -------- | ---------- | ------ | --- | --------------- |
82 * | A10 |C 2 |P |O | |
83 * | A11 |C 3 |P |O | |
84 * | A12 |C 4 |P |O | |
85 * | A13 |C 5 |P |O | |
88 * | A16 |C 10 | |O | |
89 * | A17 |C 11 | |O | |
90 * | A18 |C 12 | |O | |
91 * | D0 |B 8 | |I/O | |
92 * | D1 |B 9 | |I/O | |
93 * | D2 |B 10 | |I/O | |
94 * | D3 |B 11 | |I/O | |
95 * | D4 |B 12 | |I/O | |
96 * | D5 |B 13 | |I/O | |
97 * | D6 |B 14 | |I/O | |
98 * | D7 |B 15 | |I/O | |
99 * | ME |C 13 |P |O | |
100 * | RD |B 0 |P |O | |
101 * | WR |B 1 |P |O | |
102 * | BUSREQ |D 2 | |O | |
103 * | IOCS1 |A 11 | |I |TIM1_CH4 |
104 * | BUSACK |A 12 | |I | |
105 * | HALT |A 12 | |I | |
106 * | NMI |B 7 | |O | |
107 * | RST |B 6 | |O |TIM16_CH1N |
109 * | |A 9 | | |af1 USART1_TX |
110 * | |A 10 | | |af1 USART1_RX |
111 * | |A 15 | |JTDI | remap SPI1_NSS' |
112 * | |B 3 | |JTDO |remap SPI1_SCK' |
113 * | |B 4 | |NJTRST |remap SPI1_MISO' |
114 * | |B 5 | | |remap SPI1_MOSI' |
115 * | |C 14 | | |af1 OSC32 |
116 * | |C 15 | | |af1 OSC32 |
120 AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees
128 #include <libopencm3/stm32/gpio.h>
129 #include <libopencm3/stm32/rcc.h>
130 #include <libopencm3/stm32/timer.h>
131 #include <libopencm3/stm32/dma.h>
136 /* Number of array elements */
137 #define NELEMS(x) (sizeof x/sizeof *x)
142 #define CONCAT(x,y) x ## y
143 #define EVALUATOR(x,y) CONCAT(x,y)
145 #define GPIO_(X) CONCAT(GPIO, X)
156 #define P_BUSREQ GPIOD
158 #define P_BUSACK GPIOA
160 //#define P_HALT GPIOA
162 #define P_IOCS1 GPIOA
172 #define ADp1_PORT GPIOA
174 #define ADp2_OFS ADp1_WIDTH
177 #define ADp2_PORT GPIOC
179 #define ADp3_OFS (ADp2_OFS+ADp2_WIDTH)
181 #define ADp3_SHIFT 10
182 #define ADp3_PORT GPIOC
184 #define ADunbuff1_WIDTH 1
185 #define ADunbuff1_SHIFT 8
186 #define ADunbuff1_PORT GPIOA
188 #define ADunbuff2_WIDTH 2
189 #define ADunbuff2_SHIFT 6
190 #define ADunbuff2_PORT GPIOC
192 #define ADunbuff3_WIDTH 3
193 #define ADunbuff3_SHIFT 10
194 #define ADunbuff3_PORT GPIOC
199 #define DB_PORT GPIOB
201 #define GPIO_ME GPIO_(ME)
202 #define GPIO_RD GPIO_(RD)
203 #define GPIO_WR GPIO_(WR)
204 #define GPIO_BUSREQ GPIO_(BUSREQ)
205 #define GPIO_BUSACK GPIO_(BUSACK)
206 //#define GPIO_HALT GPIO_(HALT)
207 #define GPIO_IOCS1 GPIO_(IOCS1)
208 #define GPIO_NMI GPIO_(NMI)
209 #define GPIO_RST GPIO_(RST)
211 #define Z80_O_ME BBIO_PERIPH(P_ME+ODR, ME)
212 #define Z80_O_RD BBIO_PERIPH(P_RD+ODR, RD)
213 #define Z80_O_WR BBIO_PERIPH(P_WR+ODR, WR)
214 #define Z80_O_BUSREQ BBIO_PERIPH(P_BUSREQ+ODR, BUSREQ)
215 #define Z80_O_NMI BBIO_PERIPH(P_NMI+ODR, NMI)
216 #define Z80_O_RST BBIO_PERIPH(P_RST+ODR, RST)
218 #define Z80_I_BUSACK BBIO_PERIPH(P_BUSACK+IDR, BUSACK)
219 //#define Z80_I_HALT BBIO_PERIPH(P_HALT+IDR, HALT)
222 #define MASK(n) ((1<<n)-1)
224 #define IOFIELD_SET(src, ofs, width, shift) \
225 ((((src>>ofs) & MASK(width)) << shift) | ((((~src>>ofs) & MASK(width)) << shift) << 16))
227 #define IOFIELD_GET(src, width, shift) \
228 ((src>>shift) & MASK(width))
230 #define CNF_MODE_I_F (GPIO_CNF_INPUT_FLOAT<<2 |GPIO_MODE_INPUT)
231 #define CNF_MODE_O_PP (GPIO_CNF_OUTPUT_PUSHPULL<<2 | GPIO_MODE_OUTPUT_10_MHZ)
233 #define DB_MODE_INPUT ( (CNF_MODE_I_F << (4 * 0)) \
234 | (CNF_MODE_I_F << (4 * 1)) \
235 | (CNF_MODE_I_F << (4 * 2)) \
236 | (CNF_MODE_I_F << (4 * 3)) \
237 | (CNF_MODE_I_F << (4 * 4)) \
238 | (CNF_MODE_I_F << (4 * 5)) \
239 | (CNF_MODE_I_F << (4 * 6)) \
240 | (CNF_MODE_I_F << (4 * 7)))
242 #define DB_MODE_OUTPUT ( (CNF_MODE_O_PP << (4 * 0)) \
243 | (CNF_MODE_O_PP << (4 * 1)) \
244 | (CNF_MODE_O_PP << (4 * 2)) \
245 | (CNF_MODE_O_PP << (4 * 3)) \
246 | (CNF_MODE_O_PP << (4 * 4)) \
247 | (CNF_MODE_O_PP << (4 * 5)) \
248 | (CNF_MODE_O_PP << (4 * 6)) \
249 | (CNF_MODE_O_PP << (4 * 7)))
252 /*--------------------------------------------------------------------------*/
254 static void tim16_setup(void)
256 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM16RST
;
257 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM16RST
;
259 TIM16_BDTR
= TIM_BDTR_MOE
;
262 | TIM_CCMR1_OC1M_FORCE_LOW
263 | TIM_CCMR1_CC1S_OUT
;
265 TIM16_CCER
= TIM_CCER_CC1NE
268 TIM16_ARR
= 48; /* default */
269 TIM16_CCR1
= 1; /* */
272 /*--------------------------------------------------------------------------*/
274 static void tim16_set(int mode
)
278 cc_mode
= TIM_CCMR1_CC1S_OUT
;
280 TIM16_CR1
= TIM_CR1_OPM
;
283 cc_mode
|= TIM_CCMR1_OC1M_FORCE_LOW
;
285 cc_mode
|= TIM_CCMR1_OC1M_FORCE_HIGH
;
288 cc_mode
|= TIM_CCMR1_OC1M_PWM2
;
291 TIM16_CCMR1
= cc_mode
;
294 TIM16_CR1
|= TIM_CR1_CEN
;
297 /*--------------------------------------------------------------------------*/
302 * A0..A6, A8..A13 are buffered. No need to disable.
303 * A7, A14..A18: set to input.
306 static void z80_setup_adrbus_tristate(void)
309 gpio_set_mode(ADunbuff1_PORT
, GPIO_MODE_INPUT
,
310 GPIO_CNF_INPUT_FLOAT
, MASK(ADunbuff1_WIDTH
) << ADunbuff1_SHIFT
);
311 gpio_set_mode(ADunbuff2_PORT
, GPIO_MODE_INPUT
, GPIO_CNF_INPUT_FLOAT
,
312 (MASK(ADunbuff2_WIDTH
) << ADunbuff2_SHIFT
) | (MASK(ADunbuff3_WIDTH
) << ADunbuff3_SHIFT
));
314 GPIO_CRH(GPIOA
) = (GPIO_CRH(GPIOA
) & ~(0x0f << (4 * 0)))
315 | (CNF_MODE_I_F
<< (4 * 0));
316 GPIO_CRL(GPIOC
) = (GPIO_CRL(GPIOC
) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
317 | ((CNF_MODE_I_F
<< (4 * 6)) | (CNF_MODE_I_F
<< (4 * 7)));
318 GPIO_CRH(GPIOC
) = (GPIO_CRH(GPIOC
) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
319 | ((CNF_MODE_I_F
<< (4*2)) | (CNF_MODE_I_F
<< (4*3)) | (CNF_MODE_I_F
<< (4*4)));
324 static void z80_setup_adrbus_active(void)
327 gpio_set_mode(ADunbuff1_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
328 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADunbuff1_WIDTH
) << ADunbuff1_SHIFT
);
329 gpio_set_mode(ADunbuff2_PORT
, GPIO_MODE_OUTPUT_10_MHZ
, GPIO_CNF_OUTPUT_PUSHPULL
,
330 (MASK(ADunbuff2_WIDTH
) << ADunbuff2_SHIFT
) | (MASK(ADunbuff3_WIDTH
) << ADunbuff3_SHIFT
));
332 GPIO_CRH(GPIOA
) = (GPIO_CRH(GPIOA
) & ~(0x0f << (4 * 0)))
333 | (CNF_MODE_O_PP
<< (4 * 0));
334 GPIO_CRL(GPIOC
) = (GPIO_CRL(GPIOC
) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7))))
335 | ((CNF_MODE_O_PP
<< (4 * 6)) | (CNF_MODE_O_PP
<< (4 * 7)));
336 GPIO_CRH(GPIOC
) = (GPIO_CRH(GPIOC
) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4))))
337 | ((CNF_MODE_O_PP
<< (4*2)) | (CNF_MODE_O_PP
<< (4*3)) | (CNF_MODE_O_PP
<< (4*4)));
342 static void z80_setup_dbus_in(void)
344 GPIO_CRH(DB_PORT
) = DB_MODE_INPUT
;
347 static void z80_setup_dbus_out(void)
349 GPIO_CRH(DB_PORT
) = DB_MODE_OUTPUT
;
353 static void z80_setaddress(uint32_t addr
)
355 GPIO_BSRR(ADp1_PORT
) = IOFIELD_SET(addr
, ADp1_OFS
, ADp1_WIDTH
, ADp1_SHIFT
);
356 GPIO_BSRR(ADp2_PORT
) = IOFIELD_SET(addr
, ADp2_OFS
, ADp2_WIDTH
, ADp2_SHIFT
);
357 GPIO_BSRR(ADp3_PORT
) = IOFIELD_SET(addr
, ADp3_OFS
, ADp3_WIDTH
, ADp3_SHIFT
);
360 void z80_setup_bus(void)
364 gpio_set_mode(P_RST
, GPIO_MODE_OUTPUT_10_MHZ
,
365 GPIO_CNF_OUTPUT_ALTFN_PUSHPULL
, GPIO_RST
);
367 gpio_set_mode(P_BUSREQ
, GPIO_MODE_OUTPUT_10_MHZ
,
368 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_BUSREQ
);
370 gpio_set_mode(P_NMI
, GPIO_MODE_OUTPUT_10_MHZ
,
371 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_NMI
);
375 gpio_set_mode(P_ME
, GPIO_MODE_OUTPUT_2_MHZ
,
376 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_ME
);
377 gpio_set_mode(P_RD
, GPIO_MODE_OUTPUT_10_MHZ
,
378 GPIO_CNF_OUTPUT_PUSHPULL
, GPIO_RD
| GPIO_WR
);
381 //while(Z80_I_BUSACK == 1);
383 gpio_set_mode(ADp1_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
384 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp1_WIDTH
) << ADp1_SHIFT
);
385 gpio_set_mode(ADp2_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
386 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp2_WIDTH
) << ADp2_SHIFT
);
387 gpio_set_mode(ADp3_PORT
, GPIO_MODE_OUTPUT_10_MHZ
,
388 GPIO_CNF_OUTPUT_PUSHPULL
, MASK(ADp3_WIDTH
) << ADp3_SHIFT
);
393 void z80_request_bus(void)
396 while(Z80_I_BUSACK
== 1);
397 z80_setup_adrbus_active();
400 void z80_release_bus(void)
403 z80_setup_adrbus_tristate();
405 while(Z80_I_BUSACK
== 0);
408 void z80_reset(level_t level
)
410 int x
= level
? -1 : 0;
414 // Z80_O_RST = level;
417 void z80_reset_pulse(void)
422 void z80_busreq(level_t level
)
424 Z80_O_BUSREQ
= level
;
428 int z80_stat_halt(void)
434 void z80_write(uint32_t addr
, uint8_t data
)
436 z80_setaddress(addr
);
438 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
439 z80_setup_dbus_out();
445 uint8_t z80_read(uint32_t addr
)
449 z80_setaddress(addr
);
454 data
= IOFIELD_GET(GPIO_IDR(DB_PORT
),DB_WIDTH
, DB_SHIFT
);
462 void z80_memset(uint32_t addr
, uint8_t data
, int length
)
464 z80_setup_dbus_out();
467 z80_setaddress(addr
++);
468 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
475 void z80_write_block(uint8_t *src
, uint32_t dest
, uint32_t length
)
479 z80_setup_dbus_out();
482 z80_setaddress(dest
++);
484 GPIO_BSRR(DB_PORT
) = IOFIELD_SET(data
, DB_OFS
, DB_WIDTH
, DB_SHIFT
);
492 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
493 017A' rx.in_idx: ds 1 ;
494 017B' rx.out_idx: ds 1 ;
495 017C' rx.buf: ds rx.buf_len ;
496 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
498 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
499 018D' tx.in_idx: ds 1 ;
500 018E' tx.out_idx: ds 1 ;
501 018F' tx.buf: ds tx.buf_len ;
502 019E' tx.buf_end equ $-1 ; last byte
506 typedef struct __attribute__((packed
)) {
515 #define FIFO_BUFSIZE_MASK -3
516 #define FIFO_INDEX_IN -2
517 #define FIFO_INDEX_OUT -1
525 } fifo_dsc
[NUM_FIFOS
];
528 void z80_memfifo_init(const fifo_t f
, uint32_t adr
)
531 DBG_P(2, "z80_memfifo_init: %i, %lx\n", f
, adr
);
533 fifo_dsc
[f
].base
= adr
;
537 fifo_dsc
[f
].mask
= z80_read(adr
+ FIFO_BUFSIZE_MASK
);
538 fifo_dsc
[f
].idx_in
= z80_read(adr
+ FIFO_INDEX_IN
);
539 fifo_dsc
[f
].idx_out
= z80_read(adr
+ FIFO_INDEX_OUT
);
545 int z80_memfifo_is_empty(const fifo_t f
)
549 if (fifo_dsc
[f
].base
!= 0) {
551 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
557 rc
= idx
== fifo_dsc
[f
].idx_out
;
563 int z80_memfifo_is_full(const fifo_t f
)
567 if (fifo_dsc
[f
].base
!= 0) {
569 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
570 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
576 uint8_t z80_memfifo_getc(const fifo_t f
)
580 while (z80_memfifo_is_empty(f
))
584 idx
= fifo_dsc
[f
].idx_out
;
585 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
586 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
587 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
594 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
598 while (z80_memfifo_is_full(f
))
602 idx
= fifo_dsc
[f
].idx_in
;
603 z80_write(fifo_dsc
[f
].base
+idx
, val
);
604 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
605 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
609 /*--------------------------------------------------------------------------*/
613 //uint8_t idx_out, idx_in;
618 /*--------------------------------------------------------------------------*/
622 static void tim1_setup(void)
624 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM1RST
;
625 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM1RST
;
631 /* | TIM_SMCR_ETF_CK_INT_N_2 */
636 TIM1_DIER
= TIM_DIER_TDE
;
640 | TIM_CCMR1_OC1M_FORCE_LOW
641 | TIM_CCMR1_CC1S_OUT
;
643 TIM1_SMCR
|= TIM_SMCR_SMS_TM
;
648 /*--------------------------------------------------------------------------*/
650 static void tim1_ch4_setup(void)
653 RCC_APB2RSTR
|= RCC_APB2RSTR_TIM1RST
;
654 RCC_APB2RSTR
&= ~RCC_APB2RSTR_TIM1RST
;
657 | TIM_CCMR2_CC4S_IN_TI2
659 | TIM_CCMR2_IC4PSC_OFF
;
662 /* | TIM_CCER_CC4P */
665 /* Enable DMA for channel 4 */
666 TIM1_DIER
= TIM_DIER_CC4DE
;
669 /*--------------------------------------------------------------------------*/
671 static void dma1_ch4_setup(void)
680 DMA1_CMAR4
= (uint32_t) msg_fifo
.buf
;
682 #if (DB_SHIFT == 0) || (DB_SHIFT == 8)
683 DMA1_CPAR4
= DB_PORT
+ IDR
+ DB_SHIFT
/8;
685 #error "Databus not byte aligned!"
688 DMA1_CNDTR4
= NELEMS(msg_fifo
.buf
);
689 // msg_fifo.count = NELEMS(msg_fifo.buf);
693 DMA1_CCR4
|= DMA_CCR_EN
;
696 /*--------------------------------------------------------------------------*/
698 void z80_setup_msg_fifo(void)
700 gpio_set_mode(P_BUSACK
, GPIO_MODE_INPUT
,
701 GPIO_CNF_INPUT_FLOAT
, GPIO_BUSACK
| GPIO_IOCS1
);
708 void z80_init_msg_fifo(uint32_t addr
)
711 DBG_P(1, "z80_init_msg_fifo: %lx\n", addr
);
714 z80_write(addr
+FIFO_INDEX_OUT
, z80_read(addr
+FIFO_INDEX_IN
));
716 msg_fifo
.base
= addr
;
720 int z80_msg_fifo_getc(void)
724 if (msg_fifo
.count
!= (NELEMS(msg_fifo
.buf
) - DMA1_CNDTR4
)) {
725 c
= msg_fifo
.buf
[msg_fifo
.count
];
726 if (++msg_fifo
.count
== NELEMS(msg_fifo
.buf
))
729 if (msg_fifo
.base
!= 0) {
731 z80_write(msg_fifo
.base
+FIFO_INDEX_OUT
, msg_fifo
.count
);