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1 /*
2 */
3
4 #include "common.h"
5 //#include <avr/power.h>
6 //#include <avr/pgmspace.h>
7 //#include <util/atomic.h>
8 //#include <avr/sleep.h>
9 //#include <string.h>
10
11
12 #include "debug.h"
13 #include "serial.h"
14 #include "z80-if.h"
15
16
17 /* ugly hack to get Z180 loadfile into flash memory */
18 #define const const FLASH
19 #include "../z180/hdrom.h"
20 #undef const
21
22
23 /*--------------------------------------------------------------------------*/
24
25 uint32_t z80_sram_cmp(uint32_t addr, uint32_t length, uint8_t wval, int inc)
26 {
27 uint8_t rval;
28 int_fast8_t errors = 0;
29
30 DBG_P(1, "SRAM: Check 0x%.5lx byte... ", length);
31 while (length--) {
32 if ((rval = z80_read(addr)) != wval) {
33 if (errors == 0) {
34 DBG_P(1, "\nSRAM: Address W R\n" \
35 " ------------------\n");
36 }
37 errors++;
38 if (errors > 20) {
39 DBG_P(1, " ...\n");
40 break;
41 }
42 DBG_P(1, " 0x%.5lx 0x%.2x 0x%.2x\n", addr, wval, rval);
43 }
44 addr++;
45 wval += inc;
46 }
47 DBG_P(1, "Done.\n");
48
49 return addr;
50 }
51
52 void z80_sram_fill(uint32_t addr, uint32_t length, uint8_t startval, int inc)
53 {
54 printf("SRAM: Write 0x%.5lx byte... ", length);
55 while (length--) {
56 z80_write(addr, startval);
57 ++addr;
58 startval += inc;
59 }
60 printf("Done.\n");
61 }
62
63
64 #if 0
65 void z80_sram_fill_string(uint32_t addr, int length, const char *text)
66 {
67 char c;
68 const char *p = text;
69
70 while (length--) {
71 z80_write(addr++, c = *p++);
72 if (c == 0)
73 p = text;
74 }
75 }
76
77
78 uint32_t z80_sram_cmp_string(uint32_t addr, int length, const char *text)
79 {
80 char c;
81 const char *p = text;
82
83 while (length--) {
84 c = *p++;
85 if (z80_read(addr) != c)
86 break;
87 ++addr;
88 if (c == 0)
89 p = text;
90 }
91 return addr;
92 }
93
94 const char * const qbfox = "Zhe quick brown fox jumps over the lazy dog!";
95 const char * const qbcat = "Zhe quick brown fox jumps over the lazy cat!";
96
97 #endif
98
99 uint8_t z80_get_byte(uint32_t adr)
100 {
101 uint8_t data;
102
103 z80_request_bus();
104 data = z80_read(adr),
105 z80_release_bus();
106
107 return data;
108 }
109
110
111 /*--------------------------------------------------------------------------*/
112
113 struct msg_item {
114 uint8_t fct;
115 uint8_t sub_min, sub_max;
116 void (*func)(uint8_t, int, uint8_t *);
117 };
118
119 uint32_t msg_to_addr(uint8_t *msg)
120 {
121 union {
122 uint32_t as32;
123 uint8_t as8[4];
124 } addr;
125
126 addr.as8[0] = msg[0];
127 addr.as8[1] = msg[1];
128 addr.as8[2] = msg[2];
129 addr.as8[3] = 0;
130
131 return addr.as32;
132 }
133
134 void do_msg_ini_msgfifo(uint8_t subf, int len, uint8_t * msg)
135 {
136 (void)subf; (void)len;
137
138 z80_init_msg_fifo(msg_to_addr(msg));
139 }
140
141
142 void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
143 {
144 (void)len;
145
146 z80_memfifo_init(subf - 1, msg_to_addr(msg));
147 }
148
149
150 void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
151 {
152 (void)subf;
153
154 while (len--)
155 putchar(*msg++);
156 }
157
158
159 const FLASH struct msg_item z80_messages[] =
160 {
161 { 0, /* fct nr. */
162 0, 0, /* sub fct nr. from, to */
163 do_msg_ini_msgfifo},
164 { 0,
165 1, 2,
166 do_msg_ini_memfifo},
167 { 1,
168 1, 1,
169 do_msg_char_out},
170 { 0xff, /* end mark */
171 0, 0,
172 0},
173
174 };
175
176
177
178
179 void do_message(int len, uint8_t *msg)
180 {
181 uint8_t fct, sub_fct;
182 int_fast8_t i = 0;
183
184 if (len >= 2) {
185 fct = *msg++;
186 sub_fct = *msg++;
187 len -= 2;
188
189 while (fct != z80_messages[i].fct)
190 ++i;
191
192 if (z80_messages[i].fct == 0xff) {
193 DBG_P(1, "do_message: Unknown function: %i, %i\n",
194 fct, sub_fct);
195 return; /* TODO: unknown message # */
196 }
197
198 while (fct == z80_messages[i].fct) {
199 if (sub_fct >= z80_messages[i].sub_min && sub_fct <= z80_messages[i].sub_max )
200 break;
201 ++i;
202 }
203
204 if (z80_messages[i].fct != fct) {
205 DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
206 fct, sub_fct);
207 return; /* TODO: unknown message sub# */
208 }
209
210 (z80_messages[i].func)(sub_fct, len, msg);
211
212
213 } else {
214 /* TODO: error */
215 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
216 }
217 }
218
219
220
221 #define CTRBUF_LEN 256
222
223 void check_msg_fifo(void)
224 {
225 int ch;
226 static int_fast8_t state;
227 static int msglen,idx;
228 static uint8_t buffer[CTRBUF_LEN];
229
230 while (state != 3 && (ch = z80_msg_fifo_getc()) >= 0) {
231 switch (state) {
232 case 0: /* wait for start of message */
233 if (ch == 0x81) {
234 msglen = 0;
235 idx = 0;
236 state = 1;
237 }
238 break;
239 case 1: /* get msg len */
240 if (ch > 0 && ch <= CTRBUF_LEN) {
241 msglen = ch;
242 state = 2;
243 } else
244 state = 0;
245 break;
246 case 2: /* get message */
247 buffer[idx++] = ch;
248 if (idx == msglen)
249 state = 3;
250 break;
251 }
252 }
253
254 if (state == 3) {
255 do_message(msglen, buffer);
256 state = 0;
257 }
258 }
259
260
261 /*--------------------------------------------------------------------------*/
262
263 void dump_mem(const FLASH uint8_t *addr, uint32_t len)
264 {
265 DBG_P(1, "hdrom dump:");
266 while (len) {
267 DBG_P(1, "\n %.5x:", addr);
268 for (unsigned i = 0; i<16; i++)
269 DBG_P(1, " %.2x", *addr++);
270 len -= len > 16 ? 16 : len;
271 }
272 DBG_P(1, "\n");
273 }
274
275 /*--------------------------------------------------------------------------*/
276
277 void z80_load_mem(void)
278 {
279 unsigned sec = 0;
280 uint32_t sec_base = hdrom_start;
281
282 DBG_P(1, "Loading z80 memory... \n");
283
284 while (sec < hdrom_sections) {
285 DBG_P(2, " From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n",
286 hdrom_address[sec],
287 hdrom_address[sec]+hdrom_length_of_sections[sec] - 1,
288 hdrom_length_of_sections[sec]);
289
290 z80_write_block((const FLASH unsigned char *) &hdrom[sec_base], /* src */
291 hdrom_address[sec], /* dest */
292 hdrom_length_of_sections[sec]); /* len */
293 sec_base+=hdrom_length_of_sections[sec];
294 sec++;
295 }
296 }
297
298 /*--------------------------------------------------------------------------*/
299
300
301 const FLASH uint8_t iniprog[] = {
302 0xAF, // xor a
303 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
304 0x3E, 0x30, // ld a,030h
305 0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states
306 };
307
308 const FLASH uint8_t sertest[] = {
309 0xAF, // xor a
310 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
311 0x3E, 0x30, // ld a,030h
312 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
313 0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0
314 0xED, 0x39, 0x03, // out0 (cntlb1),a
315 0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ;
316 0xED, 0x39, 0x01, // out0 (cntla1),a
317 0x3E, 0x00, // ld a,0
318 0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts
319 0xED, 0x38, 0x05, //l0:in0 a,(stat1)
320 0xE6, 0x80, // and 80h
321 0x28, 0xF9, // jr z,l0
322 0xED, 0x00, 0x09, // in0 b,(rdr1)
323 0xED, 0x38, 0x05, //l1:in0 a,(stat1)
324 0xE6, 0x02, // and 02h
325 0x28, 0xF9, // jr z,l1
326 0xED, 0x01, 0x07, // out0 (tdr1),b
327 0x18, 0xEA, // jr l0
328 };
329
330 const FLASH uint8_t test1[] = {
331 0xAF, // xor a
332 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
333 0x3E, 0x30, // ld a,030h
334 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
335 0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers
336 0x06, 0x08, // ld b,dmct_e-dmclrt
337 0x0E, 0x20, // ld c,sar0l
338 0xED, 0x93, // otimr
339 0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst
340 0xED, 0x39, 0x31, // out0 (dmode),a ;
341 0x3E, 0x62, // ld a,062h ;enable dma0,
342 0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k
343 0x18, 0xFB, // jr cl_1 ;
344 0x00, 0x00, //dmclrt: dw 0 ;src (inc)
345 0x00, // db 0 ;src
346 0x00, 0x00, // dw 0 ;dst (inc),
347 0x00, // db 0 ;dst
348 0x00, 0x00, // dw 0 ;count (64k)
349 };
350
351
352
353 // check_msg_fifo();
354