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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
4 * SPDX-License-Identifier: GPL-2.0
11 * | Z180-Sig | AVR-Port | Dir |
12 * +------------+---------------+-------+
44 * | BUSREQ | PD 7 | O |
45 * | BUSACK | PD 6 | I |
48 * +------------------------------------+
57 #include <util/atomic.h>
63 //#define P_ZCLK PORTB
65 //#define DDR_ZCLK DDRB
73 #define P_BUSREQ PORTD
75 #define DDR_BUSREQ DDRD
76 #define P_BUSACK PORTD
77 #define PIN_BUSACK PIND
79 #define DDR_BUSACK DDRD
100 //#define ADB_PORT PORTE
103 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
104 #define Z80_O_MREQ SBIT(P_MREQ, 4)
105 #define Z80_O_RD SBIT(P_RD, 3)
106 #define Z80_O_WR SBIT(P_WR, 2)
107 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
108 //#define Z80_O_NMI SBIT(P_NMI, )
109 #define Z80_O_RST SBIT(P_RST, 5)
110 #define Z80_I_RST SBIT(PIN_RST, 5)
111 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
112 //#define Z80_I_HALT SBIT(P_HALT, )
120 #define DDR_STEP DDRG
123 #define DDR_WAIT DDRG
124 /* All three signals are on the same Port (PortG) */
125 #define PORT_SS PORTG
128 #define Z80_O_RUN SBIT(PORT_SS, RUN)
129 #define Z80_O_STEP SBIT(PORT_SS, STEP)
130 #define Z80_I_WAIT SBIT(PORT_SS, WAIT)
136 #define MASK(n) ((1<<(n))-1)
137 #define SMASK(w,s) (MASK(w) << (s))
139 void z80_bus_request_or_exit(void)
141 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
))
142 cmd_error(CMD_RET_FAILURE
, EBUSTO
, NULL
);
145 static zstate_t zstate
;
146 static volatile uint8_t timer
; /* used for bus timeout */
148 /*---------------------------------------------------------*/
149 /* 10Hz timer interrupt generated by OC5A */
150 /*---------------------------------------------------------*/
152 ISR(TIMER5_COMPA_vect
)
161 /*--------------------------------------------------------------------------*/
164 static void z80_addrbus_set_in(void)
166 /* /MREQ, /RD, /WR: Input, no pullup */
167 DDR_MREQ
&= ~(_BV(MREQ
) | _BV(RD
) | _BV(WR
));
176 PIN_ADB
= P_ADB
& (MASK(ADB_WIDTH
) << ADB_SHIFT
);
177 DDR_ADB
= DDR_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
181 static void z80_addrbus_set_out(void)
183 /* /MREQ, /RD, /WR: Output and high */
187 DDR_MREQ
|= _BV(MREQ
) | _BV(RD
) | _BV(WR
);
191 DDR_ADB
= DDR_ADB
| (MASK(ADB_WIDTH
) << ADB_SHIFT
);
195 static void z80_dbus_set_in(void)
202 static void z80_dbus_set_out(void)
207 static void z80_reset_active(void)
209 if (Stat
& S_RESET_POLARITY
)
215 static void z80_reset_inactive(void)
217 if (Stat
& S_RESET_POLARITY
)
223 static void z80_reset_pulse(void)
227 z80_reset_inactive();
231 void z80_setup_bus(void)
233 ATOMIC_BLOCK(ATOMIC_RESTORESTATE
) {
235 /* /ZRESET: Input, no pullup */
236 DDR_RST
&= ~_BV(RST
);
239 /* /BUSREQ: Output and high */
241 DDR_BUSREQ
|= _BV(BUSREQ
);
243 /* /BUSACK: Input, no pullup */
244 DDR_BUSACK
&= ~_BV(BUSACK
);
245 P_BUSACK
&= ~_BV(BUSACK
);
247 z80_addrbus_set_in();
250 if (getenv_yesno(PSTR(ENV_SINGLESTEP
))) {
251 /* /RUN & /STEP: output, /WAIT: input */
253 PORT_SS
= (PORT_SS
& ~_BV(RUN
)) | _BV(STEP
);
254 DDR_SS
= (DDR_SS
& ~_BV(WAIT
)) | _BV(RUN
) | _BV(STEP
);
258 Stat
|= S_RESET_POLARITY
;
260 Stat
&= ~S_RESET_POLARITY
;
268 PRR1
&= ~_BV(PRTIM5
);
269 OCR5A
= F_CPU
/ 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
270 TCCR5B
= (0b01<<WGM52
)|(0b101<<CS40
); /* CTC Mode, Prescaler 1024 */
271 TIMSK5
= _BV(OCIE5A
); /* Enable oca interrupt */
276 zstate_t
z80_bus_state(void)
282 static void z80_busreq_hpulse(void)
285 z80_addrbus_set_in();
288 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
290 Z80_O_BUSREQ
= 1; /* 2 AVR clock cycles */
291 Z80_O_BUSREQ
= 0; /* 2 AVR clock cycles */
296 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
300 if (Z80_I_BUSACK
== 1) {
308 if (zstate
& ZST_ACQUIRED
) {
310 while (Z80_I_BUSACK
== 1 && timer
)
312 if (Z80_I_BUSACK
== 0)
313 z80_addrbus_set_out();
321 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
325 ----------------+---------------+---------------+---------------+---------------+
327 Reset | 0 | 0 | 0 | 0 |
330 Request | 1 | | 3 | |
333 Release | | 0 | | 2 |
339 Restart | | | 2 | 3 |
347 zstate_t
z80_bus_cmd(bus_cmd_t cmd
)
353 z80_addrbus_set_in();
357 while (Z80_I_BUSACK
== 0 && timer
)
366 z80_reset_inactive();
368 while (Z80_I_BUSACK
== 1 && timer
)
370 if (Z80_I_BUSACK
== 0) {
371 z80_addrbus_set_out();
382 while (Z80_I_BUSACK
== 1 && timer
)
384 if (Z80_I_BUSACK
== 0) {
385 z80_addrbus_set_out();
386 zstate
= RUNNING_AQRD
;
401 z80_addrbus_set_in();
405 while (Z80_I_BUSACK
== 0 && timer
)
411 z80_addrbus_set_in();
414 while (Z80_I_BUSACK
== 0 && timer
)
426 _delay_ms(20); /* TODO: */
427 z80_reset_inactive();
433 z80_addrbus_set_in();
435 z80_addrbus_set_out();
436 zstate
= RUNNING_AQRD
;
457 z80_busreq_hpulse(); /* TODO: */
467 /*--------------------------------------------------------------------------*/
470 //inline __attribute__ ((always_inline))
471 void z80_setaddress(uint32_t addr
)
474 P_ADH
= (addr
& 0xff00) >> 8;
475 PIN_ADB
= (((addr
>> 16) << ADB_SHIFT
) ^ P_ADB
) & MASK(ADB_WIDTH
) << ADB_SHIFT
;
478 int32_t z80_memsize_detect(void)
480 const uint8_t PATTERN_1
= 0x55;
481 const uint8_t PATTERN_2
= ~PATTERN_1
;
484 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
))
487 uint8_t ram_0
= z80_read(0);
488 uint8_t ram_1
= z80_read(1);
490 z80_write(0, ram_0
^ 0xff);
492 if ((z80_read(0) ^ ram_0
) != 0xff) {
495 z80_write(0, PATTERN_1
);
496 for (addr
=1; addr
< CONFIG_SYS_RAMSIZE_MAX
; addr
<<= 1) {
497 uint8_t ram_i
= z80_read(addr
);
498 z80_write(addr
, PATTERN_2
);
499 if (z80_read(0) != PATTERN_1
|| z80_read(addr
) != PATTERN_2
)
501 z80_write(addr
, ram_i
);
506 z80_bus_cmd(Release
);
511 /*--------------------------------------------------------------------------*/
513 void z80_write(uint32_t addr
, uint8_t data
)
515 z80_setaddress(addr
);
526 uint8_t z80_read(uint32_t addr
)
530 z80_setaddress(addr
);
544 void z80_memset(uint32_t addr
, uint8_t data
, uint32_t length
)
550 z80_setaddress(addr
++);
558 void z80_write_block_P(const FLASH
uint8_t *src
, uint32_t dest
, uint32_t length
)
565 z80_setaddress(dest
++);
576 void z80_write_block(const uint8_t *src
, uint32_t dest
, uint32_t length
)
583 z80_setaddress(dest
++);
594 void z80_read_block (uint8_t *dest
, uint32_t src
, size_t length
)
601 z80_setaddress(src
++);
612 /*--------------------------------------------------------------------------*/
615 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
616 017A' rx.in_idx: ds 1 ;
617 017B' rx.out_idx: ds 1 ;
618 017C' rx.buf: ds rx.buf_len ;
619 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
621 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
622 018D' tx.in_idx: ds 1 ;
623 018E' tx.out_idx: ds 1 ;
624 018F' tx.buf: ds tx.buf_len ;
625 019E' tx.buf_end equ $-1 ; last byte
629 typedef struct __attribute__((packed
)) {
638 #define FIFO_BUFSIZE_MASK -3
639 #define FIFO_INDEX_IN -2
640 #define FIFO_INDEX_OUT -1
648 } fifo_dsc
[NUM_FIFOS
];
651 void z80_memfifo_init(const fifo_t f
, uint32_t addr
)
653 fifo_dsc
[f
].base
= addr
;
657 z80_bus_cmd(Request
);
658 fifo_dsc
[f
].mask
= z80_read(addr
+ FIFO_BUFSIZE_MASK
);
659 fifo_dsc
[f
].idx_in
= z80_read(addr
+ FIFO_INDEX_IN
);
660 fifo_dsc
[f
].idx_out
= z80_read(addr
+ FIFO_INDEX_OUT
);
661 z80_bus_cmd(Release
);
663 if (fifo_dsc
[f
].idx_in
!= 0 || fifo_dsc
[f
].idx_out
!= 0) {
664 DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
665 f
, addr
, fifo_dsc
[f
].idx_in
, fifo_dsc
[f
].idx_out
, fifo_dsc
[f
].mask
);
671 int z80_memfifo_is_empty(const fifo_t f
)
675 if (fifo_dsc
[f
].base
!= 0) {
677 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
680 z80_bus_cmd(Request
);
682 z80_bus_cmd(Release
);
683 rc
= idx
== fifo_dsc
[f
].idx_out
;
689 int z80_memfifo_is_full(const fifo_t f
)
693 if (fifo_dsc
[f
].base
!= 0) {
694 z80_bus_cmd(Request
);
695 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
696 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
697 z80_bus_cmd(Release
);
703 uint8_t z80_memfifo_getc_wait(const fifo_t f
)
707 while (z80_memfifo_is_empty(f
))
710 z80_bus_cmd(Request
);
711 idx
= fifo_dsc
[f
].idx_out
;
712 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
713 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
714 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
715 z80_bus_cmd(Release
);
720 int z80_memfifo_getc(const fifo_t f
)
724 if (fifo_dsc
[f
].base
!= 0) {
725 uint8_t idx
= fifo_dsc
[f
].idx_out
;
726 z80_bus_cmd(Request
);
727 if (idx
!= z80_read(fifo_dsc
[f
].base
+ FIFO_INDEX_IN
)) {
728 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
729 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
730 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
732 z80_bus_cmd(Release
);
739 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
743 while (z80_memfifo_is_full(f
))
746 z80_bus_cmd(Request
);
747 idx
= fifo_dsc
[f
].idx_in
;
748 z80_write(fifo_dsc
[f
].base
+idx
, val
);
749 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
750 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
751 z80_bus_cmd(Release
);
754 /*--------------------------------------------------------------------------*/
756 void z80_load_mem(int_fast8_t verbosity
,
757 const FLASH
unsigned char data
[],
758 const FLASH
unsigned long *sections
,
759 const FLASH
unsigned long address
[],
760 const FLASH
unsigned long length_of_sections
[])
762 uint32_t sec_base
= 0;
765 printf_P(PSTR("Loading Z180 memory... \n"));
767 for (unsigned sec
= 0; sec
< *sections
; sec
++) {
769 printf_P(PSTR(" From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n"),
771 address
[sec
]+length_of_sections
[sec
] - 1,
772 length_of_sections
[sec
]);
775 z80_write_block_P((const FLASH
unsigned char *) &data
[sec_base
], /* src */
776 address
[sec
], /* dest */
777 length_of_sections
[sec
]); /* len */
778 sec_base
+= length_of_sections
[sec
];