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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
4 * SPDX-License-Identifier: GPL-2.0
11 * | Z180-Sig | AVR-Port | Dir |
12 * +------------+---------------+-------+
44 * | BUSREQ | PD 7 | O |
45 * | BUSACK | PD 6 | I |
48 * +------------------------------------+
57 #include <util/atomic.h>
63 //#define P_ZCLK PORTB
65 //#define DDR_ZCLK DDRB
73 #define P_BUSREQ PORTD
75 #define DDR_BUSREQ DDRD
76 #define P_BUSACK PORTD
77 #define PIN_BUSACK PIND
79 #define DDR_BUSACK DDRD
100 //#define ADB_PORT PORTE
103 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
104 #define Z80_O_MREQ SBIT(P_MREQ, 4)
105 #define Z80_O_RD SBIT(P_RD, 3)
106 #define Z80_O_WR SBIT(P_WR, 2)
107 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
108 //#define Z80_O_NMI SBIT(P_NMI, )
109 #define Z80_O_RST SBIT(P_RST, 5)
110 #define Z80_I_RST SBIT(PIN_RST, 5)
111 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
112 //#define Z80_I_HALT SBIT(P_HALT, )
120 #define DDR_STEP DDRG
123 #define DDR_WAIT DDRG
124 /* All three signals are on the same Port (PortG) */
125 #define PORT_SS PORTG
128 #define Z80_O_RUN SBIT(PORT_SS, RUN)
129 #define Z80_O_STEP SBIT(PORT_SS, STEP)
130 #define Z80_I_WAIT SBIT(PORT_SS, WAIT)
136 #define MASK(n) ((1<<(n))-1)
137 #define SMASK(w,s) (MASK(w) << (s))
140 static zstate_t zstate
;
141 static volatile uint8_t timer
; /* used for bus timeout */
142 static bool reset_polarity
;
144 /*---------------------------------------------------------*/
145 /* 10Hz timer interrupt generated by OC4A */
146 /*---------------------------------------------------------*/
148 ISR(TIMER5_COMPA_vect
)
157 /*--------------------------------------------------------------------------*/
160 static void z80_addrbus_set_in(void)
162 /* /MREQ, /RD, /WR: Input, no pullup */
163 DDR_MREQ
&= ~(_BV(MREQ
) | _BV(RD
) | _BV(WR
));
172 PIN_ADB
= P_ADB
& (MASK(ADB_WIDTH
) << ADB_SHIFT
);
173 DDR_ADB
= DDR_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
177 static void z80_addrbus_set_out(void)
179 /* /MREQ, /RD, /WR: Output and high */
183 DDR_MREQ
|= _BV(MREQ
) | _BV(RD
) | _BV(WR
);
187 DDR_ADB
= DDR_ADB
| (MASK(ADB_WIDTH
) << ADB_SHIFT
);
191 static void z80_dbus_set_in(void)
198 static void z80_dbus_set_out(void)
203 static void z80_reset_active(void)
211 static void z80_reset_inactive(void)
219 static void z80_reset_pulse(void)
223 z80_reset_inactive();
227 void z80_setup_bus(void)
229 ATOMIC_BLOCK(ATOMIC_RESTORESTATE
) {
231 /* /ZRESET: Input, no pullup */
232 DDR_RST
&= ~_BV(RST
);
235 /* /BUSREQ: Output and high */
237 DDR_BUSREQ
|= _BV(BUSREQ
);
239 /* /BUSACK: Input, no pullup */
240 DDR_BUSACK
&= ~_BV(BUSACK
);
241 P_BUSACK
&= ~_BV(BUSACK
);
243 z80_addrbus_set_in();
246 if (getenv_yesno(PSTR(ENV_SINGLESTEP
))) {
247 /* /RUN & /STEP: output, /WAIT: input */
249 PORT_SS
= (PORT_SS
& ~_BV(RUN
)) | _BV(STEP
);
250 DDR_SS
= (DDR_SS
& ~_BV(WAIT
)) | _BV(RUN
) | _BV(STEP
);
253 reset_polarity
= Z80_I_RST
;
261 PRR1
&= ~_BV(PRTIM5
);
262 OCR5A
= F_CPU
/ 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
263 TCCR5B
= (0b01<<WGM52
)|(0b101<<CS40
); /* CTC Mode, Prescaler 1024 */
264 TIMSK5
= _BV(OCIE5A
); /* Enable oca interrupt */
269 zstate_t
z80_bus_state(void)
275 static void z80_busreq_hpulse(void)
278 z80_addrbus_set_in();
281 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
283 Z80_O_BUSREQ
= 1; /* 2 AVR clock cycles */
284 Z80_O_BUSREQ
= 0; /* 2 AVR clock cycles */
289 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
293 if (Z80_I_BUSACK
== 1) {
301 if (zstate
& ZST_ACQUIRED
) {
303 while (Z80_I_BUSACK
== 1 && timer
)
305 if (Z80_I_BUSACK
== 0)
306 z80_addrbus_set_out();
314 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
318 ----------------+---------------+---------------+---------------+---------------+
320 Reset | 0 | 0 | 0 | 0 |
323 Request | 1 | | 3 | |
326 Release | | 0 | | 2 |
332 Restart | | | 2 | 3 |
340 zstate_t
z80_bus_cmd(bus_cmd_t cmd
)
346 z80_addrbus_set_in();
356 z80_reset_inactive();
358 while (Z80_I_BUSACK
== 1 && timer
)
360 if (Z80_I_BUSACK
== 0) {
361 z80_addrbus_set_out();
372 while (Z80_I_BUSACK
== 1 && timer
)
374 if (Z80_I_BUSACK
== 0) {
375 z80_addrbus_set_out();
376 zstate
= RUNNING_AQRD
;
391 z80_addrbus_set_in();
398 z80_addrbus_set_in();
410 z80_reset_inactive();
416 z80_addrbus_set_in();
418 z80_addrbus_set_out();
419 zstate
= RUNNING_AQRD
;
440 z80_busreq_hpulse(); /* TODO: */
450 /*--------------------------------------------------------------------------*/
453 //inline __attribute__ ((always_inline))
454 void z80_setaddress(uint32_t addr
)
457 P_ADH
= (addr
& 0xff00) >> 8;
458 PIN_ADB
= (((addr
>> 16) << ADB_SHIFT
) ^ P_ADB
) & MASK(ADB_WIDTH
) << ADB_SHIFT
;
461 void z80_write(uint32_t addr
, uint8_t data
)
463 z80_setaddress(addr
);
474 uint8_t z80_read(uint32_t addr
)
478 z80_setaddress(addr
);
492 void z80_memset(uint32_t addr
, uint8_t data
, uint32_t length
)
498 z80_setaddress(addr
++);
506 void z80_write_block_P(const FLASH
uint8_t *src
, uint32_t dest
, uint32_t length
)
513 z80_setaddress(dest
++);
524 void z80_write_block(const uint8_t *src
, uint32_t dest
, uint32_t length
)
531 z80_setaddress(dest
++);
542 void z80_read_block (uint8_t *dest
, uint32_t src
, size_t length
)
549 z80_setaddress(src
++);
562 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
563 017A' rx.in_idx: ds 1 ;
564 017B' rx.out_idx: ds 1 ;
565 017C' rx.buf: ds rx.buf_len ;
566 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
568 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
569 018D' tx.in_idx: ds 1 ;
570 018E' tx.out_idx: ds 1 ;
571 018F' tx.buf: ds tx.buf_len ;
572 019E' tx.buf_end equ $-1 ; last byte
576 typedef struct __attribute__((packed
)) {
585 #define FIFO_BUFSIZE_MASK -3
586 #define FIFO_INDEX_IN -2
587 #define FIFO_INDEX_OUT -1
595 } fifo_dsc
[NUM_FIFOS
];
598 void z80_memfifo_init(const fifo_t f
, uint32_t addr
)
600 fifo_dsc
[f
].base
= addr
;
604 z80_bus_cmd(Request
);
605 fifo_dsc
[f
].mask
= z80_read(addr
+ FIFO_BUFSIZE_MASK
);
606 fifo_dsc
[f
].idx_in
= z80_read(addr
+ FIFO_INDEX_IN
);
607 fifo_dsc
[f
].idx_out
= z80_read(addr
+ FIFO_INDEX_OUT
);
608 z80_bus_cmd(Release
);
610 if (fifo_dsc
[f
].idx_in
!= 0 || fifo_dsc
[f
].idx_out
!= 0) {
611 DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
612 f
, addr
, fifo_dsc
[f
].idx_in
, fifo_dsc
[f
].idx_out
, fifo_dsc
[f
].mask
);
618 int z80_memfifo_is_empty(const fifo_t f
)
622 if (fifo_dsc
[f
].base
!= 0) {
624 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
627 z80_bus_cmd(Request
);
629 z80_bus_cmd(Release
);
630 rc
= idx
== fifo_dsc
[f
].idx_out
;
636 int z80_memfifo_is_full(const fifo_t f
)
640 if (fifo_dsc
[f
].base
!= 0) {
641 z80_bus_cmd(Request
);
642 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
643 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
644 z80_bus_cmd(Release
);
650 uint8_t z80_memfifo_getc_wait(const fifo_t f
)
654 while (z80_memfifo_is_empty(f
))
657 z80_bus_cmd(Request
);
658 idx
= fifo_dsc
[f
].idx_out
;
659 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
660 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
661 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
662 z80_bus_cmd(Release
);
667 int z80_memfifo_getc(const fifo_t f
)
671 if (fifo_dsc
[f
].base
!= 0) {
672 uint8_t idx
= fifo_dsc
[f
].idx_out
;
673 z80_bus_cmd(Request
);
674 if (idx
!= z80_read(fifo_dsc
[f
].base
+ FIFO_INDEX_IN
)) {
675 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
676 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
677 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
679 z80_bus_cmd(Release
);
686 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
690 while (z80_memfifo_is_full(f
))
693 z80_bus_cmd(Request
);
694 idx
= fifo_dsc
[f
].idx_in
;
695 z80_write(fifo_dsc
[f
].base
+idx
, val
);
696 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
697 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
698 z80_bus_cmd(Release
);