avr/i2c.c

   1
   2 /*
   3  * I2C (TWI) master interface.
   4  */
   5
   6 #include "common.h"
   7 #include <avr/interrupt.h>
   8 #include <util/delay.h>
   9 #include <string.h>
  10
  11 #include "config.h"
  12 #include "timer.h"
  13 #include "debug.h"
  14 #include "i2c.h"
  15
  16 #define  DEBUG_I2C 0
  17
  18 #define debug_i2c(fmt, args...)                 \
  19         debug_cond(DEBUG_I2C, fmt, ##args)
  20
  21
  22 /* General TWI Master status codes */
  23 #define TWI_START                  0x08  /* START has been transmitted */
  24 #define TWI_REP_START              0x10  /* Repeated START has been transmitted */
  25 #define TWI_ARB_LOST               0x38  /* Arbitration lost */
  26
  27 /* TWI Master Transmitter status codes */
  28 #define TWI_MTX_ADR_ACK            0x18  /* SLA+W has been transmitted and ACK received */
  29 #define TWI_MTX_ADR_NACK           0x20  /* SLA+W has been transmitted and NACK received */
  30 #define TWI_MTX_DATA_ACK           0x28  /* Data byte has been transmitted and ACK received */
  31 #define TWI_MTX_DATA_NACK          0x30  /* Data byte has been transmitted and NACK received */
  32
  33 /* TWI Master Receiver status codes */
  34 #define TWI_MRX_ADR_ACK            0x40  /* SLA+R has been transmitted and ACK received */
  35 #define TWI_MRX_ADR_NACK           0x48  /* SLA+R has been transmitted and NACK received */
  36 #define TWI_MRX_DATA_ACK           0x50  /* Data byte has been received and ACK transmitted */
  37 #define TWI_MRX_DATA_NACK          0x58  /* Data byte has been received and NACK transmitted */
  38
  39 /* TWI Miscellaneous status codes */
  40 #define TWI_NO_STATE               0xF8  /* No relevant state information available */
  41 #define TWI_BUS_ERROR              0x00  /* Bus error due to an illegal START or STOP condition */
  42
  43
  44 /*
  45  * TWINT: TWI Interrupt Flag
  46  * TWEA:  TWI Enable Acknowledge Bit
  47  * TWSTA: TWI START Condition Bit
  48  * TWSTO: TWI STOP Condition Bit
  49  * TWEN:  TWI Enable Bit
  50  * TWIE:  TWI Interrupt Enable
  51  *
  52  *      (1<<TWEN)|(1<<TWIE)|(1<<TWINT)
  53  *      (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|           (1<<TWEA)
  54  *      (1<<TWEN)|(1<<TWIE)|(1<<TWINT)
  55  *
  56  * default:
  57  *      (1<<TWEN)|          (1<<TWINT)|           (1<<TWSTO)
  58  *
  59  * Init:
  60  *      (1<<TWEN)
  61  *
  62  * start read/write:
  63  *      (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
  64  *      (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
  65  *      (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
  66  *      (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
  67  *
  68  * wait ready:
  69  *       (1<<TWIE)|(1<<TWSTO)
  70  *
  71  *
  72  *
  73  *i2c_result
  74  *
  75  *      0b10000000      Busy (Transmission in progress)
  76  *      0b01000000      Timeout
  77  *      0b00001000      Start transmitted
  78  *      0b00000100      Slave acknowledged address
  79  *      0b00000010      Data byte(s) transmitted/received
  80  *      0b00000001      Transmission completed
  81  *
  82  *
  83  *----------------------------------------------------------------------
  84  */
  85
  86 #define TWI_C_DISABLE           0x00
  87 #define TWI_C_ENABLE            (1<<TWEN)
  88
  89
  90
  91  typedef struct i2c_msg_s {
  92         uint8_t stat;
  93  #define XMIT_DONE      (1<<0)
  94  #define DATA_ACK       (1<<1)
  95  #define ADDR_ACK       (1<<2)
  96  #define START          (1<<3)
  97  #define TIMEOUT        (1<<6)
  98  #define BUSY           (1<<7)
  99         uint8_t idx;
 100         uint8_t len;
 101         uint8_t buf[CONFIG_SYS_I2C_BUFSIZE];
 102 } i2c_msg_t;
 103
 104 static volatile i2c_msg_t xmit;
 105
 106 ISR(TWI_vect)
 107 {
 108         uint8_t tmp_stat;
 109         uint8_t tmp_idx;
 110         uint8_t next_twcr;
 111         uint8_t n;
 112
 113         tmp_idx = xmit.idx;
 114         tmp_stat = xmit.stat;
 115
 116         uint8_t twsr = TWSR;
 117
 118         switch (twsr & 0xf8) {
 119
 120         case TWI_START:
 121         case TWI_REP_START:
 122                 tmp_stat = BUSY | START;
 123                 tmp_idx = 0;                    /* reset xmit_buf index */
 124
 125                 if (tmp_idx < xmit.len) {               /* all bytes transmited? */
 126                         TWDR = xmit.buf[tmp_idx];
 127                         ++tmp_idx;
 128                         next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT);
 129                 } else {
 130                         tmp_stat |= XMIT_DONE;
 131                         tmp_stat &= ~BUSY;
 132                         next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
 133                 }
 134                 break;
 135
 136         case TWI_MTX_ADR_ACK:
 137         case TWI_MTX_DATA_ACK:
 138                 if ((twsr&0xf8) == TWI_MTX_ADR_ACK)
 139                         tmp_stat |= ADDR_ACK;
 140                 else
 141                         tmp_stat |= DATA_ACK;
 142
 143                 if (tmp_idx < xmit.len) {               /* all bytes transmited? */
 144                         TWDR = xmit.buf[tmp_idx];
 145                         ++tmp_idx;
 146                         next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT);
 147                 } else {
 148                         tmp_stat |= XMIT_DONE;
 149                         tmp_stat &= ~BUSY;
 150                         next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
 151                 }
 152                 break;
 153
 154         case TWI_MTX_DATA_NACK:
 155                 tmp_stat |= XMIT_DONE;
 156                 tmp_stat &= ~BUSY;
 157                 next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
 158                 break;
 159
 160         case TWI_MRX_DATA_ACK:
 161                 xmit.buf[tmp_idx] = TWDR;
 162                 ++tmp_idx;
 163                 /* fall thru */
 164         case TWI_MRX_ADR_ACK:
 165                 if ((twsr&0xf8) == TWI_MRX_ADR_ACK)
 166                         tmp_stat |= ADDR_ACK;
 167                 else
 168                         tmp_stat |= DATA_ACK;
 169
 170                 n = xmit.len-1;
 171                 if (tmp_idx < n) {
 172                         next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA);
 173                 } else {
 174                         next_twcr = (1<<TWEN)|(1<<TWIE)|(1<<TWINT);
 175                 }
 176                 break;
 177
 178         case TWI_MRX_DATA_NACK:
 179                 tmp_stat |= ADDR_ACK | DATA_ACK;
 180
 181                 xmit.buf[tmp_idx] = TWDR;
 182                 ++tmp_idx;
 183                 /* fall thru */
 184         default:
 185                 tmp_stat &= ~BUSY;
 186                 next_twcr = (1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO);
 187                 break;
 188         }
 189
 190         xmit.stat = tmp_stat;
 191         xmit.idx = tmp_idx;
 192
 193         debug_i2c("|%02x", twsr);
 194         TWCR = next_twcr;
 195 }
 196
 197
 198 /*------------------------------------------------------------------*/
 199
 200 static uint8_t twps;
 201 static uint8_t twbr;
 202
 203
 204 static void _init(void)
 205 {
 206         xmit.stat = 0;
 207
 208         /* Disable TWI, disable TWI interrupt. */
 209         /* (Reset TWI hardware state machine.) */
 210         TWCR = TWI_C_DISABLE;
 211         _delay_us(5);
 212 #if DEBUG_I2C
 213         memset((void *) xmit.buf, 0xdf, sizeof(xmit.buf));
 214 #endif
 215
 216         TWDR = 0xff;
 217         TWBR = twbr;
 218         TWSR = twps & 0x03;
 219         TWCR = TWI_C_ENABLE;
 220 }
 221
 222 void i2c_init(uint32_t speed)
 223 {
 224         twps = 0;
 225         uint32_t tmp_twbr = F_CPU /2 / speed - 8;
 226
 227         while (tmp_twbr > 255) {
 228                 tmp_twbr >>= 4;
 229                 twps += 1;
 230         }
 231         debug_cond((twps > 3), "*** TWCLK too low: %lu Hz\n", speed);
 232
 233         twbr = (uint8_t) tmp_twbr;
 234         _init();
 235 }
 236
 237
 238 int_fast8_t i2c_waitready(void)
 239 {
 240         uint32_t timer = get_timer(0);
 241         uint8_t timeout = 0;
 242
 243         do {
 244                 if (get_timer(timer) >= 30) {
 245                         timeout = TIMEOUT;
 246                         _init();
 247                 }
 248         } while ((TWCR & ((1<<TWIE)|(1<<TWSTO))) != 0 && !timeout);
 249
 250         xmit.stat |= timeout;
 251
 252 #if DEBUG_I2C
 253         dump_ram((uint8_t *) &xmit, 4, "=== i2c_wait ready: (done)");
 254         _delay_ms(30);
 255 #endif
 256         return xmit.stat;
 257 }
 258
 259 static
 260 int i2c_send(uint8_t chip, uint16_t addr, uint8_t alen, uint8_t *buffer, int8_t len)
 261 {
 262         uint8_t i, n;
 263         uint8_t rc;
 264
 265         rc = i2c_waitready();
 266         if ((rc & (BUSY | TIMEOUT)) != 0)
 267                 return rc;
 268
 269         xmit.stat = BUSY;
 270         xmit.buf[0] = chip<<1;
 271         for (i = 1; i < alen+1; i++) {
 272                 xmit.buf[i] = (uint8_t) addr;
 273                 addr >>= 8;
 274         }
 275         for (n = len + i; i < n; i++)
 276                 xmit.buf[i] = *buffer++;
 277         xmit.len = i;
 278
 279 #if DEBUG_I2C
 280         dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_send");
 281         _delay_ms(30);
 282 #endif
 283         /* Enable TWI, TWI int and initiate start condition */
 284         TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA);
 285
 286         rc = xmit.stat;
 287
 288         return rc;
 289 }
 290
 291 static
 292 int i2c_recv(uint8_t chip, uint8_t *buffer, int8_t len)
 293 {
 294         uint8_t rc;
 295
 296         rc = i2c_waitready();
 297         if ((rc & (BUSY | TIMEOUT)) != 0)
 298                 return rc;
 299
 300         xmit.stat = BUSY;
 301         xmit.len = len + 1;
 302         xmit.buf[0] = (chip<<1) | 1;
 303
 304 #if DEBUG_I2C
 305         dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_recv: before start");
 306         _delay_ms(30);
 307 #endif
 308         /* Enable TWI, TWI int and initiate start condition */
 309         TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA);
 310         rc = i2c_waitready();
 311
 312 #if DEBUG_I2C
 313         dump_ram((uint8_t *) &xmit, 0x20, "=== i2c_recv: after completion");
 314         _delay_ms(30);
 315 #endif
 316         if (rc & DATA_ACK) {
 317                 /* at least 1 byte received */
 318                 for (uint8_t i=1, n=xmit.idx; i < n; i++)
 319                         *buffer++ = xmit.buf[i];
 320         }
 321
 322         return rc;
 323 }
 324
 325 /*
 326  * Read/Write interface:
 327  *   chip:    I2C chip address, range 0..127
 328  *   addr:    Memory (register) address within the chip
 329  *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
 330  *              memories, 0 for register type devices with only one
 331  *              register)
 332  *   buffer:  Where to read/write the data
 333  *   len:     How many bytes to read/write
 334  *
 335  *   Returns: 0 on success, not 0 on failure
 336  */
 337
 338 int i2c_write(uint8_t chip, unsigned int addr, uint_fast8_t alen,
 339                                 uint8_t *buffer, uint_fast8_t len)
 340 {
 341         int rc;
 342
 343         if ((alen > 2) || (1 + alen + len > CONFIG_SYS_I2C_BUFSIZE)) {
 344                 debug("** i2c_write: buffer overflow, alen: %u, len: %u\n",
 345                         alen, len);
 346                 return -1;
 347         }
 348
 349         i2c_send(chip, addr, alen, buffer, len);
 350         rc = i2c_waitready();
 351
 352         return (rc & XMIT_DONE) != 0;
 353 }
 354
 355 int i2c_read(uint8_t chip, unsigned int addr, uint_fast8_t alen,
 356                                 uint8_t *buffer, uint_fast8_t len)
 357 {
 358         int rc;
 359
 360         if ((alen > 2) || (1 + len > CONFIG_SYS_I2C_BUFSIZE)) {
 361                 debug("** i2c_read: parameter error: alen: %u, len: %u\n",
 362                         alen, len);
 363                 return -1;
 364         }
 365
 366         if (alen != 0) {
 367                 i2c_send(chip, addr, alen, NULL, 0);
 368         }
 369         rc = i2c_recv(chip, buffer, len);
 370
 371         return !((rc & (XMIT_DONE|DATA_ACK)) == (XMIT_DONE|DATA_ACK));
 372 }
 373
 374
 375