z180/z180reg.inc

   1         .xlist
   2
   3 ;;
   4 ;; HD64180/Z180 Register Definitions
   5 ;;
   6
   7
   8 b2m     macro   name,nr
   9 name    equ     nr
  10 M_&name equ     1 shl nr
  11         endm
  12
  13 ;       ifndef  IOBASE
  14 IOBASE  equ     0
  15 ;       endif
  16
  17 cntla0  equ     IOBASE+00h      ;ASCI Control Register A Channel 0
  18 cntla1  equ     IOBASE+01h      ;ASCI Control Register A Channel 1
  19         b2m MPE, 7              ;Multi-Processor Mode Enable
  20         b2m RE, 6               ;Receiver Enable
  21         b2m TE, 5               ;Transmitter Enable
  22         b2m RTS0, 4             ;Request to Send Channel 0
  23         b2m CKA1D, 4            ;
  24         b2m MPBR, 3             ;Multiprocessor Bit Receive (Read)
  25         b2m EFR, 3              ;Error Flag Reset (Write)
  26         b2m MOD2, 2             ;Data Format Mode 1 = 8-Bit data
  27         b2m MOD1, 1             ;1 = Parity enabled
  28         b2m MOD0, 0             ;1 = 2 stop bits
  29
  30 cntlb0  equ     IOBASE+02h      ;ASCI Control Register B Channel 0
  31 cntlb1  equ     IOBASE+03h      ;ASCI Control Register B Channel 1
  32         b2m MPBT,7              ;Multiprocessor Bit Transmit
  33         b2m MP,6                ;Multiprocessor Mode
  34         b2m CTS,5               ;Clear to Send
  35         b2m PS,5                ;Prescale
  36         b2m PEO,4               ;Parity Even Odd
  37         b2m DR,3                ;Divede Ratio
  38         b2m SS2,2               ;Source/Speed Select 2,1,0
  39         b2m SS1,1               ;
  40         b2m SS0,0               ;
  41
  42 stat0   equ     IOBASE+04h      ;ASCI Status Channel 0
  43 stat1   equ     IOBASE+05h      ;ASCI Status Channel 1
  44         b2m RDRF,7              ;Receive Data Register Full
  45         b2m OVRN,6              ;Overrun Error
  46         b2m PERR,5              ;Parity Error   (M80: PE conflicts with JP/CALL cc)
  47         b2m FE,4                ;Framing Error
  48         b2m RIE,3               ;Receive Interrupt Enable
  49         b2m DCD0,2              ;Data Carrier Detect (Ch 0)
  50         b2m CTS1E,2             ;Clear To Send (Ch 1)
  51         b2m TDRE,1              ;Transmit Data Register Empty
  52         b2m TIE,0               ;Transmit Interrupt Enable
  53
  54 tdr0    equ     IOBASE+06h      ;ASCI Transmit Data
  55 tdr1    equ     IOBASE+07h      ;ASCI Transmit Data
  56 rdr0    equ     IOBASE+08h      ;ASCI Receive Data
  57 rdr1    equ     IOBASE+09h      ;ASCI Receive Data
  58
  59 cntr    equ     IOBASE+0Ah      ;CSI/O Control Register
  60 trdr    equ     IOBASE+0Bh      ;CSI/O Transmit/Receive Data Register
  61
  62 tmdr0l  equ     IOBASE+0Ch      ;Timer Data Register Channel 0
  63 tmdr0h  equ     IOBASE+0Dh      ;
  64 rldr0l  equ     IOBASE+0Eh      ;Timer Reload Register Channel 0
  65 rldr0h  equ     IOBASE+0Fh      ;
  66 tcr     equ     IOBASE+10h      ;Timer Control Register
  67         b2m TIF1,7              ;Timer Interrupt Flag
  68         b2m TIF0,6              ;
  69         b2m TIE1,5              ;Timer Interrupt Enable
  70         b2m TIE0,4              ;
  71         b2m TOC1,3              ;Timer Output Control
  72         b2m TOC0,2              ;
  73         b2m TDE1,1              ;Timer Down Count Enable
  74         b2m TDE0,0              ;
  75
  76
  77 asext0  equ     IOBASE+12h      ;ASCI Extension Control Register
  78 asext1  equ     IOBASE+13h      ;ASCI Extension Control Register
  79         b2m DCD0DIS,6           ;DCD0 Disable
  80         b2m CTS0DIS,5           ;CTS0 Disable
  81         b2m X1,4                ;CKA * 1 Clock/Samle Rate Divider
  82         b2m BRGMOD,3            ;BRG Mode (Baud rate generator)
  83         b2m BREAKEN,2           ;Break Enable
  84         b2m BREAK,1             ;Break detected
  85         b2m SENDBREAK,0         ;Send Break
  86
  87 tmdr1l  equ     IOBASE+14h      ;Timer Data Register Channel 1
  88 tmdr1h  equ     IOBASE+15h      ;
  89 rldr1l  equ     IOBASE+16h      ;Timer Reload Register Channel 1
  90 rldr1h  equ     IOBASE+17h      ;
  91
  92 frc     equ     IOBASE+18h      ;Free Running Counter
  93
  94 astc0l  equ     IOBASE+1Ah      ;ASCI Time Constant Register 0
  95 astc0h  equ     IOBASE+1Bh      ;
  96 astc1l  equ     IOBASE+1Ch      ;ASCI Time Constant Register 1
  97 astc1h  equ     IOBASE+1Dh      ;
  98
  99 cmr     equ     IOBASE+1Eh      ;Clock Mutiplier Register
 100         b2m X2CM,7              ;X2 Clock Multiplier
 101         b2m LNC,6               ;Low Noise Crystal
 102
 103 ccr     equ     IOBASE+1Fh      ;CPU Control Register
 104         b2m NCD 7               ;No Clock Divide
 105
 106 sar0l   equ     IOBASE+20h      ;DMA Src Adr Register Channel 0
 107 sar0h   equ     IOBASE+21h      ;
 108 sar0b   equ     IOBASE+22h      ;
 109 dar0l   equ     IOBASE+23h      ;DMA Dst Adr Register Channel 0
 110 dar0h   equ     IOBASE+24h      ;
 111 dar0b   equ     IOBASE+25h      ;
 112 bcr0l   equ     IOBASE+26h      ;DMA Byte Count Register Channel 0
 113 bcr0h   equ     IOBASE+27h      ;
 114
 115 mar1l   equ     IOBASE+28h      ;DMA Memory Address Register Channel 1
 116 mar1h   equ     IOBASE+29h      ;
 117 mar1b   equ     IOBASE+2Ah      ;
 118 iar1l   equ     IOBASE+2Bh      ;DMA I/O Address Register Channel 1
 119 iar1h   equ     IOBASE+2Ch      ;
 120 iar1b   equ     IOBASE+2Dh      ;
 121         b2m ALTE,7              ;Alternating Chnnels
 122         b2m ALTC,6              ;Currently selected DMA Channel when Bit7=1
 123         b2m REQ1SEL2,2          ;
 124         b2m REQ1SEL1,1          ;
 125         b2m REQ1SEL0,0          ;
 126
 127 bcr1l   equ     IOBASE+2Eh      ;DMA Byte Count Register Channel 1
 128 bcr1h   equ     IOBASE+2Fh      ;
 129
 130 dstat   equ     IOBASE+30h      ;DMA Status Register
 131         b2m DE1,7               ;DMA enable ch 1,0
 132         b2m DE0,6               ;
 133         b2m DWE1,5              ;DMA Enable Bit Write Enable 1,0
 134         b2m DWE0,4              ;
 135         b2m DIE1,3              ;DMA Interrupt Enable 1,0
 136         b2m DIE0,2              ;
 137         b2m DME,0               ;DMA Master enable
 138
 139 dmode   equ     IOBASE+31h      ;DMA Mode Register
 140         b2m DM1,5               ;Ch 0 Destination Mode 1,0
 141         b2m DM0,4               ;
 142         b2m SM1,3               ;Ch 0 Source Mode 1,0
 143         b2m SM0,2               ;
 144         b2m MMOD,1              ;Memory MODE select (0=cycle steel/1=burst)
 145
 146 dcntl   equ     IOBASE+32h      ;DMA/WAIT Control
 147         b2m MWI1,7              ;Memory Wait Insertion
 148         b2m MWI0,6              ;
 149         b2m IWI1,5              ;I/O Wait Insertion
 150         b2m IWI0,4              ;
 151         b2m DMS1,3              ;DREQi Select (Edge/Level)
 152         b2m DMS0,2              ;
 153         b2m DIMA1,1             ;DMA Ch1 I/O Memory Mode Select
 154         b2m DIMA0,0
 155 M_MWI   equ M_MWI1 + M_MWI0
 156 M_IWI   equ M_IWI1 + M_IWI0
 157
 158 il      equ     IOBASE+33h      ;Interrupt Vector Low Register
 159 itc     equ     IOBASE+34h      ;INT/TRAP Control Register
 160         b2m TRAP,7              ;Trap
 161         b2m UFO,6               ;Unidentified Fetch Object
 162         b2m ITE2,2              ;/INT Enable 2,1,0
 163         b2m ITE1,1              ;
 164         b2m ITE0,0              ;
 165
 166 rcr     equ     IOBASE+36h      ;Refresh Control Register
 167         b2m REFE,7              ;Refresh Enable
 168         b2m REFW,6              ;Refresh Wait State
 169         b2m CYC1,1              ;Cycle select
 170         b2m CYC0,0              ;
 171
 172 cbr     equ     IOBASE+38h      ;MMU Common Base Register
 173 bbr     equ     IOBASE+39h      ;MMU Bank Base Register
 174 cbar    equ     IOBASE+3Ah      ;MMU Common/Bank Register
 175
 176 omcr    equ     IOBASE+3Eh      ;Operation Mode Control Register
 177         b2m M1E,7               ;M1 Enable
 178         b2m M1TE,6              ;M1 Temporary Enable
 179         b2m IOC,5               ;I/O Compatibility
 180
 181 icr     equ     IOBASE+3Fh      ;I/O Control Register
 182         b2m IOSTP,5             ;I/O Stop
 183 ;
 184 ; Interrupt Vectors
 185 ;
 186
 187 IV$INT1  equ    0               ;/INT1         (highest priority)
 188 IV$INT2  equ    2               ;/INT2
 189 IV$PRT0  equ    4               ;PRT channel 0
 190 IV$PRT1  equ    6               ;PRT channel 1
 191 IV$DMA0  equ    8               ;DMA channel 0
 192 IV$DMA1  equ    10              ;DMA channel 1
 193 IV$CSIO  equ    12              ;CSI/O
 194 IV$ASCI0 equ    14              ;ASCI channel 0
 195 IV$ASCI1 equ    16              ;ASCI channel 1 (lowest priority)
 196
 197         .list
 198