avr/z180-serv.c

   1 /*
   2  */
   3
   4 #include "common.h"
   5 //#include <avr/power.h>
   6 //#include <avr/pgmspace.h>
   7 #include <util/atomic.h>
   8 //#include <avr/sleep.h>
   9 //#include <string.h>
  10
  11 #include "background.h"
  12 #include "debug.h"
  13 #include "serial.h"
  14 #include "z80-if.h"
  15 #include "z180-serv.h"
  16
  17
  18
  19 /*--------------------------------------------------------------------------*/
  20
  21
  22 uint8_t z80_get_byte(uint32_t adr)
  23 {
  24         uint8_t data;
  25
  26         z80_bus_cmd(Request);
  27         data = z80_read(adr);
  28         z80_bus_cmd(Release);
  29
  30         return data;
  31 }
  32
  33
  34 /*--------------------------------------------------------------------------*/
  35
  36 struct msg_item {
  37         uint8_t fct;
  38         uint8_t sub_min, sub_max;
  39         void (*func)(uint8_t, int, uint8_t *);
  40 };
  41
  42 uint32_t msg_to_addr(uint8_t *msg)
  43 {
  44         union {
  45                 uint32_t as32;
  46                 uint8_t as8[4];
  47         } addr;
  48
  49         addr.as8[0] = msg[0];
  50         addr.as8[1] = msg[1];
  51         addr.as8[2] = msg[2];
  52         addr.as8[3] = 0;
  53
  54         return addr.as32;
  55 }
  56
  57
  58 void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
  59 {
  60         (void)len;
  61
  62         z80_memfifo_init(subf, msg_to_addr(msg));
  63 }
  64
  65
  66 void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
  67 {
  68         (void)subf;
  69
  70         while (len--)
  71                 putchar(*msg++);
  72 }
  73
  74
  75 const FLASH struct msg_item z80_messages[] =
  76 {
  77         { 0,                    /* fct nr. */
  78           1, 3,                 /* sub fct nr. from, to */
  79           do_msg_ini_memfifo},
  80         { 1,
  81           1, 1,
  82           do_msg_char_out},
  83         { 0xff,                         /* end mark */
  84           0, 0,
  85           0},
  86
  87 };
  88
  89
  90
  91
  92 void do_message(int len, uint8_t *msg)
  93 {
  94         uint8_t fct, sub_fct;
  95         int_fast8_t i = 0;
  96
  97         if (len >= 2) {
  98                 fct = *msg++;
  99                 sub_fct = *msg++;
 100                 len -= 2;
 101
 102                 while (fct != z80_messages[i].fct) {
 103                         if (z80_messages[i].fct == 0xff) {
 104                                 DBG_P(1, "do_message: Unknown function: %i, %i\n",
 105                                                 fct, sub_fct);
 106                                 return; /* TODO: unknown message # */
 107                         }
 108
 109                         ++i;
 110                 }
 111
 112                 while (fct == z80_messages[i].fct) {
 113                         if (sub_fct >= z80_messages[i].sub_min &&
 114                                         sub_fct <= z80_messages[i].sub_max )
 115                                 break;
 116                         ++i;
 117                 }
 118
 119                 if (z80_messages[i].fct != fct) {
 120                         DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
 121                                         fct, sub_fct);
 122                         return; /* TODO: unknown message sub# */
 123                 }
 124
 125                 (z80_messages[i].func)(sub_fct, len, msg);
 126
 127
 128         } else {
 129                 /* TODO: error */
 130                 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
 131         }
 132 }
 133
 134
 135
 136 #define CTRBUF_LEN 256
 137
 138 void check_msg_fifo(void)
 139 {
 140         int ch;
 141         static int_fast8_t state;
 142         static int msglen,idx;
 143         static uint8_t buffer[CTRBUF_LEN];
 144
 145         while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
 146                 switch (state) {
 147                 case 0:         /* wait for start of message */
 148                         if (ch == 0x81) {
 149                                 msglen = 0;
 150                                 idx = 0;
 151                                 state = 1;
 152                         }
 153                         break;
 154                 case 1:         /* get msg len */
 155                         if (ch > 0 && ch <= CTRBUF_LEN) {
 156                                 msglen = ch;
 157                                 state = 2;
 158                         } else
 159                                 state = 0;
 160                         break;
 161                 case 2:         /* get message */
 162                         buffer[idx++] = ch;
 163                         if (idx == msglen) {
 164                                 do_message(msglen, buffer);
 165                                 state = 0;
 166                         }
 167                         break;
 168                 }
 169         }
 170 }
 171
 172
 173 int msg_handling(int state)
 174 {
 175         uint8_t pending;
 176
 177         ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 178                 pending = (Stat & S_MSG_PENDING) != 0;
 179                 Stat &= ~S_MSG_PENDING;
 180         }
 181
 182         if (pending) {
 183                 switch (state) {
 184                 case 0:
 185                         z80_bus_cmd(Request);
 186                         uint32_t addr = z80_read(0x40) +
 187                                 ((uint16_t) z80_read(0x41) << 8) +
 188                                 ((uint32_t) z80_read(0x42) << 16);
 189                         z80_bus_cmd(Release);
 190                         if (addr != 0) {
 191                                 z80_memfifo_init(fifo_msgin, addr);
 192                                 state = 1;
 193                         }
 194                         break;
 195                 case 1:
 196                         check_msg_fifo();
 197                         break;
 198                 }
 199         }
 200
 201         return state;
 202 }
 203
 204
 205 int console_handling(int state)
 206 {
 207         int ch;
 208         uint8_t pending;
 209
 210         ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 211                 pending = (Stat & S_CON_PENDING) != 0;
 212                 Stat &= ~S_CON_PENDING;
 213         }
 214
 215         if (pending) {
 216                 while ((ch = z80_memfifo_getc(fifo_conout)) >= 0) {
 217                         putchar(ch);
 218                 }
 219         }
 220
 221         return state;
 222 }
 223
 224
 225
 226
 227 static int handle_msg_handling;
 228
 229 void setup_z180_serv(void)
 230 {
 231
 232         handle_msg_handling = bg_register(msg_handling, 0);
 233 //      bg_register(console_handling, 0);
 234 }
 235
 236 void restart_z180_serv(void)
 237 {
 238         z80_bus_cmd(Request);
 239         z80_write(0x40, 0);
 240         z80_write(0x41, 0);
 241         z80_write(0x42, 0);
 242         z80_bus_cmd(Release);
 243
 244         bg_setstat(handle_msg_handling, 0);
 245 }
 246
 247 /*--------------------------------------------------------------------------*/
 248
 249 #if 0
 250 void dump_mem(const FLASH uint8_t *addr, uint32_t len)
 251 {
 252         DBG_P(1, "hdrom dump:");
 253         while (len) {
 254                 DBG_P(1, "\n    %.5x:", addr);
 255                 for (unsigned i = 0; i<16; i++)
 256                         DBG_P(1, " %.2x", *addr++);
 257                 len -= len > 16 ? 16 : len;
 258         }
 259         DBG_P(1, "\n");
 260 }
 261 #endif
 262 /*--------------------------------------------------------------------------*/
 263
 264
 265 const FLASH uint8_t iniprog[] = {
 266         0xAF,                   // xor     a
 267         0xED, 0x39, 0x36,       // out0    (rcr),a         ;disable  DRAM refresh
 268         0x3E, 0x30,             // ld      a,030h
 269         0xED, 0x39, 0x32        //out0    (dcntl),a       ;0 mem, max i/0 wait states
 270 };
 271
 272 const FLASH uint8_t sertest[] = {
 273         0xAF,              //   xor     a
 274         0xED, 0x39, 0x36,  //   out0    (rcr),a         ;disable  DRAM refresh
 275         0x3E, 0x30,        //   ld      a,030h
 276         0xED, 0x39, 0x32,  //   out0    (dcntl),a       ;0 mem, max i/0 wait states
 277         0x3E, 0x80,        //   ld      a,M_MPBT                ;no MP, PS=10, DR=16, SS=0
 278         0xED, 0x39, 0x03,  //   out0    (cntlb1),a
 279         0x3E, 0x64,        //   ld      a,M_RE + M_TE + M_MOD2  ;
 280         0xED, 0x39, 0x01,  //   out0    (cntla1),a
 281         0x3E, 0x00,        //   ld      a,0
 282         0xED, 0x39, 0x05,  //   out0    (stat1),a       ;Enable rx interrupts
 283         0xED, 0x38, 0x05,  //l0:in0     a,(stat1)
 284         0xE6, 0x80,        //   and     80h
 285         0x28, 0xF9,        //   jr      z,l0
 286         0xED, 0x00, 0x09,  //   in0     b,(rdr1)
 287         0xED, 0x38, 0x05,  //l1:in0     a,(stat1)
 288         0xE6, 0x02,        //   and     02h
 289         0x28, 0xF9,        //   jr      z,l1
 290         0xED, 0x01, 0x07,  //   out0    (tdr1),b
 291         0x18, 0xEA,        //   jr      l0
 292 };
 293
 294 const FLASH uint8_t test1[] = {
 295         0xAF,              //   xor     a
 296         0xED, 0x39, 0x36,  //   out0    (rcr),a         ;disable  DRAM refresh
 297         0x3E, 0x30,        //   ld      a,030h
 298         0xED, 0x39, 0x32,  //   out0    (dcntl),a       ;0 mem, max i/0 wait states
 299         0x21, 0x1E, 0x00,  //   ld      hl,dmclrt       ;load DMA registers
 300         0x06, 0x08,        //   ld      b,dmct_e-dmclrt
 301         0x0E, 0x20,        //   ld      c,sar0l
 302         0xED, 0x93,        //   otimr
 303         0x3E, 0xC3,        //   ld      a,0c3h          ;dst +1, src +1, burst
 304         0xED, 0x39, 0x31,  //   out0    (dmode),a       ;
 305         0x3E, 0x62,        //   ld      a,062h          ;enable dma0,
 306         0xED, 0x39, 0x30,  //cl_1:      out0    (dstat),a       ;copy 64k
 307         0x18, 0xFB,        //   jr      cl_1            ;
 308         0x00, 0x00,        //dmclrt:    dw      0               ;src (inc)
 309         0x00,              //   db      0               ;src
 310         0x00, 0x00,        //   dw      0               ;dst (inc),
 311         0x00,              //   db      0               ;dst
 312         0x00, 0x00,        //   dw      0               ;count (64k)
 313 };
 314
 315
 316