z180/cpuinfo.180

   1         .z80                            ; for M80, ignored by SLR assembler
   2         include z180reg.inc
   3
   4 RUN_TPA         equ     0
   5
   6 UUNKNOWN        equ     0       ;Unknown CPU
   7 U8080           equ     1       ;8080
   8 U8085           equ     2       ;8085
   9 UZ80            equ     3       ;Z80
  10 UX180           equ     4       ;HD64180 or higher
  11 UHD64180        equ     5       ;HD64180
  12 UZ80180         equ     6       ;Z80180
  13 UZ8S180         equ     7       ;Z8S180, Z8L180
  14
  15
  16 ;-------------------------------------------------------------------------------
  17
  18
  19    if RUN_TPA
  20 base            equ     0100h
  21    else
  22 base            equ     0
  23    endif
  24
  25
  26         aseg
  27         org     base
  28         jp      start
  29
  30 done:   db      0
  31 result: db      0
  32 cycls:  db      0
  33 wstates:db      0
  34
  35 ;-------------------------------------------------------------------------------
  36 cyctab:
  37         db       0      ;Unknown CPU
  38         db      20      ;8080
  39         db      20      ;8085
  40         db      21      ;Z80
  41         db      19      ;HD64180 or higher
  42         db      19      ;HD64180
  43         db      19      ;Z80180
  44         db      19      ;Z8S180, Z8L180
  45
  46 ;-------------------------------------------------------------------------------
  47 ; Check if register C exists. D holds mask of bit to test.
  48 ;       return z, if register exists
  49
  50 chk_reg:
  51         in      a,(c)
  52         ld      l,a
  53         ; check, if register is changeable
  54         xor     d               ;
  55         out     (c),a
  56         in      a,(c)           ; get it back
  57         xor     d
  58         out     (c),l           ; set register to original state
  59         cp      l
  60         ret
  61
  62 ;-------------------------------------------------------------------------------
  63 ; Check CPU
  64 ;
  65 ;
  66 ; return:
  67 ;       E = 0   Unknown
  68 ;       E = 1   8080
  69 ;       E = 2   8085
  70 ;       E = 3   Z80
  71 ;       E = 4   HD64180 or higher
  72 ;       E = 5   HD64180
  73 ;       E = 6   Z80180
  74 ;       E = 7   Z8S180, Z8L180
  75 ;
  76 ;-------------------------------------------------------------------------------
  77 ; Registers only in Z180+, not in HD64180
  78 ;       3E      OMCR
  79 ;
  80 ; Registers only in Z8S180/Z8L180
  81 ;       12      ASEXT0
  82 ;       13      ASEXT1
  83 ;       1A      ASTC0L
  84 ;       1B      ASTC0H
  85 ;       1C      ASTC1L
  86 ;       1D      ASTC1H
  87 ;       1E      CMR
  88 ;       1F      CCR
  89 ;       2D      IAR1B
  90 ;
  91 ; Reserved registers
  92 ;       11
  93 ;       19
  94 ;       35
  95 ;       37
  96 ;       3B - 3D
  97
  98 check:
  99         ld      e,U8080         ; Init return val, assume 8080
 100         xor     a
 101         dec     a               ; 00 --> 0FFH   8080/8085: even parity; Z80+: No overflow
 102         jp      po,chk_z80      ; Z80+ if P/V flag reset
 103
 104         ; The 8085 logical AND instructions always set the auxiliary flag ON.
 105         ; The 8080 logical AND instructions set the flag to reflect the
 106         ; logical OR of bit 3 of the values involved in the AND operation.
 107         ; (8080/8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL, 1977, 1978)
 108
 109         xor     a
 110         and     a               ; 8085 sets, 8080 resets half carry.
 111         daa                     ; A=06 (8085) or A=00 (8080)
 112         ret     z
 113         inc     e
 114         ret
 115
 116 chk_z80:
 117         ld      e,UZ80          ; Assume Z80
 118         daa                     ; Z80: 099H, x180+: 0F9H
 119         cp      99h             ; Result on 180 type cpus is F9 here. Thanks Hitachi
 120         ret     z
 121         inc     e               ; x180
 122
 123         ; At least Hitachi HD64180
 124         ; Test differences in certain internal registers
 125         ; to determine the 180 variant.
 126
 127         ld      a,(wstates)
 128         out0    (DCNTL),a
 129         out0    (RCR),b         ;
 130         in0     a,(icr)
 131         cp      01FH
 132         jr      z,icr_ok
 133
 134         ;TODO: additional plausibility checks
 135
 136         ret                     ; I/O registers not found
 137
 138         ; Register (base) found.
 139
 140 icr_ok:
 141         inc     e               ; HD64180
 142         ld      c,omcr          ; Check, if CPU has OMCR register
 143         ld      d,M_IOC         ;
 144         call    chk_reg         ;
 145         ret     nz              ; Register does not exist. It's a HD64180
 146
 147         inc     e               ; Z80180
 148         ld      c,cmr           ; Check, if CPU has CMR register
 149         ld      d,M_LNC         ;
 150         call    chk_reg         ;
 151         ret     nz              ; register does not exist. It's a Z80180
 152
 153         inc     e               ; S180/L180 (class) detected.
 154         ret
 155
 156 ;-------------------------------------------------------------------------------
 157
 158 start:
 159         ld      sp,stack
 160         ld      hl,done
 161         ld      b,h
 162         ld      (hl),b
 163         inc     hl
 164         ld      (hl),b
 165         call    check
 166         ld      hl,cyctab
 167         ld      d,h
 168         add     hl,de
 169         ld      a,(hl)
 170         ld      hl,cycls
 171         ld      (hl),a
 172         dec     hl
 173         ld      (hl),e
 174         dec     hl
 175         ld      (hl),0ffH
 176         out     (040H),a
 177                                 ;808x   Z80    Z180(0W) Z180(MaxW)
 178 loop:                           ;---------------------------------
 179         in      a,(050h)        ;10     11       10     +3*3  19
 180         jp      loop            ;10     10        9     +3*3  18
 181                                 ;---------------------------------
 182                                 ;20     21       19           37
 183
 184 ;       jr      loop            ;--     12        8     +2*3  14
 185
 186         rept    4
 187           dw    0
 188         endm
 189 stack:
 190         end
 191
 192 ; vim:set ts=8 noet nowrap