z180/config.inc

   1
   2 FALSE   equ     0
   3 TRUE    equ     NOT FALSE
   4
   5
   6 DEBUG   equ     true
   7
   8 banked  equ     true
   9
  10 ;-----------------------------------------------------
  11 ; CPU and BANKING types
  12
  13
  14 CPU_Z180        equ     TRUE
  15 CPU_Z80         equ     FALSE
  16
  17 ROMSYS          equ     FALSE
  18
  19 AVRCLK          equ     18432           ;[KHz]
  20
  21     if CPU_Z180
  22
  23 ;-----------------------------------------------------
  24 FOSC            equ     AVRCLK/2        ;Oscillator frequency [KHz]
  25 PHI             equ     FOSC*2          ;CPU frequency (clock doubler enabled)
  26
  27 ;----------------------------------------------------------------------
  28 ; Baudrate Generator for x16 clock mode:
  29 ; TC = (f PHI / (32 * baudrate)) - 2
  30 ;
  31 ;     PHI [MHz]: 9.216 18.432
  32 ;     baudrate     TC     TC
  33 ;     ----------------------
  34 ;      115200       -      3
  35 ;       57600       3      8
  36 ;       38400       -     13
  37 ;       19200      13     28
  38 ;        9600      28     58
  39
  40
  41 ;-----------------------------------------------------
  42 ; Programmable Reload Timer (PRT)
  43
  44 PRT_PRE         equ     20              ;PRT prescaler
  45
  46 ; Reload value for 10 ms Int. (0.1KHz):
  47 ; tc10ms = phi/prescale/0.1KHz  = phi / (prescale/10)
  48
  49 PRT_TC10MS      equ     PHI / (PRT_PRE/10)
  50
  51 ;-----------------------------------------------------
  52 ; MMU
  53
  54 COMMON_SIZE     equ     16*1024         ;Common Area size in bytes
  55                                         ;must be multiple of 4K
  56
  57 if (COMMON_SIZE mod 1000h)
  58         .printx COMMON_SIZE not multiple of 4K!
  59         end     ;stop assembly
  60 endif
  61
  62 CSK     equ     COMMON_SIZE/1000h       ;
  63 CA      equ     10h - CSK               ;common area start
  64 BA      equ     0                       ;banked area start
  65
  66 SYS$CBR         equ     0
  67 SYS$CBAR        equ     CA*16 + CA      ;CBAR in system mode
  68 USR$CBAR        equ     CA*16 + BA      ;CBAR in user mode (CP/M)
  69
  70
  71 BANKS           equ     18              ;max nr. of banks
  72
  73 ;-----------------------------------------------------
  74
  75 CREFSH          equ     0               ;Refresh rate register (disable refresh)
  76 CWAITIO         equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States
  77 PHI_X2          equ     0               ;set to M_X2CM to enable the clock doubler
  78
  79     endif               ;CPU_Z180
  80     if  CPU_Z80
  81
  82 PHI             equ     AVRCLK/5        ;CPU frequency [KHz]
  83 BAUDCLCK        equ     AVRCLK/10       ;Baudrate clock [KHz]
  84 ;BDCLK16                equ
  85
  86 SIOAD   EQU     0bch
  87 SIOAC   EQU     0bdh
  88 SIOBD   EQU     0beh
  89 SIOBC   EQU     0bfh
  90
  91 CTC0    EQU     0f4h
  92 CTC1    EQU     0f5h
  93 CTC2    EQU     0f6h
  94 CTC3    EQU     0f7h
  95
  96 ;
  97 ; Init Serial I/O for console input and output (SIO-A)
  98 ;
  99 ; Baudrate clock: 1843200 Hz (Bus connector pin A17)
 100 ;
 101 ; Baudrate   Divider    SIO     CTC
 102 ; ---------------------------------
 103 ; 115200          16     16       1
 104 ;  57600          32     16       2
 105 ;  38400          48     16       3
 106 ;  19200          96     16       6
 107 ;   9600         192     16      12
 108 ;   4800         384     16      24
 109 ;   2400         768     16      48
 110 ;   1200        1536     16      96
 111 ;    600        3072     16     192
 112 ;    300        6144     64      92
 113
 114     endif       ; CPU_Z80
 115
 116     if  ROMSYS
 117 c$rom           equ     0a5h
 118 ROM_EN          equ     0C0h
 119 ROM_DIS         equ     ROMEN+1
 120      if CPU_Z180
 121 CWAITROM        equ     2 shl MWI0
 122      endif
 123     endif
 124
 125
 126 DDTZRSTVEC      equ     030h            ;DDTZ Restart vector (breakpoints)
 127
 128 INIDONE         equ     03Fh            ;CP/M skip hw init, if this address
 129 INIDONEVAL      equ     080h            ;    is set to this value.
 130
 131 mtx.fifo_len    equ     32              ;Message transfer fifos
 132 mtx.fifo_id     equ     0               ;    This *must* have #0
 133 mrx.fifo_len    equ     32
 134 mrx.fifo_id     equ     1
 135
 136 ci.fifo_len     equ     32              ;AVRCON Character I/O via AVR
 137 ci.fifo_id      equ     2
 138 co.fifo_len     equ     32
 139 co.fifo_id      equ     3
 140
 141 s1.rx_len       equ     128             ;Serial 1 (ASCI1) buffers
 142 s1.rx_id        equ     4               ;
 143 s1.tx_len       equ     128             ;
 144 s1.tx_id        equ     5               ;
 145
 146 AVRINT5         equ     4Fh
 147 AVRINT6         equ     5Fh
 148 ;PMSG           equ     80h
 149
 150 ;-----------------------------------------------------
 151 ; Definition of (logical) top 2 memory pages
 152
 153 sysram_start    equ     0FE00h
 154 bs$stack$size   equ     80
 155
 156 isvsw_loc       equ     0FEE0h
 157
 158 ivtab           equ     0ffc0h          ;int vector table
 159 iv2tab          equ     ivtab + 2*9
 160
 161
 162
 163 ;-----------------------------------------------------
 164
 165 o.id            equ     -4
 166 o.mask          equ     -3
 167 o.in_idx        equ     -2
 168 o.out_idx       equ     -1
 169
 170         .lall
 171
 172 mkbuf   macro   id,name,size
 173   if ((size AND (size-1)) NE 0) OR (size GT 256)
 174     .printx Error: buffer ^size must be power of 2 and in range 0..256!
 175     name&.mask equ ;wrong size error
 176   else
 177     db id
 178     ds 3
 179     name:: ds size
 180     name&.mask equ low (size-1)
 181     if size ne 0
 182       name&.end equ $-1
 183       name&.len equ size
 184       name&.id equ id
 185     endif
 186   endif
 187 endm
 188
 189 ;-----------------------------------------------------
 190
 191 inidat  macro
 192         cseg
 193 ??ps.a  defl    $
 194         endm
 195
 196 inidate macro
 197 ??ps.len defl   $ - ??ps.a
 198         dseg
 199         ds      ??ps.len
 200         endm
 201
 202 ;-----------------------------------------------------
 203
 204 b0call  macro   address
 205         call    _b0call
 206         dw      address
 207         endm