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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
4 * SPDX-License-Identifier: GPL-2.0
11 * | Z180-Sig | AVR-Port | Dir |
12 * +------------+---------------+-------+
44 * | BUSREQ | PD 7 | O |
45 * | BUSACK | PD 6 | I |
48 * +------------------------------------+
57 #include <util/atomic.h>
63 //#define P_ZCLK PORTB
65 //#define DDR_ZCLK DDRB
73 #define P_BUSREQ PORTD
75 #define PIN_BUSREQ PIND
76 #define DDR_BUSREQ DDRD
77 #define P_BUSACK PORTD
78 #define PIN_BUSACK PIND
80 #define DDR_BUSACK DDRD
101 //#define ADB_PORT PORTE
104 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
105 #define Z80_O_MREQ SBIT(P_MREQ, 4)
106 #define Z80_O_RD SBIT(P_RD, 3)
107 #define Z80_O_WR SBIT(P_WR, 2)
108 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
109 #define Z80_I_BUSREQ SBIT(PIN_BUSREQ, 7)
110 //#define Z80_O_NMI SBIT(P_NMI, )
111 #define Z80_O_RST SBIT(P_RST, 5)
112 #define Z80_I_RST SBIT(PIN_RST, 5)
113 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
114 //#define Z80_I_HALT SBIT(P_HALT, )
122 #define DDR_STEP DDRG
125 #define DDR_WAIT DDRG
126 /* All three signals are on the same Port (PortG) */
127 #define PORT_SS PORTG
130 #define Z80_O_RUN SBIT(PORT_SS, RUN)
131 #define Z80_O_STEP SBIT(PORT_SS, STEP)
132 #define Z80_I_WAIT SBIT(PORT_SS, WAIT)
138 #define MASK(n) ((1<<(n))-1)
139 #define SMASK(w,s) (MASK(w) << (s))
141 void z80_bus_request_or_exit(void)
143 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
))
144 cmd_error(CMD_RET_FAILURE
, EBUSTO
, NULL
);
147 static zstate_t zstate
;
148 static volatile uint8_t timer
; /* used for bus timeout */
151 static volatile uint16_t busack_cycles_ovl
;
153 static uint32_t busack_cycles
;
155 ISR(TIMER4_COMPB_vect
)
160 /*---------------------------------------------------------*/
161 /* 10Hz timer interrupt generated by OC5A */
162 /*---------------------------------------------------------*/
164 ISR(TIMER5_COMPA_vect
)
173 /*--------------------------------------------------------------------------*/
176 static void z80_addrbus_set_in(void)
178 /* /MREQ, /RD, /WR: Input, no pullup */
179 DDR_MREQ
&= ~(_BV(MREQ
) | _BV(RD
) | _BV(WR
));
188 PIN_ADB
= P_ADB
& (MASK(ADB_WIDTH
) << ADB_SHIFT
);
189 DDR_ADB
= DDR_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
193 static void z80_addrbus_set_out(void)
195 /* /MREQ, /RD, /WR: Output and high */
199 DDR_MREQ
|= _BV(MREQ
) | _BV(RD
) | _BV(WR
);
203 DDR_ADB
= DDR_ADB
| (MASK(ADB_WIDTH
) << ADB_SHIFT
);
207 static void z80_dbus_set_in(void)
214 static void z80_dbus_set_out(void)
219 static void z80_reset_active(void)
221 if (Stat
& S_RESET_POLARITY
)
227 static void z80_reset_inactive(void)
229 if (Stat
& S_RESET_POLARITY
)
235 static void z80_reset_pulse(void)
239 z80_reset_inactive();
243 void z80_setup_bus(void)
245 ATOMIC_BLOCK(ATOMIC_RESTORESTATE
) {
247 /* /ZRESET: Input, no pullup */
248 DDR_RST
&= ~_BV(RST
);
251 /* /BUSREQ: Output and high */
253 DDR_BUSREQ
|= _BV(BUSREQ
);
255 /* /BUSACK: Input, no pullup */
256 DDR_BUSACK
&= ~_BV(BUSACK
);
257 P_BUSACK
&= ~_BV(BUSACK
);
259 z80_addrbus_set_in();
262 if (getenv_yesno(PSTR(ENV_SINGLESTEP
))) {
263 /* /RUN & /STEP: output, /WAIT: input */
265 PORT_SS
= (PORT_SS
& ~_BV(RUN
)) | _BV(STEP
);
266 DDR_SS
= (DDR_SS
& ~_BV(WAIT
)) | _BV(RUN
) | _BV(STEP
);
270 Stat
|= S_RESET_POLARITY
;
272 Stat
&= ~S_RESET_POLARITY
;
280 PRR1
&= ~_BV(PRTIM5
);
281 OCR5A
= F_CPU
/ 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
282 TCCR5B
= (0b01<<WGM52
)|(0b101<<CS40
); /* CTC Mode, Prescaler 1024 */
283 TIMSK5
= _BV(OCIE5A
); /* Enable oca interrupt */
288 uint32_t z80_get_busreq_cycles(void)
290 return busack_cycles
;
293 zstate_t
z80_bus_state(void)
298 void z80_toggle_reset(void)
303 void z80_toggle_busreq(void)
309 static void z80_busreq_hpulse(void)
312 z80_addrbus_set_in();
315 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
317 Z80_O_BUSREQ
= 1; /* 2 AVR clock cycles */
318 Z80_O_BUSREQ
= 0; /* 2 AVR clock cycles */
323 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
327 if (Z80_I_BUSACK
== 1) {
335 if (zstate
& ZST_ACQUIRED
) {
337 while (Z80_I_BUSACK
== 1 && timer
)
339 if (Z80_I_BUSACK
== 0)
340 z80_addrbus_set_out();
348 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
352 ----------------+---------------+---------------+---------------+---------------+
354 Reset | 0 | 0 | 0 | 0 |
357 Request | 1 | | 3 | |
360 Release | | 0 | | 2 |
366 Restart | | | 2 | 3 |
374 zstate_t
z80_bus_cmd(bus_cmd_t cmd
)
380 z80_addrbus_set_in();
385 while (Z80_I_BUSACK
== 0 && timer
)
394 timer
= 255; //BUS_TO;
400 busack_cycles_ovl
= 0;
401 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
402 Z80_I_RST
= 1; /* Toggle RESET --> inactive */
404 TIFR4
= _BV(OCF4B
); /* Clear compare match flag */
405 // TIMSK4 &= ~_BV(OCIE4A); /* Disable Output Compare A interrupt */
407 TIMSK4
|= _BV(OCIE4B
); /* Enable compare match interrupt */
409 while (Z80_I_BUSACK
== 1 && timer
)
412 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
413 tcnt
= TCNT4
- OCR4B
;
414 ovl_cnt
= busack_cycles_ovl
;
416 TIMSK4
&= ~_BV(OCIE4B
); /* Disable compare match interrupt */
417 // TIMSK4 |= _BV(OCIE4A); /* Enable Output Compare A interrupt */
419 if (Z80_I_BUSACK
== 0) {
420 if ((ifr
& _BV(OCF4B
)) && !(tcnt
& (1<<15)))
422 busack_cycles
= tcnt
+ ((uint32_t) ovl_cnt
<< 16);
423 z80_addrbus_set_out();
425 // debug("### ovl: %u, ifr: %u, beg: %u, end: %u\n", ovl_cnt,
426 // (ifr & _BV(OCF4B)) != 0, OCR4B, tcnt);
436 while (Z80_I_BUSACK
== 1 && timer
)
438 if (Z80_I_BUSACK
== 0) {
439 z80_addrbus_set_out();
440 zstate
= RUNNING_AQRD
;
455 z80_addrbus_set_in();
460 while (Z80_I_BUSACK
== 0 && timer
)
466 z80_addrbus_set_in();
469 while (Z80_I_BUSACK
== 0 && timer
)
481 _delay_ms(20); /* TODO: */
482 z80_reset_inactive();
488 z80_addrbus_set_in();
490 z80_addrbus_set_out();
491 zstate
= RUNNING_AQRD
;
512 z80_busreq_hpulse(); /* TODO: */
522 /*--------------------------------------------------------------------------*/
525 //inline __attribute__ ((always_inline))
526 void z80_setaddress(uint32_t addr
)
529 P_ADH
= (addr
& 0xff00) >> 8;
530 PIN_ADB
= (((addr
>> 16) << ADB_SHIFT
) ^ P_ADB
) & MASK(ADB_WIDTH
) << ADB_SHIFT
;
533 int32_t z80_memsize_detect(void)
535 const uint8_t PATTERN_1
= 0x55;
536 const uint8_t PATTERN_2
= ~PATTERN_1
;
539 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
))
542 uint8_t ram_0
= z80_read(0);
543 uint8_t ram_1
= z80_read(1);
545 z80_write(0, ram_0
^ 0xff);
547 if ((z80_read(0) ^ ram_0
) != 0xff) {
550 z80_write(0, PATTERN_1
);
551 for (addr
=1; addr
< CONFIG_SYS_RAMSIZE_MAX
; addr
<<= 1) {
552 uint8_t ram_i
= z80_read(addr
);
553 z80_write(addr
, PATTERN_2
);
554 if (z80_read(0) != PATTERN_1
|| z80_read(addr
) != PATTERN_2
)
556 z80_write(addr
, ram_i
);
561 z80_bus_cmd(Release
);
566 /*--------------------------------------------------------------------------*/
568 void z80_write(uint32_t addr
, uint8_t data
)
570 z80_setaddress(addr
);
581 uint8_t z80_read(uint32_t addr
)
585 z80_setaddress(addr
);
599 void z80_memset(uint32_t addr
, uint8_t data
, uint32_t length
)
605 z80_setaddress(addr
++);
613 void z80_write_block_P(const FLASH
uint8_t *src
, uint32_t dest
, uint32_t length
)
620 z80_setaddress(dest
++);
631 void z80_write_block(const uint8_t *src
, uint32_t dest
, uint32_t length
)
638 z80_setaddress(dest
++);
649 void z80_read_block (uint8_t *dest
, uint32_t src
, size_t length
)
656 z80_setaddress(src
++);
667 /*--------------------------------------------------------------------------*/
670 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
671 017A' rx.in_idx: ds 1 ;
672 017B' rx.out_idx: ds 1 ;
673 017C' rx.buf: ds rx.buf_len ;
674 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
676 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
677 018D' tx.in_idx: ds 1 ;
678 018E' tx.out_idx: ds 1 ;
679 018F' tx.buf: ds tx.buf_len ;
680 019E' tx.buf_end equ $-1 ; last byte
684 typedef struct __attribute__((packed
)) {
693 #define FIFO_BUFSIZE_MASK -3
694 #define FIFO_INDEX_IN -2
695 #define FIFO_INDEX_OUT -1
703 } fifo_dsc
[NUM_FIFOS
];
706 void z80_memfifo_init(const fifo_t f
, uint32_t addr
)
708 fifo_dsc
[f
].base
= addr
;
712 z80_bus_cmd(Request
);
713 fifo_dsc
[f
].mask
= z80_read(addr
+ FIFO_BUFSIZE_MASK
);
714 fifo_dsc
[f
].idx_in
= z80_read(addr
+ FIFO_INDEX_IN
);
715 fifo_dsc
[f
].idx_out
= z80_read(addr
+ FIFO_INDEX_OUT
);
716 z80_bus_cmd(Release
);
718 if (fifo_dsc
[f
].idx_in
!= 0 || fifo_dsc
[f
].idx_out
!= 0) {
719 DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
720 f
, addr
, fifo_dsc
[f
].idx_in
, fifo_dsc
[f
].idx_out
, fifo_dsc
[f
].mask
);
726 int z80_memfifo_is_empty(const fifo_t f
)
730 if (fifo_dsc
[f
].base
!= 0) {
732 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
735 z80_bus_cmd(Request
);
737 z80_bus_cmd(Release
);
738 rc
= idx
== fifo_dsc
[f
].idx_out
;
744 int z80_memfifo_is_full(const fifo_t f
)
748 if (fifo_dsc
[f
].base
!= 0) {
749 z80_bus_cmd(Request
);
750 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
751 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
752 z80_bus_cmd(Release
);
758 uint8_t z80_memfifo_getc_wait(const fifo_t f
)
762 while (z80_memfifo_is_empty(f
))
765 z80_bus_cmd(Request
);
766 idx
= fifo_dsc
[f
].idx_out
;
767 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
768 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
769 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
770 z80_bus_cmd(Release
);
775 int z80_memfifo_getc(const fifo_t f
)
779 if (fifo_dsc
[f
].base
!= 0) {
780 uint8_t idx
= fifo_dsc
[f
].idx_out
;
781 z80_bus_cmd(Request
);
782 if (idx
!= z80_read(fifo_dsc
[f
].base
+ FIFO_INDEX_IN
)) {
783 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
784 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
785 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
787 z80_bus_cmd(Release
);
794 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
798 while (z80_memfifo_is_full(f
))
801 z80_bus_cmd(Request
);
802 idx
= fifo_dsc
[f
].idx_in
;
803 z80_write(fifo_dsc
[f
].base
+idx
, val
);
804 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
805 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
806 z80_bus_cmd(Release
);
809 /*--------------------------------------------------------------------------*/
811 void z80_load_mem(int_fast8_t verbosity
,
812 const FLASH
unsigned char data
[],
813 const FLASH
unsigned long *sections
,
814 const FLASH
unsigned long address
[],
815 const FLASH
unsigned long length_of_sections
[])
817 uint32_t sec_base
= 0;
820 printf_P(PSTR("Loading Z180 memory... \n"));
822 for (unsigned sec
= 0; sec
< *sections
; sec
++) {
824 printf_P(PSTR(" From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n"),
826 address
[sec
]+length_of_sections
[sec
] - 1,
827 length_of_sections
[sec
]);
830 z80_write_block_P((const FLASH
unsigned char *) &data
[sec_base
], /* src */
831 address
[sec
], /* dest */
832 length_of_sections
[sec
]); /* len */
833 sec_base
+= length_of_sections
[sec
];