]>
cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
2 * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
4 * SPDX-License-Identifier: GPL-2.0
11 * | Z180-Sig | AVR-Port | Dir |
12 * +------------+---------------+-------+
44 * | BUSREQ | PD 7 | O |
45 * | BUSACK | PD 6 | I |
48 * +------------------------------------+
57 #include <util/atomic.h>
63 //#define P_ZCLK PORTB
65 //#define DDR_ZCLK DDRB
73 #define P_BUSREQ PORTD
75 #define PIN_BUSREQ PIND
76 #define DDR_BUSREQ DDRD
77 #define P_BUSACK PORTD
78 #define PIN_BUSACK PIND
80 #define DDR_BUSACK DDRD
101 //#define ADB_PORT PORTE
104 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
105 #define Z80_O_MREQ SBIT(P_MREQ, 4)
106 #define Z80_O_RD SBIT(P_RD, 3)
107 #define Z80_O_WR SBIT(P_WR, 2)
108 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
109 #define Z80_I_BUSREQ SBIT(PIN_BUSREQ, 7)
110 //#define Z80_O_NMI SBIT(P_NMI, )
111 #define Z80_O_RST SBIT(P_RST, 5)
112 #define Z80_I_RST SBIT(PIN_RST, 5)
113 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
114 //#define Z80_I_HALT SBIT(P_HALT, )
122 #define DDR_STEP DDRG
125 #define DDR_WAIT DDRG
126 /* All three signals are on the same Port (PortG) */
127 #define PORT_SS PORTG
130 #define Z80_O_RUN SBIT(PORT_SS, RUN)
131 #define Z80_O_STEP SBIT(PORT_SS, STEP)
132 #define Z80_I_WAIT SBIT(PORT_SS, WAIT)
138 #define MASK(n) ((1<<(n))-1)
139 #define SMASK(w,s) (MASK(w) << (s))
141 void z80_bus_request_or_exit(void)
143 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
))
144 cmd_error(CMD_RET_FAILURE
, EBUSTO
, NULL
);
147 static zstate_t zstate
;
148 static volatile uint8_t timer
; /* used for bus timeout */
151 static volatile uint16_t busack_cycles_ovl
;
153 static uint32_t busack_cycles
;
155 ISR(TIMER4_COMPB_vect
)
160 /*---------------------------------------------------------*/
161 /* 10Hz timer interrupt generated by OC5A */
162 /*---------------------------------------------------------*/
164 ISR(TIMER5_COMPA_vect
)
173 /*--------------------------------------------------------------------------*/
176 static void z80_addrbus_set_in(void)
178 /* /MREQ, /RD, /WR: Input, no pullup */
179 DDR_MREQ
&= ~(_BV(MREQ
) | _BV(RD
) | _BV(WR
));
188 PIN_ADB
= P_ADB
& (MASK(ADB_WIDTH
) << ADB_SHIFT
);
189 DDR_ADB
= DDR_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
193 static void z80_addrbus_set_out(void)
195 /* /MREQ, /RD, /WR: Output and high */
199 DDR_MREQ
|= _BV(MREQ
) | _BV(RD
) | _BV(WR
);
203 DDR_ADB
= DDR_ADB
| (MASK(ADB_WIDTH
) << ADB_SHIFT
);
207 static void z80_dbus_set_in(void)
214 static void z80_dbus_set_out(void)
219 static void z80_reset_active(void)
221 if (Stat
& S_RESET_POLARITY
)
227 static void z80_reset_inactive(void)
229 if (Stat
& S_RESET_POLARITY
)
235 static void z80_reset_pulse(void)
239 z80_reset_inactive();
243 void z80_setup_bus(void)
245 ATOMIC_BLOCK(ATOMIC_RESTORESTATE
) {
247 /* /ZRESET: Input, no pullup */
248 DDR_RST
&= ~_BV(RST
);
251 /* /BUSREQ: Output and high */
253 DDR_BUSREQ
|= _BV(BUSREQ
);
255 /* /BUSACK: Input, no pullup */
256 DDR_BUSACK
&= ~_BV(BUSACK
);
257 P_BUSACK
&= ~_BV(BUSACK
);
259 z80_addrbus_set_in();
262 if (getenv_yesno(PSTR(ENV_SINGLESTEP
))) {
263 /* /RUN & /STEP: output, /WAIT: input */
265 PORT_SS
= (PORT_SS
& ~_BV(RUN
)) | _BV(STEP
);
266 DDR_SS
= (DDR_SS
& ~_BV(WAIT
)) | _BV(RUN
) | _BV(STEP
);
270 Stat
|= S_RESET_POLARITY
;
272 Stat
&= ~S_RESET_POLARITY
;
280 PRR1
&= ~_BV(PRTIM5
);
281 OCR5A
= F_CPU
/ 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
282 TCCR5B
= (0b01<<WGM52
)|(0b101<<CS40
); /* CTC Mode, Prescaler 1024 */
283 TIMSK5
= _BV(OCIE5A
); /* Enable oca interrupt */
288 uint32_t z80_get_busreq_cycles(void)
290 return busack_cycles
;
293 zstate_t
z80_bus_state(void)
298 void z80_toggle_reset(void)
303 void z80_toggle_busreq(void)
309 static void z80_busreq_hpulse(void)
312 z80_addrbus_set_in();
315 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
317 Z80_O_BUSREQ
= 1; /* 2 AVR clock cycles */
318 Z80_O_BUSREQ
= 0; /* 2 AVR clock cycles */
323 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
327 if (Z80_I_BUSACK
== 1) {
335 if (zstate
& ZST_ACQUIRED
) {
337 while (Z80_I_BUSACK
== 1 && timer
)
339 if (Z80_I_BUSACK
== 0)
340 z80_addrbus_set_out();
348 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
352 ----------------+---------------+---------------+---------------+---------------+
354 Reset | 0 | 0 | 0 | 0 |
357 Request | 1 | | 3 | |
360 Release | | 0 | | 2 |
366 Restart | | | 2 | 3 |
374 zstate_t
z80_bus_cmd(bus_cmd_t cmd
)
380 z80_addrbus_set_in();
385 while (Z80_I_BUSACK
== 0 && timer
)
394 timer
= 255; //BUS_TO;
400 busack_cycles_ovl
= 0;
401 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
402 //z80_reset_inactive();
403 Z80_I_RST
= 1; /* Toggle RESET --> inactive */
405 TIFR4
= _BV(OCF4B
); /* Clear compare match flag */
407 TIMSK4
|= _BV(OCIE4B
); /* Enable compare match interrupt */
409 while (Z80_I_BUSACK
== 1 && timer
)
412 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
413 tcnt
= TCNT4
- OCR4B
;
414 ovl_cnt
= busack_cycles_ovl
;
416 TIMSK4
&= ~_BV(OCIE4B
); /* Disable compare match interrupt */
418 if (Z80_I_BUSACK
== 0) {
419 if ((ifr
& _BV(OCF4B
)) && !(tcnt
& (1<<15)))
421 busack_cycles
= tcnt
+ ((uint32_t) ovl_cnt
<< 16);
422 z80_addrbus_set_out();
424 // debug("### ovl: %u, ifr: %u, beg: %u, end: %u\n", ovl_cnt,
425 // (ifr & _BV(OCF4B)) != 0, OCR4B, tcnt);
435 while (Z80_I_BUSACK
== 1 && timer
)
437 if (Z80_I_BUSACK
== 0) {
438 z80_addrbus_set_out();
439 zstate
= RUNNING_AQRD
;
454 z80_addrbus_set_in();
459 while (Z80_I_BUSACK
== 0 && timer
)
465 z80_addrbus_set_in();
468 while (Z80_I_BUSACK
== 0 && timer
)
480 _delay_ms(20); /* TODO: */
481 z80_reset_inactive();
487 z80_addrbus_set_in();
489 z80_addrbus_set_out();
490 zstate
= RUNNING_AQRD
;
511 z80_busreq_hpulse(); /* TODO: */
521 /*--------------------------------------------------------------------------*/
524 //inline __attribute__ ((always_inline))
525 void z80_setaddress(uint32_t addr
)
528 P_ADH
= (addr
& 0xff00) >> 8;
529 PIN_ADB
= (((addr
>> 16) << ADB_SHIFT
) ^ P_ADB
) & MASK(ADB_WIDTH
) << ADB_SHIFT
;
532 int32_t z80_memsize_detect(void)
534 const uint8_t PATTERN_1
= 0x55;
535 const uint8_t PATTERN_2
= ~PATTERN_1
;
538 if (!(z80_bus_cmd(Request
) & ZST_ACQUIRED
))
541 uint8_t ram_0
= z80_read(0);
542 uint8_t ram_1
= z80_read(1);
544 z80_write(0, ram_0
^ 0xff);
546 if ((z80_read(0) ^ ram_0
) != 0xff) {
549 z80_write(0, PATTERN_1
);
550 for (addr
=1; addr
< CONFIG_SYS_RAMSIZE_MAX
; addr
<<= 1) {
551 uint8_t ram_i
= z80_read(addr
);
552 z80_write(addr
, PATTERN_2
);
553 if (z80_read(0) != PATTERN_1
|| z80_read(addr
) != PATTERN_2
)
555 z80_write(addr
, ram_i
);
560 z80_bus_cmd(Release
);
565 /*--------------------------------------------------------------------------*/
567 void z80_write(uint32_t addr
, uint8_t data
)
569 z80_setaddress(addr
);
580 uint8_t z80_read(uint32_t addr
)
584 z80_setaddress(addr
);
598 void z80_memset(uint32_t addr
, uint8_t data
, uint32_t length
)
604 z80_setaddress(addr
++);
612 void z80_write_block_P(const FLASH
uint8_t *src
, uint32_t dest
, uint32_t length
)
619 z80_setaddress(dest
++);
630 void z80_write_block(const uint8_t *src
, uint32_t dest
, uint32_t length
)
637 z80_setaddress(dest
++);
648 void z80_read_block (uint8_t *dest
, uint32_t src
, size_t length
)
655 z80_setaddress(src
++);
666 /*--------------------------------------------------------------------------*/
669 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
670 017A' rx.in_idx: ds 1 ;
671 017B' rx.out_idx: ds 1 ;
672 017C' rx.buf: ds rx.buf_len ;
673 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
675 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
676 018D' tx.in_idx: ds 1 ;
677 018E' tx.out_idx: ds 1 ;
678 018F' tx.buf: ds tx.buf_len ;
679 019E' tx.buf_end equ $-1 ; last byte
683 typedef struct __attribute__((packed
)) {
692 #define FIFO_BUFSIZE_MASK -3
693 #define FIFO_INDEX_IN -2
694 #define FIFO_INDEX_OUT -1
702 } fifo_dsc
[NUM_FIFOS
];
705 void z80_memfifo_init(const fifo_t f
, uint32_t addr
)
707 fifo_dsc
[f
].base
= addr
;
711 z80_bus_cmd(Request
);
712 fifo_dsc
[f
].mask
= z80_read(addr
+ FIFO_BUFSIZE_MASK
);
713 fifo_dsc
[f
].idx_in
= z80_read(addr
+ FIFO_INDEX_IN
);
714 fifo_dsc
[f
].idx_out
= z80_read(addr
+ FIFO_INDEX_OUT
);
715 z80_bus_cmd(Release
);
717 if (fifo_dsc
[f
].idx_in
!= 0 || fifo_dsc
[f
].idx_out
!= 0) {
718 DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
719 f
, addr
, fifo_dsc
[f
].idx_in
, fifo_dsc
[f
].idx_out
, fifo_dsc
[f
].mask
);
725 int z80_memfifo_is_empty(const fifo_t f
)
729 if (fifo_dsc
[f
].base
!= 0) {
731 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
734 z80_bus_cmd(Request
);
736 z80_bus_cmd(Release
);
737 rc
= idx
== fifo_dsc
[f
].idx_out
;
743 int z80_memfifo_is_full(const fifo_t f
)
747 if (fifo_dsc
[f
].base
!= 0) {
748 z80_bus_cmd(Request
);
749 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
750 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
751 z80_bus_cmd(Release
);
757 uint8_t z80_memfifo_getc_wait(const fifo_t f
)
761 while (z80_memfifo_is_empty(f
))
764 z80_bus_cmd(Request
);
765 idx
= fifo_dsc
[f
].idx_out
;
766 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
767 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
768 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
769 z80_bus_cmd(Release
);
774 int z80_memfifo_getc(const fifo_t f
)
778 if (fifo_dsc
[f
].base
!= 0) {
779 uint8_t idx
= fifo_dsc
[f
].idx_out
;
780 z80_bus_cmd(Request
);
781 if (idx
!= z80_read(fifo_dsc
[f
].base
+ FIFO_INDEX_IN
)) {
782 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
783 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
784 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
786 z80_bus_cmd(Release
);
793 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
797 while (z80_memfifo_is_full(f
))
800 z80_bus_cmd(Request
);
801 idx
= fifo_dsc
[f
].idx_in
;
802 z80_write(fifo_dsc
[f
].base
+idx
, val
);
803 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
804 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
805 z80_bus_cmd(Release
);
808 /*--------------------------------------------------------------------------*/
810 void z80_load_mem(int_fast8_t verbosity
,
811 const FLASH
unsigned char data
[],
812 const FLASH
unsigned long *sections
,
813 const FLASH
unsigned long address
[],
814 const FLASH
unsigned long length_of_sections
[])
816 uint32_t sec_base
= 0;
819 printf_P(PSTR("Loading Z180 memory... \n"));
821 for (unsigned sec
= 0; sec
< *sections
; sec
++) {
823 printf_P(PSTR(" From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n"),
825 address
[sec
]+length_of_sections
[sec
] - 1,
826 length_of_sections
[sec
]);
829 z80_write_block_P((const FLASH
unsigned char *) &data
[sec_base
], /* src */
830 address
[sec
], /* dest */
831 length_of_sections
[sec
]); /* len */
832 sec_base
+= length_of_sections
[sec
];