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Version 0.6.8.2
[z180-stamp.git] / z180 / init.180
1 page 255
2 .z80
3
4 extrn ddtz,bpent
5 extrn $stack
6 extrn charini,?const,?conin
7 extrn ?cono,?conos
8 extrn romend
9
10
11 global iobyte
12 global isv_sw
13
14 include config.inc
15 if CPU_Z180
16 include z180reg.inc
17 include z180.lib
18 endif
19
20
21
22
23 ;----------------------------------------------------------------------
24
25 cseg
26 romstart equ $
27
28 org romstart+0
29 jp start
30
31 iobyte: db 2
32
33 ; restart vectors
34
35 rsti defl 1
36 rept 7
37 org 8*rsti + romstart
38 jp bpent
39 rsti defl rsti+1
40 endm
41
42 ;----------------------------------------------------------------------
43 ; Config space
44 ;
45
46 org romstart+40h
47
48 dw 0
49 db 0
50
51
52 if ROMSYS
53 $crom: defb c$rom ;
54 else
55 db 0 ;
56 endif
57
58 INIWAITS defl CWAITIO
59 if ROMSYS
60 INIWAITS defl INIWAITS+CWAITROM
61 endif
62
63 ;----------------------------------------------------------------------
64
65 org romstart+50h
66 start:
67 jp cstart
68 jp wstart
69 jp ?const
70 jp ?conin
71 jp ?cono
72 jp ?conos
73 jp charini
74
75 ;----------------------------------------------------------------------
76
77 hwini0:
78 if CPU_Z180
79 db ;count
80 db rcr,CREFSH ;configure DRAM refresh
81 db dcntl,INIWAITS ;wait states
82 db cbr,SYS$CBR
83 db cbar,SYS$CBAR
84 endif
85 db 0
86
87 if CPU_Z180
88 dmclrt: ;clear ram per dma
89 db dmct_e-dmclrt-2 ;
90 db sar0l ;first port
91 dw nullbyte ;src (fixed)
92 nullbyte:
93 db 000h ;src
94 dw romend ;dst (inc), start after "rom" code
95 db 00h ;dst
96 dw 0-romend ;count (64k)
97 dmct_e:
98 db 0
99 endif
100
101
102 cstart:
103 if CPU_Z180
104
105 push af
106 in0 a,(itc) ;Illegal opcode trap?
107 jp m,??st01
108 ld a,i ;I register == 0 ?
109 jr z,hw_reset ; yes, harware reset
110
111 ??st01:
112 ; TODO: SYS$CBR
113 ld a,(syscbr)
114 out0 (cbr),a
115 pop af ;restore registers
116 jp bpent ;
117
118 hw_reset:
119 di ;0058
120 ld a,CREFSH
121 out0 (rcr),a ; configure DRAM refresh
122 ld a,CWAITIO
123 out0 (dcntl),a ; wait states
124
125 ld a,M_NCD ;No Clock Divide
126 out0 (ccr),a
127 ; ld a,M_X2CM ;X2 Clock Multiplier
128 ; out0 (cmr),a
129 else
130 di
131 xor a
132 ld (@cbnk),a
133 endif
134
135 ; check warm start mark
136
137 ld ix,mark_55AA ; top of common area
138 ld a,0aah ;
139 cp (ix+000h) ;
140 jr nz,kstart ;
141 cp (ix+002h) ;
142 jr nz,kstart ;
143 cpl ;
144 cp (ix+001h) ;
145 jr nz,kstart ;
146 cp (ix+003h) ;
147 jr nz,kstart ;
148 ld sp,$stack ; mark found, check
149 jp z,wstart ; check ok,
150
151 ; ram not ok, initialize -- kstart --
152
153 kstart:
154 if CPU_Z180
155 ld a,SYS$CBR ;TODO:
156 out0 (cbr),a
157 ld a,SYS$CBAR
158 out0 (cbar),a
159 endif
160
161 ld sp,$stack ;01e1
162
163 ; Clear RAM using DMA0
164
165 if CPU_Z180
166 if 0
167
168 ld hl,dmclrt ;load DMA registers
169 call ioiniml
170 ld a,0cbh ;01ef dst +1, src fixed, burst
171 out0 (dmode),a ;01f1
172
173 ld b,512/64
174 ld a,062h ;01f4 enable dma0,
175 ??cl_1:
176 out0 (dstat),a ;01f9 clear (up to) 64k
177 djnz ??cl_1 ; end of RAM?
178
179 endif
180 endif
181
182 ld hl,055AAh ;set warm start mark
183 ld (mark_55AA),hl
184 ld (mark_55AA+2),hl
185
186 ; -- wstart --
187
188 wstart:
189 call sysram_init
190 call ivtab_init
191 if CPU_Z180
192 ; call prt0_init
193 endif
194
195 call msginit
196 call charini
197
198 if CPU_Z80
199 ld a,0
200 call selbnk
201 endif
202
203 ld a,INIDONEVAL ;tell others (CP/M) that hardware and fifos
204 ld (INIDONE),a ; are allready initialized
205
206 im 2
207 ei
208
209 call ?const
210 call ?const
211 or a
212 call nz,?conin
213
214 if CPU_Z180
215 ld e,0 ;Sys$Bank
216 else
217 ; TODO:
218 endif
219 jp ddtz
220
221
222 if CPU_Z180
223 ; TODO: SYS$CBR
224 syscbr: db 0
225 endif
226
227 ;
228 ;----------------------------------------------------------------------
229 ;
230
231 global bufinit
232
233 bufinit:
234 ld (ix+o.in_idx),0 ;reset pointers (empty fifo)
235 ld (ix+o.out_idx),0
236 ld a,(ix+o.id)
237 ld hl,fifolst
238 ld e,a
239 ld d,0
240 add hl,de
241 add hl,de
242 push ix
243 pop de
244 cp 4
245 jr nc,bfi_skip
246
247 ld (hl),e
248 inc hl
249 ld (hl),d
250
251 bfi_skip:
252 ex de,hl
253 call hwl2phy ;get phys. address of fifo
254 ld c,a
255 ld a,(ix+o.id) ;fifo id
256 or a ;test if fifo 0
257 ret z
258
259 ld b,a
260 push bc ;c: bank-addr, b: ignored
261 push hl ;address
262 ld c,0
263 push bc ;c: function, b:subf
264 ld b,5
265 ld h,c
266 ld l,c
267 add hl,sp
268 call msg.sm
269 pop hl
270 pop hl
271 pop hl
272 ret
273
274 public fifolst
275 fifolst :
276 rept 4
277 dw 0
278 endm
279
280 ;----------------------------------------------------------------------
281
282 extrn msg.sm
283 extrn msginit,msg.sout
284 extrn mtx.fifo,mrx.fifo
285 extrn ff.init,co.fifo,ci.fifo
286
287
288 fifoinit:
289 if CPU_Z180
290
291 ret
292
293 else ;CPU_Z180
294
295 call msginit
296
297 ld hl,buffers
298 ld b,buftablen
299 bfi_1:
300 ld a,(hl)
301 inc hl
302 ld (bufdat+0),a
303 ld e,(hl)
304 inc hl
305 ld d,(hl)
306 inc hl
307 ex de,hl
308
309 or a
310 jr nz,bfi_2
311
312 ld a,(@cbnk)
313 call bnk2phy
314
315 ld (40h+0),hl
316 ld (40h+2),a
317 out (AVRINT5),a
318 jr bfi_3
319 bfi_2:
320
321 ld a,(@cbnk)
322 call bnk2phy
323
324 ld (bufdat+1),hl
325 ld (bufdat+3),a
326 ld hl,inimsg
327 call msg.sout
328 bfi_3:
329 ex de,hl
330 djnz bfi_1
331 ret
332 endif
333
334
335
336
337 ;
338 ;----------------------------------------------------------------------
339 ;
340
341 sysram_init:
342 ld hl,sysramw
343 ld de,topcodsys
344 ld bc,sysrame-sysramw
345 ldir
346
347 ret
348
349 ;----------------------------------------------------------------------
350
351 ivtab_init:
352 ld hl,ivtab ;
353 ld a,h ;
354 ld i,a ;
355 if CPU_Z180
356 out0 (il),l ;
357 endif
358
359 ; Let all vectors point to spurious int routines.
360
361 ld d,high sp.int0
362 ld a,low sp.int0
363 ld b,9
364 ivt_i1:
365 ld (hl),a
366 inc l
367 ld (hl),d
368 inc l
369 add a,sp.int.len
370 djnz ivt_i1
371 ret
372
373 ;----------------------------------------------------------------------
374
375 ; Reload value for 10 ms Int. (0.1KHz):
376 ; tc10ms = phi/prescale/0.1KHz = phi / (prescale/10)
377
378 PRT_TC10MS equ 18432 / (PRT_PRE/10)
379
380
381 if CPU_Z180
382 prt0_init:
383 ld a,i
384 ld h,a
385 in0 a,(il)
386 and 0E0h
387 or IV$PRT0
388 ld l,a
389 ld (hl),low iprt0
390 inc hl
391 ld (hl),high iprt0
392 ld hl,prt0itab
393 call ioiniml
394 ret
395
396 prt0itab:
397 db prt0it_e-prt0itab-2
398 db tmdr0l
399 dw PRT_TC10MS
400 dw PRT_TC10MS
401 db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.
402 prt0it_e:
403 db 0
404 endif
405
406
407 ;
408 ;----------------------------------------------------------------------
409 ;
410
411 if CPU_Z180
412 io.ini:
413 if 0
414 push bc
415 ld b,0 ;high byte port adress
416 ioi_nxt:
417 ld a,(hl) ;count
418 inc hl
419 or a
420 jr z,ioi_e
421
422 ld c,(hl) ;port address
423 inc hl
424 ioi_r:
425 outi
426 inc b ;outi decrements b
427 dec a
428 jr nz,ioi_r
429 jr ioi_nxt
430 ioi_e:
431 pop bc
432 ret
433
434 else ;(if 1/0)
435
436 push bc
437 jr ioi_nxt
438 ioi_l:
439 ld c,(hl) ;port address
440 inc hl
441 inc c
442 ioi_r:
443 dec c ;otim increments c
444 otim
445 jr z,ioi_r
446 ioi_nxt:
447 ld b,(hl) ;count
448 inc hl
449 inc b ;stop if count == 0
450 djnz ioi_l
451 pop bc
452 ret
453
454 endif ;(1/0)
455
456 else
457
458 io.ini:
459 push bc
460 jr ioi_nxt
461 ioi_l:
462 ld c,(hl) ;port address
463 inc hl
464 otir
465 ioi_nxt:
466 ld b,(hl) ;count
467 inc hl
468 inc b
469 djnz ioi_l
470 endif
471 pop bc
472 ret
473
474 ;----------------------------------------------------------------------
475
476 if CPU_Z180
477
478 global ioiniml
479
480 ioiniml:
481 push bc
482 xor a
483 ioml_lp:
484 ld b,(hl)
485 inc hl
486 cp b
487 jr z,ioml_e
488
489 ld c,(hl)
490 inc hl
491 otimr
492 jr ioml_lp
493 ioml_e:
494 pop bc
495 ret z
496 endif
497
498 io.ini.l:
499 ;
500
501
502
503 ;----------------------------------------------------------------------
504 ;
505 if CPU_Z180
506
507 ;--------------------------------------------------------------------
508 ; Return the BBR value for the given bank number
509 ;
510 ; in a: Bank number
511 ; out a: bbr value
512
513 bnk2log:
514 or a ;
515 ret z ; Bank 0 is at physical address 0
516
517 push bc ;
518 ld b,a ;
519 ld c,CA ;
520 mlt bc ;
521 ld a,c ;
522 add a,10h ;
523 pop bc ;
524 ret ;
525
526 ;--------------------------------------------------------------
527
528 ;in hl: Log. Address
529 ; a: Bank number
530 ;
531 ;out ahl: Phys. (linear) Address
532
533
534 bnk2phy:
535 call bnk2log
536 ; fall thru
537
538 ;--------------------------------------------------------------
539 ;
540 ; hl: Log. Address
541 ; a: Bank base (bbr)
542 ;
543 ; 2 0 0
544 ; 0 6 8 0
545 ; hl hhhhhhhhllllllll
546 ; a + bbbbbbbb
547 ;
548 ; OP: ahl = (a<<12) + (h<<8) + l
549 ;
550 ;out ahl: Phys. (linear) Address
551
552 log2phy:
553 push bc ;
554 l2p_i:
555 ld c,a ;
556 ld b,16 ;
557 mlt bc ; bc = a<<4
558 ld a,c ;
559 add a,h ;
560 ld h,a ;
561 ld a,b ;
562 adc a,0 ;
563 pop bc ;
564 ret ;
565
566 ;--------------------------------------------------------------
567 ;
568 ; hl: Log. Address
569 ;
570 ;
571 ; OP: ahl = (bankbase<<12) + (d<<8) + e
572 ;
573 ;out ahl: Phys. (linear) Address
574
575 public hwl2phy
576
577 hwl2phy:
578 push bc ;
579 in0 c,(cbar) ;
580 ld a,h ;
581 or 00fh ; log. addr in common1?
582 cp c
583 jr c,hlp_1
584
585 in0 a,(cbr) ; yes, cbr is address base
586 jr hl2p_x
587 hlp_1:
588 ld b,16 ; log. address in baked area?
589 mlt bc
590 ld a,h
591 cp c
592 jr c,hlp_2
593 in0 a,(bbr) ; yes, bbr is address base
594 jr hl2p_x
595 hlp_2:
596 xor a ; common1
597 hl2p_x:
598 jr nz,l2p_i
599
600 pop bc ; bank part is 0, no translation
601 ret ;
602
603
604
605 else ;CPU_Z180
606
607 ;----------------------------------------------------------------------
608 ;
609
610 bnk2phy:
611 sla h
612 jr nc,b2p_1 ;A15=1 --> common
613 ld a,3
614 b2p_1:
615 srl a
616 rr h
617 ret
618
619 endif
620
621 ;--------------------------------------------------------------
622 ;
623 ;return:
624 ; hl = hl + a
625 ; Flags undefined
626 ;
627
628 add_hl_a:
629 add a,l
630 ld l,a
631 ret nc
632 inc h
633 ret
634
635 ; ---------------------------------------------------------
636
637 sysramw:
638
639 .phase isvsw_loc
640 topcodsys:
641
642 ; Trampoline for interrupt routines in banked ram.
643 ; Switch stack pointer to "system" stack in top ram
644 ; Save cbar
645
646 isv_sw: ;
647 ex (sp),hl ;save hl, 'return adr' in hl
648 push de ;
649 push af ;
650 ex de,hl ;'return address' in de
651 ld hl,0 ;
652 add hl,sp ;
653 ld a,h ;
654 cp 0f8h ;
655 jr nc,isw_1 ;stack allready in top ram
656 ld sp,$stack ;
657 isw_1:
658 push hl ;save user stack pointer
659 in0 h,(cbar) ;
660 push hl ;
661 ld a,SYS$CBAR ;
662 out0 (cbar),a ;
663 ex de,hl ;
664 ld e,(hl) ;
665 inc hl ;
666 ld d,(hl) ;
667 ex de,hl ;
668 push bc ;
669 call jphl ;
670
671 pop bc ;
672 pop hl ;
673 out0 (cbar),h ;
674 pop hl ;
675 ld sp,hl ;
676 pop af ;
677 pop de ;
678 pop hl ;
679 ei ;
680 ret ;
681 jphl:
682 jp (hl) ;
683
684 ; ---------------------------------------------------------
685
686 if CPU_Z180
687
688 iprt0:
689 push af
690 push hl
691 in0 a,(tcr)
692 in0 a,(tmdr0l)
693 in0 a,(tmdr0h)
694 ld a,(tim_ms)
695 inc a
696 cp 100
697 jr nz,iprt_1
698 xor a
699 ld hl,(tim_s)
700 inc hl
701 ld (tim_s),hl
702 iprt_1:
703 ld (tim_ms),a
704 pop hl
705 pop af
706 ei
707 ret
708
709 endif
710
711 ; ---------------------------------------------------------
712
713 sp.int0:
714 ld a,0d0h
715 jr sp.i.1
716 sp.int.len equ $-sp.int0
717 ld a,0d1h
718 jr sp.i.1
719 ld a,0d2h
720 jr sp.i.1
721 ld a,0d3h
722 jr sp.i.1
723 ld a,0d4h
724 jr sp.i.1
725 ld a,0d5h
726 jr sp.i.1
727 ld a,0d6h
728 jr sp.i.1
729 ld a,0d7h
730 jr sp.i.1
731 ld a,0d8h
732 sp.i.1:
733 ; out (80h),a
734 halt
735
736 ; ---------------------------------------------------------
737
738 if CPU_Z80
739
740 ; Get IFF2
741 ; This routine may not be loaded in page zero
742 ;
743 ; return Carry clear, if INTs are enabled.
744 ;
745 global getiff
746 getiff:
747 xor a ;clear accu and carry
748 push af ;stack bottom := 00xxh
749 pop af
750 ld a,i ;P flag := IFF2
751 ret pe ;exit carry clear, if enabled
752 dec sp
753 dec sp ;has stack bottom been overwritten?
754 pop af
755 and a ;if not 00xxh, INTs were
756 ret nz ;actually enabled
757 scf ;Otherwise, they really are disabled
758 ret
759
760 ;----------------------------------------------------------------------
761
762 global selbnk
763
764 ; a: bank (0..2)
765
766 selbnk:
767 push bc
768 ld c,a
769 call getiff
770 push af
771
772 ld a,c
773 di
774 ld (@cbnk),a
775 ld a,5
776 out (SIOAC),a
777 ld a,(mm_sio0)
778 rla
779 srl c
780 rra
781 out (SIOAC),a
782 ld (mm_sio0),a
783
784 ld a,5
785 out (SIOBC),a
786 ld a,(mm_sio1)
787 rla
788 srl c
789 rra
790 out (SIOBC),a
791 ld (mm_sio1),a
792 pop af
793 pop bc
794 ret c ;INTs were disabled
795 ei
796 ret
797
798 ;----------------------------------------------------------------------
799
800 ; c: bank (0..2)
801
802 if 0
803
804 selbnk:
805 ld a,(@cbnk)
806 xor c
807 and 3
808 ret z ;no change
809
810 call getiff
811 push af
812 ld a,c
813 di
814 ld (@cbnk),a
815 ld a,5
816 out (SIOAC),a
817 ld a,(mm_sio0)
818 rla
819 srl c
820 rra
821 out (SIOAC),a
822 ld (mm_sio0),a
823
824 ld a,5
825 out (SIOBC),a
826 ld a,(mm_sio1)
827 rla
828 srl c
829 rra
830 out (SIOBC),a
831 ld (mm_sio1),a
832 pop af
833 ret nc ;INTs were disabled
834 ei
835 ret
836
837 endif
838
839 ;----------------------------------------------------------------------
840
841 if 0
842 ex af,af'
843 push af
844 ex af,af'
845
846 rra
847 jr nc,stbk1
848 ex af,af'
849 ld a,5
850 out (SIOAC),a
851 ld a,(mm_sio0)
852 rla
853 srl c
854 rra
855 out (SIOAC),a
856 ld (mm_sio1),a
857 ex af,af'
858
859 stbk1:
860 rra
861 jr nc,stbk2
862 ex af,af'
863 ld a,5
864 out (SIOBC),a
865 ld a,(mm_sio1)
866 rla
867 srl c
868 rra
869 out (SIOBC),a
870 ld (mm_sio1),a
871 ex af,af'
872
873 stbk2:
874 endif
875
876 global @cbnk
877 global mm_sio0, mm_sio1
878
879 @cbnk: db 0 ; current bank (0..2)
880 mm_sio0:
881 ds 1
882 mm_sio1:
883 ds 1
884
885
886 endif
887
888 ;----------------------------------------------------------------------
889
890 curph defl $
891 .dephase
892 sysrame:
893 .phase curph
894 tim_ms: db 0
895 tim_s: dw 0
896 .dephase
897
898 ;-----------------------------------------------------
899
900
901 cseg
902
903 ;.phase 0ffc0h
904 ;ivtab equ 0ffc0h ; 0ffc0h ;int vector table
905 ;.dephase
906
907 ;.phase 0fffah
908 mark_55AA equ 0 - 2 - 4 ;2 byte for trap stack
909 ;ds 4
910 ;.dephase
911
912
913 end
Z180 Stamp Monitor