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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
5 * | Z180-Sig | AVR-Port | Dir | Special Function |
6 * +------------+---------------+-------+-----------------------+
17 * | A10 | PC 2 | O | |
18 * | A11 | PC 3 | O | |
19 * | A12 | PC 4 | O | |
20 * | A13 | PC 5 | O | |
21 * | A14 | PC 6 | O | |
22 * | A15 | PC 7 | O | |
23 * | A16 | PE 2 | O | |
24 * | A17 | PE 3 | O | |
25 * | A18 | PE 4 | O | |
26 * | D0 | PF 0 | I/O | |
27 * | D1 | PF 1 | I/O | |
28 * | D2 | PF 2 | I/O | |
29 * | D3 | PF 3 | I/O | |
30 * | D4 | PF 4 | I/O | |
31 * | D5 | PF 5 | I/O | |
32 * | D6 | PF 6 | I/O | |
33 * | D7 | PF 7 | I/O | |
36 * | MREQ | PD 4 | O | |
37 * | RST | PD 5 | O | |
38 * | BUSREQ | PD 7 | O | |
39 * | BUSACK | PD 6 | I | |
40 * | IOCS1 | PE 5 | I | |
44 * | | P | | af1 USART1_TX |
45 * | | P | | af1 USART1_RX |
46 * | | P |JTDI | remap SPI1_NSS' |
47 * | | P |JTDO | remap SPI1_SCK' |
48 * | | P |JTRST | remap SPI1_MISO' |
49 * | | P | | remap SPI1_MOSI' |
50 * | | P | | af1 OSC32 |
51 * | | P | | af1 OSC32 |
57 #include <util/atomic.h>
63 /* Number of array elements */
64 #define NELEMS(x) (sizeof x/sizeof *x)
75 } __attribute__((__packed__
));
77 typedef struct bits pbit_t
;
79 #define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
82 //#define P_ZCLK PORTB
84 //#define DDR_ZCLK DDRB
92 #define P_BUSREQ PORTD
94 #define DDR_BUSREQ DDRD
95 #define P_BUSACK PORTD
96 #define PIN_BUSACK PIND
98 #define DDR_BUSACK DDRD
99 //#define P_HALT PORTA
101 #define P_IOCS1 PORTE
103 #define DDR_IOCS1 DDRE
104 //#define P_NMI PORTB
125 //#define ADB_PORT PORTE
128 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
129 #define Z80_O_MREQ SBIT(P_MREQ, 4)
130 #define Z80_O_RD SBIT(P_RD, 3)
131 #define Z80_O_WR SBIT(P_WR, 2)
132 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
133 //#define Z80_O_NMI SBIT(P_NMI, )
134 #define Z80_O_RST SBIT(P_RST, 5)
135 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
136 //#define Z80_I_HALT SBIT(P_HALT, )
139 #define MASK(n) ((1<<(n))-1)
140 #define SMASK(w,s) (MASK(w) << (s))
150 static zstate_t zstate
;
152 /*--------------------------------------------------------------------------*/
155 static void z80_addrbus_set_tristate(void)
157 /* /MREQ, /RD, /WR: Input, no pullup */
158 DDR_MREQ
&= ~(_BV(MREQ
) | _BV(RD
) | _BV(WR
));
167 PIN_ADB
= P_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
168 DDR_ADB
= DDR_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
172 static void z80_addrbus_set_active(void)
174 /* /MREQ, /RD, /WR: Output and high */
178 DDR_MREQ
|= _BV(MREQ
) | _BV(RD
) | _BV(WR
);
182 DDR_ADB
= DDR_ADB
| (MASK(ADB_WIDTH
) << ADB_SHIFT
);
186 static void z80_dbus_set_in(void)
193 static void z80_dbus_set_out(void)
199 static void z80_reset_pulse(void)
207 void z80_setup_bus(void)
209 /* /ZRESET: Output and low */
213 /* /BUSREQ: Output and high */
215 DDR_BUSREQ
|= _BV(BUSREQ
);
217 /* /BUSACK: Input, no pullup */
218 DDR_BUSACK
&= ~_BV(BUSACK
);
219 P_BUSACK
&= ~_BV(BUSACK
);
221 /* /IOCS1: Input, no pullup */
222 DDR_IOCS1
&= ~_BV(IOCS1
);
223 P_IOCS1
&= ~_BV(IOCS1
);
225 z80_addrbus_set_tristate();
232 zstate_t
z80_bus_state(void)
238 static void z80_busreq_hpulse(void)
241 z80_addrbus_set_tristate();
243 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
245 Z80_O_BUSREQ
= 1; /* 2 AVR clock cycles */
246 Z80_O_BUSREQ
= 0; /* 2 AVR clock cycles */
249 if (zstate
& ZST_ACQUIRED
) {
250 while(Z80_I_BUSACK
== 1)
252 z80_addrbus_set_active();
260 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
264 ----------------+---------------+---------------+---------------+---------------+
266 Reset | 0 | 0 | 0 | 0 |
269 Request | 1 | | 3 | |
272 Release | | 0 | | 2 |
278 Restart | | | 2 | 3 |
286 zstate_t
z80_bus_cmd(bus_cmd_t cmd
)
292 z80_addrbus_set_tristate();
303 while(Z80_I_BUSACK
== 1)
305 z80_addrbus_set_active();
311 while(Z80_I_BUSACK
== 1)
313 z80_addrbus_set_active();
314 zstate
= RUNNING_AQRD
;
326 z80_addrbus_set_tristate();
333 z80_addrbus_set_tristate();
351 z80_addrbus_set_tristate();
353 z80_addrbus_set_active();
354 zstate
= RUNNING_AQRD
;
385 /*--------------------------------------------------------------------------*/
388 //inline __attribute__ ((always_inline))
389 void z80_setaddress(uint32_t addr
)
391 addr_t x
; x
.l
= addr
;
395 PIN_ADB
= ((x
.b
[2] << ADB_SHIFT
) ^ P_ADB
) & MASK(ADB_WIDTH
) << ADB_SHIFT
;
398 void z80_write(uint32_t addr
, uint8_t data
)
400 z80_setaddress(addr
);
411 uint8_t z80_read(uint32_t addr
)
415 z80_setaddress(addr
);
429 void z80_memset(uint32_t addr
, uint8_t data
, uint32_t length
)
434 z80_setaddress(addr
++);
444 void z80_write_block(const __flash
uint8_t *src
, uint32_t dest
, uint32_t length
)
451 z80_setaddress(dest
++);
463 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
464 017A' rx.in_idx: ds 1 ;
465 017B' rx.out_idx: ds 1 ;
466 017C' rx.buf: ds rx.buf_len ;
467 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
469 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
470 018D' tx.in_idx: ds 1 ;
471 018E' tx.out_idx: ds 1 ;
472 018F' tx.buf: ds tx.buf_len ;
473 019E' tx.buf_end equ $-1 ; last byte
477 typedef struct __attribute__((packed
)) {
486 #define FIFO_BUFSIZE_MASK -3
487 #define FIFO_INDEX_IN -2
488 #define FIFO_INDEX_OUT -1
496 } fifo_dsc
[NUM_FIFOS
];
499 void z80_memfifo_init(const fifo_t f
, uint32_t addr
)
501 fifo_dsc
[f
].base
= addr
;
505 DBG_P(2, "z80_memfifo_init: %i, %lx\n", f
, addr
);
507 z80_bus_cmd(Request
);
508 fifo_dsc
[f
].mask
= z80_read(addr
+ FIFO_BUFSIZE_MASK
);
509 fifo_dsc
[f
].idx_in
= z80_read(addr
+ FIFO_INDEX_IN
);
510 fifo_dsc
[f
].idx_out
= z80_read(addr
+ FIFO_INDEX_OUT
);
511 z80_bus_cmd(Release
);
516 int z80_memfifo_is_empty(const fifo_t f
)
520 if (fifo_dsc
[f
].base
!= 0) {
522 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
525 z80_bus_cmd(Request
);
527 z80_bus_cmd(Release
);
528 rc
= idx
== fifo_dsc
[f
].idx_out
;
534 int z80_memfifo_is_full(const fifo_t f
)
538 if (fifo_dsc
[f
].base
!= 0) {
539 z80_bus_cmd(Request
);
540 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
541 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
542 z80_bus_cmd(Release
);
548 uint8_t z80_memfifo_getc_wait(const fifo_t f
)
552 while (z80_memfifo_is_empty(f
))
555 z80_bus_cmd(Request
);
556 idx
= fifo_dsc
[f
].idx_out
;
557 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
558 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
559 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
560 z80_bus_cmd(Release
);
565 int z80_memfifo_getc(const fifo_t f
)
569 if (fifo_dsc
[f
].base
!= 0) {
570 uint8_t idx
= fifo_dsc
[f
].idx_out
;
571 z80_bus_cmd(Request
);
572 if (idx
!= z80_read(fifo_dsc
[f
].base
+ FIFO_INDEX_IN
)) {
573 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
574 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
575 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
577 z80_bus_cmd(Release
);
584 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
588 while (z80_memfifo_is_full(f
))
591 z80_bus_cmd(Request
);
592 idx
= fifo_dsc
[f
].idx_in
;
593 z80_write(fifo_dsc
[f
].base
+idx
, val
);
594 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
595 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
596 z80_bus_cmd(Release
);