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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/i2c.c
3 * I2C (TWI) master interface.
7 #include <avr/interrupt.h>
17 #define debug_i2c(fmt, args...) \
18 debug_cond(DEBUG_I2C, fmt, ##args)
21 /* General TWI Master status codes */
22 #define TWI_START 0x08 /* START has been transmitted */
23 #define TWI_REP_START 0x10 /* Repeated START has been transmitted */
24 #define TWI_ARB_LOST 0x38 /* Arbitration lost */
26 /* TWI Master Transmitter status codes */
27 #define TWI_MTX_ADR_ACK 0x18 /* SLA+W has been transmitted and ACK received */
28 #define TWI_MTX_ADR_NACK 0x20 /* SLA+W has been transmitted and NACK received */
29 #define TWI_MTX_DATA_ACK 0x28 /* Data byte has been transmitted and ACK received */
30 #define TWI_MTX_DATA_NACK 0x30 /* Data byte has been transmitted and NACK received */
32 /* TWI Master Receiver status codes */
33 #define TWI_MRX_ADR_ACK 0x40 /* SLA+R has been transmitted and ACK received */
34 #define TWI_MRX_ADR_NACK 0x48 /* SLA+R has been transmitted and NACK received */
35 #define TWI_MRX_DATA_ACK 0x50 /* Data byte has been received and ACK transmitted */
36 #define TWI_MRX_DATA_NACK 0x58 /* Data byte has been received and NACK transmitted */
38 /* TWI Miscellaneous status codes */
39 #define TWI_NO_STATE 0xF8 /* No relevant state information available */
40 #define TWI_BUS_ERROR 0x00 /* Bus error due to an illegal START or STOP condition */
44 * TWINT: TWI Interrupt Flag
45 * TWEA: TWI Enable Acknowledge Bit
46 * TWSTA: TWI START Condition Bit
47 * TWSTO: TWI STOP Condition Bit
48 * TWEN: TWI Enable Bit
49 * TWIE: TWI Interrupt Enable
51 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)
52 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)| (1<<TWEA)
53 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)
56 * (1<<TWEN)| (1<<TWINT)| (1<<TWSTO)
62 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
63 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
64 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
65 * (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
68 * (1<<TWIE)|(1<<TWSTO)
74 * 0b10000000 Busy (Transmission in progress)
76 * 0b00001000 Start transmitted
77 * 0b00000100 Slave acknowledged address
78 * 0b00000010 Data byte(s) transmitted/received
79 * 0b00000001 Transmission completed
82 *----------------------------------------------------------------------
85 #define TWI_C_DISABLE 0x00
86 #define TWI_C_ENABLE (1<<TWEN)
90 typedef struct i2c_msg_s
{
92 #define XMIT_DONE (1<<0)
93 #define DATA_ACK (1<<1)
94 #define ADDR_ACK (1<<2)
96 #define TIMEOUT (1<<6)
100 uint8_t buf
[CONFIG_SYS_I2C_BUFSIZE
];
103 static volatile i2c_msg_t xmit
;
113 tmp_stat
= xmit
.stat
;
117 switch (twsr
& 0xf8) {
121 tmp_stat
= BUSY
| START
;
122 tmp_idx
= 0; /* reset xmit_buf index */
124 if (tmp_idx
< xmit
.len
) { /* all bytes transmited? */
125 TWDR
= xmit
.buf
[tmp_idx
];
127 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
);
129 tmp_stat
|= XMIT_DONE
;
131 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
135 case TWI_MTX_ADR_ACK
:
136 case TWI_MTX_DATA_ACK
:
137 if ((twsr
&0xf8) == TWI_MTX_ADR_ACK
)
138 tmp_stat
|= ADDR_ACK
;
140 tmp_stat
|= DATA_ACK
;
142 if (tmp_idx
< xmit
.len
) { /* all bytes transmited? */
143 TWDR
= xmit
.buf
[tmp_idx
];
145 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
);
147 tmp_stat
|= XMIT_DONE
;
149 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
153 case TWI_MTX_DATA_NACK
:
154 tmp_stat
|= XMIT_DONE
;
156 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
159 case TWI_MRX_DATA_ACK
:
160 xmit
.buf
[tmp_idx
] = TWDR
;
163 case TWI_MRX_ADR_ACK
:
164 if ((twsr
&0xf8) == TWI_MRX_ADR_ACK
)
165 tmp_stat
|= ADDR_ACK
;
167 tmp_stat
|= DATA_ACK
;
171 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
)|(1<<TWEA
);
173 next_twcr
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
);
177 case TWI_MRX_DATA_NACK
:
178 tmp_stat
|= ADDR_ACK
| DATA_ACK
;
180 xmit
.buf
[tmp_idx
] = TWDR
;
185 next_twcr
= (1<<TWEN
)|(0<<TWIE
)|(1<<TWINT
)|(1<<TWSTO
);
189 xmit
.stat
= tmp_stat
;
192 debug_i2c("|%02x", twsr
);
197 /*------------------------------------------------------------------*/
203 static void _init(void)
207 /* Disable TWI, disable TWI interrupt. */
208 /* (Reset TWI hardware state machine.) */
209 TWCR
= TWI_C_DISABLE
;
212 memset((void *) xmit
.buf
, 0xdf, sizeof(xmit
.buf
));
221 void i2c_init(uint32_t speed
)
224 uint32_t tmp_twbr
= F_CPU
/2 / speed
- 8;
226 while (tmp_twbr
> 255) {
230 debug_cond((twps
> 3), "*** TWCLK too low: %lu Hz\n", speed
);
232 twbr
= (uint8_t) tmp_twbr
;
239 int_fast8_t i2c_waitready(void)
241 uint32_t timer
= get_timer(0);
245 if (get_timer(timer
) >= 30) {
249 } while ((TWCR
& ((1<<TWIE
)|(1<<TWSTO
))) != 0 && !timeout
);
251 xmit
.stat
|= timeout
;
254 dump_ram((uint8_t *) &xmit
, 4, "=== i2c_wait ready: (done)");
261 int i2c_send(uint8_t chip
, uint16_t addr
, uint8_t alen
, uint8_t *buffer
, int8_t len
)
266 rc
= i2c_waitready();
267 if ((rc
& (BUSY
| TIMEOUT
)) != 0)
271 xmit
.buf
[0] = chip
<<1;
272 for (i
= 1; i
< alen
+1; i
++) {
273 xmit
.buf
[i
] = (uint8_t) addr
;
276 for (n
= len
+ i
; i
< n
; i
++)
277 xmit
.buf
[i
] = *buffer
++;
281 dump_ram((uint8_t *) &xmit
, 0x20, "=== i2c_send");
284 /* Enable TWI, TWI int and initiate start condition */
285 TWCR
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
)|(1<<TWSTA
);
293 int i2c_recv(uint8_t chip
, uint8_t *buffer
, int8_t len
)
297 rc
= i2c_waitready();
298 if ((rc
& (BUSY
| TIMEOUT
)) != 0)
303 xmit
.buf
[0] = (chip
<<1) | 1;
306 dump_ram((uint8_t *) &xmit
, 0x20, "=== i2c_recv: before start");
309 /* Enable TWI, TWI int and initiate start condition */
310 TWCR
= (1<<TWEN
)|(1<<TWIE
)|(1<<TWINT
)|(1<<TWSTA
);
311 rc
= i2c_waitready();
314 dump_ram((uint8_t *) &xmit
, 0x20, "=== i2c_recv: after completion");
318 /* at least 1 byte received */
319 for (uint8_t i
=1, n
=xmit
.idx
; i
< n
; i
++)
320 *buffer
++ = xmit
.buf
[i
];
327 * Read/Write interface:
328 * chip: I2C chip address, range 0..127
329 * addr: Memory (register) address within the chip
330 * alen: Number of bytes to use for addr (typically 1, 2 for larger
331 * memories, 0 for register type devices with only one
333 * buffer: Where to read/write the data
334 * len: How many bytes to read/write
336 * Returns: 0 on success, not 0 on failure
339 int i2c_write(uint8_t chip
, unsigned int addr
, uint_fast8_t alen
,
340 uint8_t *buffer
, uint_fast8_t len
)
344 if ((alen
> 2) || (1 + alen
+ len
> CONFIG_SYS_I2C_BUFSIZE
)) {
345 debug("** i2c_write: buffer overflow, alen: %u, len: %u\n",
350 i2c_send(chip
, addr
, alen
, buffer
, len
);
351 rc
= i2c_waitready();
353 return (rc
& XMIT_DONE
) != 0;
356 int i2c_read(uint8_t chip
, unsigned int addr
, uint_fast8_t alen
,
357 uint8_t *buffer
, uint_fast8_t len
)
361 if ((alen
> 2) || (1 + len
> CONFIG_SYS_I2C_BUFSIZE
)) {
362 debug("** i2c_read: parameter error: alen: %u, len: %u\n",
368 i2c_send(chip
, addr
, alen
, NULL
, 0);
370 rc
= i2c_recv(chip
, buffer
, len
);
372 return !((rc
& (XMIT_DONE
|DATA_ACK
)) == (XMIT_DONE
|DATA_ACK
));