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cloudbase.mooo.com Git - z180-stamp.git/blob - avr/z80-if.c
5 * | Z180-Sig | AVR-Port | Dir | Special Function |
6 * +------------+---------------+-------+-----------------------+
17 * | A10 | PC 2 | O | |
18 * | A11 | PC 3 | O | |
19 * | A12 | PC 4 | O | |
20 * | A13 | PC 5 | O | |
21 * | A14 | PC 6 | O | |
22 * | A15 | PC 7 | O | |
23 * | A16 | PE 2 | O | |
24 * | A17 | PE 3 | O | |
25 * | A18 | PE 4 | O | |
26 * | D0 | PF 0 | I/O | |
27 * | D1 | PF 1 | I/O | |
28 * | D2 | PF 2 | I/O | |
29 * | D3 | PF 3 | I/O | |
30 * | D4 | PF 4 | I/O | |
31 * | D5 | PF 5 | I/O | |
32 * | D6 | PF 6 | I/O | |
33 * | D7 | PF 7 | I/O | |
36 * | MREQ | PD 4 | O | |
37 * | RST | PD 5 | O | |
38 * | BUSREQ | PD 7 | O | |
39 * | BUSACK | PD 6 | I | |
40 * | IOCS1 | PE 5 | I | |
44 * | | P | | af1 USART1_TX |
45 * | | P | | af1 USART1_RX |
46 * | | P |JTDI | remap SPI1_NSS' |
47 * | | P |JTDO | remap SPI1_SCK' |
48 * | | P |JTRST | remap SPI1_MISO' |
49 * | | P | | remap SPI1_MOSI' |
50 * | | P | | af1 OSC32 |
51 * | | P | | af1 OSC32 |
58 #include <util/atomic.h>
64 //#define P_ZCLK PORTB
66 //#define DDR_ZCLK DDRB
74 #define P_BUSREQ PORTD
76 #define DDR_BUSREQ DDRD
77 #define P_BUSACK PORTD
78 #define PIN_BUSACK PIND
80 #define DDR_BUSACK DDRD
81 //#define P_HALT PORTA
85 #define DDR_IOCS1 DDRE
107 //#define ADB_PORT PORTE
110 //#define Z80_O_ZCLK SBIT(P_ZCLK, 5)
111 #define Z80_O_MREQ SBIT(P_MREQ, 4)
112 #define Z80_O_RD SBIT(P_RD, 3)
113 #define Z80_O_WR SBIT(P_WR, 2)
114 #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
115 //#define Z80_O_NMI SBIT(P_NMI, )
116 #define Z80_O_RST SBIT(P_RST, 5)
117 #define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
118 //#define Z80_I_HALT SBIT(P_HALT, )
124 #define MASK(n) ((1<<(n))-1)
125 #define SMASK(w,s) (MASK(w) << (s))
135 static zstate_t zstate
;
136 static volatile uint8_t timer
; /* used for bus timeout */
138 /*---------------------------------------------------------*/
139 /* 10Hz timer interrupt generated by OC4A */
140 /*---------------------------------------------------------*/
142 ISR(TIMER4_COMPA_vect
)
151 /*--------------------------------------------------------------------------*/
154 static void z80_addrbus_set_tristate(void)
156 /* /MREQ, /RD, /WR: Input, no pullup */
157 DDR_MREQ
&= ~(_BV(MREQ
) | _BV(RD
) | _BV(WR
));
166 PIN_ADB
= P_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
167 DDR_ADB
= DDR_ADB
& ~(MASK(ADB_WIDTH
) << ADB_SHIFT
);
171 static void z80_addrbus_set_active(void)
173 /* /MREQ, /RD, /WR: Output and high */
177 DDR_MREQ
|= _BV(MREQ
) | _BV(RD
) | _BV(WR
);
181 DDR_ADB
= DDR_ADB
| (MASK(ADB_WIDTH
) << ADB_SHIFT
);
185 static void z80_dbus_set_in(void)
192 static void z80_dbus_set_out(void)
198 static void z80_reset_pulse(void)
206 void z80_setup_bus(void)
208 /* /ZRESET: Output and low */
212 /* /BUSREQ: Output and high */
214 DDR_BUSREQ
|= _BV(BUSREQ
);
216 /* /BUSACK: Input, no pullup */
217 DDR_BUSACK
&= ~_BV(BUSACK
);
218 P_BUSACK
&= ~_BV(BUSACK
);
220 /* /IOCS1: Input, no pullup */
221 DDR_IOCS1
&= ~_BV(IOCS1
);
222 P_IOCS1
&= ~_BV(IOCS1
);
224 z80_addrbus_set_tristate();
230 PRR1
&= ~_BV(PRTIM4
);
231 OCR4A
= F_CPU
/ 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
232 TCCR4B
= (0b01<<WGM42
)|(0b101<<CS30
); /* CTC Mode, Prescaler 1024 */
233 TIMSK4
= _BV(OCIE4A
); /* Enable oca interrupt */
238 zstate_t
z80_bus_state(void)
244 static void z80_busreq_hpulse(void)
247 z80_addrbus_set_tristate();
249 ATOMIC_BLOCK(ATOMIC_FORCEON
) {
251 Z80_O_BUSREQ
= 1; /* 2 AVR clock cycles */
252 Z80_O_BUSREQ
= 0; /* 2 AVR clock cycles */
255 if (zstate
& ZST_ACQUIRED
) {
257 while (Z80_I_BUSACK
== 1 && timer
)
259 if (Z80_I_BUSACK
== 0)
260 z80_addrbus_set_active();
268 + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
272 ----------------+---------------+---------------+---------------+---------------+
274 Reset | 0 | 0 | 0 | 0 |
277 Request | 1 | | 3 | |
280 Release | | 0 | | 2 |
286 Restart | | | 2 | 3 |
294 zstate_t
z80_bus_cmd(bus_cmd_t cmd
)
300 z80_addrbus_set_tristate();
312 while (Z80_I_BUSACK
== 1 && timer
)
314 if (Z80_I_BUSACK
== 0) {
315 z80_addrbus_set_active();
326 while (Z80_I_BUSACK
== 1 && timer
)
328 if (Z80_I_BUSACK
== 0) {
329 z80_addrbus_set_active();
330 zstate
= RUNNING_AQRD
;
345 z80_addrbus_set_tristate();
352 z80_addrbus_set_tristate();
370 z80_addrbus_set_tristate();
372 z80_addrbus_set_active();
373 zstate
= RUNNING_AQRD
;
394 z80_busreq_hpulse(); /* TODO: */
404 /*--------------------------------------------------------------------------*/
407 //inline __attribute__ ((always_inline))
408 void z80_setaddress(uint32_t addr
)
410 addr_t x
; x
.l
= addr
;
414 PIN_ADB
= ((x
.b
[2] << ADB_SHIFT
) ^ P_ADB
) & MASK(ADB_WIDTH
) << ADB_SHIFT
;
417 void z80_write(uint32_t addr
, uint8_t data
)
419 z80_setaddress(addr
);
430 uint8_t z80_read(uint32_t addr
)
434 z80_setaddress(addr
);
448 void z80_memset(uint32_t addr
, uint8_t data
, uint32_t length
)
454 z80_setaddress(addr
++);
462 void z80_write_block_P(const FLASH
uint8_t *src
, uint32_t dest
, uint32_t length
)
469 z80_setaddress(dest
++);
480 void z80_write_block(const uint8_t *src
, uint32_t dest
, uint32_t length
)
487 z80_setaddress(dest
++);
498 void z80_read_block (uint8_t *dest
, uint32_t src
, size_t length
)
505 z80_setaddress(src
++);
518 0179' rx.bs_mask: ds 1 ; (buf_len - 1)
519 017A' rx.in_idx: ds 1 ;
520 017B' rx.out_idx: ds 1 ;
521 017C' rx.buf: ds rx.buf_len ;
522 018B' rx.buf_end equ $-1 ; last byte (start+len-1)
524 018C' tx.bs_mask: ds 1 ; (buf_len - 1)
525 018D' tx.in_idx: ds 1 ;
526 018E' tx.out_idx: ds 1 ;
527 018F' tx.buf: ds tx.buf_len ;
528 019E' tx.buf_end equ $-1 ; last byte
532 typedef struct __attribute__((packed
)) {
541 #define FIFO_BUFSIZE_MASK -3
542 #define FIFO_INDEX_IN -2
543 #define FIFO_INDEX_OUT -1
551 } fifo_dsc
[NUM_FIFOS
];
554 void z80_memfifo_init(const fifo_t f
, uint32_t addr
)
556 fifo_dsc
[f
].base
= addr
;
560 DBG_P(2, "z80_memfifo_init: %i, %lx\n", f
, addr
);
562 z80_bus_cmd(Request
);
563 fifo_dsc
[f
].mask
= z80_read(addr
+ FIFO_BUFSIZE_MASK
);
564 fifo_dsc
[f
].idx_in
= z80_read(addr
+ FIFO_INDEX_IN
);
565 fifo_dsc
[f
].idx_out
= z80_read(addr
+ FIFO_INDEX_OUT
);
566 z80_bus_cmd(Release
);
571 int z80_memfifo_is_empty(const fifo_t f
)
575 if (fifo_dsc
[f
].base
!= 0) {
577 uint32_t adr
= fifo_dsc
[f
].base
+ FIFO_INDEX_IN
;
580 z80_bus_cmd(Request
);
582 z80_bus_cmd(Release
);
583 rc
= idx
== fifo_dsc
[f
].idx_out
;
589 int z80_memfifo_is_full(const fifo_t f
)
593 if (fifo_dsc
[f
].base
!= 0) {
594 z80_bus_cmd(Request
);
595 rc
= ((fifo_dsc
[f
].idx_in
+ 1) & fifo_dsc
[f
].mask
)
596 == z80_read(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
);
597 z80_bus_cmd(Release
);
603 uint8_t z80_memfifo_getc_wait(const fifo_t f
)
607 while (z80_memfifo_is_empty(f
))
610 z80_bus_cmd(Request
);
611 idx
= fifo_dsc
[f
].idx_out
;
612 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
613 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
614 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
615 z80_bus_cmd(Release
);
620 int z80_memfifo_getc(const fifo_t f
)
624 if (fifo_dsc
[f
].base
!= 0) {
625 uint8_t idx
= fifo_dsc
[f
].idx_out
;
626 z80_bus_cmd(Request
);
627 if (idx
!= z80_read(fifo_dsc
[f
].base
+ FIFO_INDEX_IN
)) {
628 rc
= z80_read(fifo_dsc
[f
].base
+idx
);
629 fifo_dsc
[f
].idx_out
= ++idx
& fifo_dsc
[f
].mask
;
630 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_OUT
, fifo_dsc
[f
].idx_out
);
632 z80_bus_cmd(Release
);
639 void z80_memfifo_putc(fifo_t f
, uint8_t val
)
643 while (z80_memfifo_is_full(f
))
646 z80_bus_cmd(Request
);
647 idx
= fifo_dsc
[f
].idx_in
;
648 z80_write(fifo_dsc
[f
].base
+idx
, val
);
649 fifo_dsc
[f
].idx_in
= ++idx
& fifo_dsc
[f
].mask
;
650 z80_write(fifo_dsc
[f
].base
+FIFO_INDEX_IN
, fifo_dsc
[f
].idx_in
);
651 z80_bus_cmd(Release
);