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[z180-stamp.git] / avr / z180-serv.c
1 /*
2 * (C) Copyright 2014-2016 Leo C. <erbl259-lmu@yahoo.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include "common.h"
8 #include <stdlib.h>
9 #include <string.h>
10 #include <stdbool.h>
11 #include <util/atomic.h>
12
13 #include "config.h"
14 #include "background.h"
15 #include "env.h"
16 #include "ff.h"
17 #include "serial.h"
18 #include "z80-if.h"
19 #include "debug.h"
20 #include "print-utils.h"
21 #include "z180-serv.h"
22 #include "timer.h"
23 #include "time.h"
24 #include "bcd.h"
25 #include "rtc.h"
26
27 #define DEBUG_CPM_SDIO 1 /* set to 1 to debug */
28
29 #define debug_cpmsd(fmt, args...) \
30 debug_cond(DEBUG_CPM_SDIO, fmt, ##args)
31
32
33 /*--------------------------------------------------------------------------*/
34
35 struct msg_item {
36 uint8_t fct;
37 uint8_t sub_min, sub_max;
38 void (*func)(uint8_t, int, uint8_t *);
39 };
40
41 uint32_t msg_to_addr(uint8_t *msg)
42 {
43 union {
44 uint32_t as32;
45 uint8_t as8[4];
46 } addr;
47
48 addr.as8[0] = msg[0];
49 addr.as8[1] = msg[1];
50 addr.as8[2] = msg[2];
51 addr.as8[3] = 0;
52
53 return addr.as32;
54 }
55
56
57 static int msg_xmit_header(uint8_t func, uint8_t subf, int len)
58 {
59 z80_memfifo_putc(fifo_msgout, 0xAE);
60 z80_memfifo_putc(fifo_msgout, len+2);
61 z80_memfifo_putc(fifo_msgout, func);
62 z80_memfifo_putc(fifo_msgout, subf);
63
64 return 0;
65 }
66
67 int msg_xmit(uint8_t func, uint8_t subf, int len, uint8_t *msg)
68 {
69 msg_xmit_header(func, subf, len);
70 while (len--)
71 z80_memfifo_putc(fifo_msgout, *msg++);
72
73 return 0;
74 }
75
76 void do_msg_ini_memfifo(uint8_t subf, int len, uint8_t * msg)
77 {
78 (void)len;
79
80 z80_memfifo_init(subf, msg_to_addr(msg));
81 }
82
83
84 void do_msg_char_out(uint8_t subf, int len, uint8_t * msg)
85 {
86 (void)subf;
87
88 while (len--)
89 putchar(*msg++);
90 }
91
92 /* echo message */
93 void do_msg_echo(uint8_t subf, int len, uint8_t * msg)
94 {
95 (void)subf;
96
97 /* send re-echo */
98 msg_xmit(1, 3, len, msg);
99 }
100
101 /* get timer */
102 void do_msg_get_timer(uint8_t subf, int len, uint8_t * msg)
103 {
104 uint32_t time_ms = (len >= 4) ? *(uint32_t *) msg : 0;
105
106 time_ms = get_timer(time_ms);
107 msg_xmit(3, subf, sizeof(time_ms), (uint8_t *) &time_ms);
108 }
109
110 /* ---------------------------------------------------------------------------*/
111
112 #define CPM_DAY_OFFSET ((1978-1900) * 365 + 19) /* 19 leap years */
113
114 /*
115 * Convert CP/M time stamp to a broken-down time structure
116 *
117 */
118 int mk_date_time (int len, uint8_t *msg, struct tm *tmp)
119 {
120 time_t stamp;
121
122 if (len != 5)
123 return -1;
124
125 /* days since 2000-01-01 */
126 long days = msg[3] + (msg[4] << 8) - 8036;
127
128 if (days < 0)
129 return -1;
130
131 stamp = days * ONE_DAY;
132 stamp += bcd2bin(msg[0]);
133 stamp += bcd2bin(msg[1]) * 60 ;
134 stamp += bcd2bin(msg[2]) * 3600L;
135 gmtime_r(&stamp, tmp);
136 return 0;
137 }
138
139 void mk_cpm_time(struct tm *tmp, uint8_t cpm_time[5])
140 {
141 uint16_t days = 1;
142 uint_fast8_t leap=2;
143
144 for (int year=78; year < tmp->tm_year; year++) {
145 days = days + 365 + (leap == 0);
146 leap = (leap+1)%4;
147 }
148 days += tmp->tm_yday;
149
150 cpm_time[0] = bin2bcd(tmp->tm_sec);
151 cpm_time[1] = bin2bcd(tmp->tm_min);
152 cpm_time[2] = bin2bcd(tmp->tm_hour);
153 cpm_time[3] = days;
154 cpm_time[4] = days >> 8;
155 }
156
157 /* get/set cp/m time */
158 void do_msg_get_set_time(uint8_t subf, int len, uint8_t * msg)
159 {
160 struct tm t;
161 uint8_t cpm_time[5];
162 int rc;
163
164 memset(cpm_time, 0, ARRAY_SIZE(cpm_time));
165
166 switch (subf) {
167 case 3: /* set date & time */
168 /* initialize t with current time */
169 rc = rtc_get (&t);
170
171 if (rc >= 0) {
172 /* insert new date & time */
173 if (mk_date_time (len, msg, &t) != 0) {
174 my_puts_P(PSTR("## set_time: Bad date format\n"));
175 break;
176 }
177
178 time_t time;
179 time = mk_gmtime(&t);
180 gmtime_r(&time, &t);
181
182 /* and write to RTC */
183 rc = rtc_set (&t);
184 if(rc)
185 my_puts_P(PSTR("## set_time: Set date failed\n"));
186 } else {
187 my_puts_P(PSTR("## set_time: Get date failed\n"));
188 }
189 /* FALL TROUGH */
190 case 2: /* get date & time */
191 rc = rtc_get (&t);
192 if (rc >= 0) {
193 time_t time;
194 time = mk_gmtime(&t);
195 //mktime(&t);
196 gmtime_r(&time, &t);
197
198 mk_cpm_time(&t, cpm_time);
199 } else {
200 my_puts_P(PSTR("## get_time: Get date failed\n"));
201 }
202 break;
203 }
204
205 msg_xmit(3, subf, sizeof(cpm_time), cpm_time);
206 }
207
208 /* ---------------------------------------------------------------------------*/
209
210 /* TODO: Variable Disk Format */
211 #define CONFIG_CPM_DISKSIZE (8*1024*1024L)
212
213 struct cpm_drive_s {
214 uint8_t drv;
215 uint8_t device;
216 char *img_name;
217 bool dirty;
218 FIL fd;
219 };
220
221 static uint8_t disk_buffer[CONFIG_CPM_BLOCK_SIZE];
222 static struct cpm_drive_s drv_table[CONFIG_CPM_MAX_DRIVE];
223 static int handle_cpm_drv_to;
224
225
226 int cpm_drv_to(int state)
227 {
228 static uint32_t ts;
229
230 switch(state) {
231 case 0:
232 break;
233
234 case 1:
235 ts = get_timer(0);
236 state = 2;
237 break;
238
239 case 2:
240 if (get_timer(ts) > 1000) {
241 for (uint_fast8_t i=0; i < CONFIG_CPM_MAX_DRIVE; i++) {
242 if (drv_table[i].dirty) {
243 f_sync(&drv_table[i].fd);
244 drv_table[i].dirty = false;
245 debug_cpmsd("## %7lu f_sync: %c:\n", get_timer(0), i+'A');
246 }
247 }
248 state = 0;
249 }
250 }
251 return state;
252 }
253
254
255 void msg_cpm_result(uint8_t subf, uint8_t rc, int res)
256 {
257 uint8_t result_msg[3];
258
259 if (res)
260 rc |= 0x80;
261
262 result_msg[0] = rc;
263 result_msg[1] = res;
264 result_msg[2] = res >> 8;
265
266 if (rc) {
267 debug_cpmsd("###%7lu error rc: %.02x, res: %d\n", get_timer(0), rc, res);
268 }
269
270 msg_xmit(2, subf, sizeof(result_msg), result_msg);
271 }
272
273 /*
274 db 2 ; disk command
275 ds 1 ; subcommand (login/read/write)
276 ds 1 ; @adrv (8 bits) +0
277 ds 1 ; @rdrv (8 bits) +1
278 ds 3 ; @xdph (24 bits) +2
279 */
280
281 void do_msg_cpm_login(uint8_t subf, int len, uint8_t * msg)
282 {
283
284 FRESULT res = 0;
285 uint8_t drv;
286 char *np;
287
288 (void)subf;
289
290 if (len != 5) { /* TODO: check adrv, rdrv */
291 return msg_cpm_result(subf, 0x01, res);
292 }
293
294 debug_cpmsd("\n## %7lu login: %c:\n", get_timer(0), msg[0]+'A');
295
296
297 drv = msg[0];
298 if ( drv>= CONFIG_CPM_MAX_DRIVE) {
299 return msg_cpm_result(subf, 0x02, res);
300 }
301
302 /*
303 uint32_t dph = ((uint32_t)msg[4] << 16) + ((uint16_t)msg[3] << 8) + msg[2];
304 */
305
306 if (drv_table[drv].img_name != NULL) {
307 debug_cpmsd("## %7lu close: '%s'\n", get_timer(0), drv_table[drv].img_name);
308 f_close(&drv_table[drv].fd);
309 drv_table[drv].dirty = false;
310 free(drv_table[drv].img_name);
311 drv_table[drv].img_name = NULL;
312 }
313
314 strcpy_P((char *)disk_buffer, PSTR("dsk0"));
315 disk_buffer[3] = msg[0] + '0';
316 if (((np = getenv_char((char*)disk_buffer)) == NULL) ||
317 ((drv_table[drv].img_name = strdup(np)) == NULL)) {
318 return msg_cpm_result(subf, 0x03, res);
319 }
320
321
322 res = f_open(&drv_table[drv].fd, drv_table[drv].img_name,
323 FA_WRITE | FA_READ);
324
325 debug_cpmsd("## %7lu open: '%s', (env: '%s'), res: %d\n", get_timer(0),
326 drv_table[drv].img_name, disk_buffer, res);
327
328 /* send result*/
329 msg_cpm_result(subf, 0x00, res);
330 }
331
332
333 /*
334 db 2 ; disk command
335 ds 1 ; subcommand (login/read/write)
336 ds 1 ; @adrv (8 bits) +0
337 ds 1 ; @rdrv (8 bits) +1
338 ds 2 ; @trk (16 bits) +2
339 ds 2 ; @sect(16 bits) +4
340 ds 1 ; @cnt (8 bits) +6
341 ds 3 ; phys. transfer addr +7
342 */
343
344 #define ADRV 0
345 #define RDRV 1
346 #define TRK 2
347 #define SEC 4
348 #define CNT 6
349 #define ADDR 7
350
351 void do_msg_cpm_rw(uint8_t subf, int len, uint8_t * msg)
352 {
353 uint8_t drv;
354 uint32_t addr;
355 uint32_t pos;
356 uint8_t secs;
357 bool dowrite = (subf == 2);
358 FRESULT res = 0;
359 uint8_t rc = 0;
360 bool buserr = 0;
361
362 if (len != 10) { /* TODO: check adrv, rdrv */
363 return msg_cpm_result(subf, 0x01, res);
364 }
365
366 drv = msg[ADRV];
367 if ( drv>= CONFIG_CPM_MAX_DRIVE) {
368 return msg_cpm_result(subf, 0x02, res);
369 }
370
371 secs = msg[CNT];
372 addr = ((uint32_t)msg[ADDR+2] << 16) + ((uint16_t)msg[ADDR+1] << 8) + msg[ADDR];
373
374
375 /* TODO: tracks per sector from dpb */
376 pos = (((uint16_t)(msg[TRK+1] << 8) + msg[TRK]) * 8
377 + ((uint32_t)(msg[SEC+1] << 8) + msg[SEC])) * CONFIG_CPM_BLOCK_SIZE;
378
379 debug_cpmsd("## %7lu cpm_rw: %s %c: trk:%4d, sec: %d, pos: %.8lx, secs: %2d, "
380 "addr: %.5lx\n", get_timer(0), dowrite ? "write" : " read",
381 msg[ADRV]+'A', ((uint16_t)(msg[TRK+1] << 8) + msg[TRK]), msg[SEC],
382 pos, msg[CNT], addr);
383
384 if (pos + secs * CONFIG_CPM_BLOCK_SIZE > CONFIG_CPM_DISKSIZE) {
385 debug_cpmsd(" access > DISKSIZE (%.8lx > %.8lx) aborted!\n",
386 pos + secs * CONFIG_CPM_BLOCK_SIZE, CONFIG_CPM_DISKSIZE);
387 return msg_cpm_result(subf, 0x04, res);
388 }
389
390 res = f_lseek(&drv_table[drv].fd, pos);
391 #if 0
392 if (f_tell(&drv_table[drv].fd) != pos) {
393 return msg_cpm_result(subf, 0x05, res);
394 }
395 #endif
396
397 while (!res && secs--) {
398 unsigned int brw;
399 if (dowrite) {
400 if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
401 buserr = 1;
402 break;
403 } else {
404 z80_read_block(disk_buffer, addr, CONFIG_CPM_BLOCK_SIZE);
405 z80_bus_cmd(Release);
406 }
407 res = f_write(&drv_table[drv].fd, disk_buffer, CONFIG_CPM_BLOCK_SIZE, &brw);
408 } else {
409 res = f_read(&drv_table[drv].fd, disk_buffer, CONFIG_CPM_BLOCK_SIZE, &brw);
410 if (res == FR_OK) {
411 if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
412 buserr = 1;
413 break;
414 } else {
415 if (brw == 0) {
416 debug_cpmsd(" short read, brw: %d\n", brw);
417 z80_memset(addr, 0, CONFIG_CPM_BLOCK_SIZE);
418 brw = CONFIG_CPM_BLOCK_SIZE;
419 } else {
420 z80_write_block(disk_buffer, addr, CONFIG_CPM_BLOCK_SIZE);
421 }
422 z80_bus_cmd(Release);
423 }
424 }
425 }
426
427 if (brw != CONFIG_CPM_BLOCK_SIZE) {
428 debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res, brw);
429 dump_ram(disk_buffer, 0, 64, "Read Data");
430 res = -1;
431 }
432
433 addr += CONFIG_CPM_BLOCK_SIZE;
434 }
435
436 if (dowrite && !res) {
437 // res = f_sync(&drv_table[drv].fd);
438 drv_table[drv].dirty = true;
439 bg_setstat(handle_cpm_drv_to, 1);
440 }
441
442
443 if (buserr) {
444 debug_cpmsd("Bus timeout\n");
445 rc = 0x03;
446 }
447
448 /* send result*/
449 msg_cpm_result(subf, rc, res);
450 }
451
452
453 const FLASH struct msg_item z80_messages[] =
454 {
455 { 0, /* fct nr. */
456 1, 3, /* sub fct nr. from, to */
457 do_msg_ini_memfifo},
458 { 1,
459 1, 1,
460 do_msg_char_out},
461 { 1,
462 2, 2,
463 do_msg_echo},
464 { 2,
465 0, 0,
466 do_msg_cpm_login},
467 { 2,
468 1, 2,
469 do_msg_cpm_rw},
470 { 3,
471 1, 1,
472 do_msg_get_timer},
473 { 3,
474 2, 3, /* 2: get, 3: set time and date */
475 do_msg_get_set_time},
476 { 0xff, /* end mark */
477 0, 0,
478 0},
479
480 };
481
482
483
484
485 void do_message(int len, uint8_t *msg)
486 {
487 uint8_t fct, sub_fct;
488 int_fast8_t i = 0;
489
490 if (len >= 2) {
491 fct = *msg++;
492 sub_fct = *msg++;
493 len -= 2;
494
495 while (fct != z80_messages[i].fct) {
496 if (z80_messages[i].fct == 0xff) {
497 DBG_P(1, "do_message: Unknown function: %i, %i\n",
498 fct, sub_fct);
499 return; /* TODO: unknown message # */
500 }
501
502 ++i;
503 }
504
505 while (fct == z80_messages[i].fct) {
506 if (sub_fct >= z80_messages[i].sub_min &&
507 sub_fct <= z80_messages[i].sub_max )
508 break;
509 ++i;
510 }
511
512 if (z80_messages[i].fct != fct) {
513 DBG_P(1, "do_message: Unknown sub function: %i, %i\n",
514 fct, sub_fct);
515 return; /* TODO: unknown message sub# */
516 }
517
518 (z80_messages[i].func)(sub_fct, len, msg);
519
520
521 } else {
522 /* TODO: error */
523 DBG_P(1, "do_message: to few arguments (%i); this shouldn't happen!\n", len);
524 }
525 }
526
527
528
529 #define CTRBUF_LEN 256
530
531 void check_msg_fifo(void)
532 {
533 int ch;
534 static int_fast8_t state;
535 static int msglen,idx;
536 static uint8_t buffer[CTRBUF_LEN];
537
538 while ((ch = z80_memfifo_getc(fifo_msgin)) >= 0) {
539 switch (state) {
540 case 0: /* wait for start of message */
541 if (ch == 0xAE) { /* TODO: magic number */
542 msglen = 0;
543 idx = 0;
544 state = 1;
545 }
546 break;
547 case 1: /* get msg len */
548 if (ch > 0 && ch <= CTRBUF_LEN) {
549 msglen = ch;
550 state = 2;
551 } else
552 state = 0;
553 break;
554 case 2: /* get message */
555 buffer[idx++] = ch;
556 if (idx == msglen) {
557 do_message(msglen, buffer);
558 state = 0;
559 }
560 break;
561 }
562 }
563 }
564
565
566 int msg_handling(int state)
567 {
568 bool pending;
569
570 ATOMIC_BLOCK(ATOMIC_FORCEON) {
571 pending = (Stat & S_MSG_PENDING) != 0;
572 Stat &= ~S_MSG_PENDING;
573 }
574
575 if (pending) {
576 uint8_t init_request;
577 z80_bus_cmd(Request);
578 init_request = z80_read(0x43);
579 z80_bus_cmd(Release);
580 if ( init_request != 0) {
581 /* Get address of fifo 0 */
582 z80_bus_cmd(Request);
583 uint32_t fifo_addr = z80_read(0x40) +
584 ((uint16_t) z80_read(0x40+1) << 8) +
585 ((uint32_t) z80_read(0x40+2) << 16);
586 z80_write(0x43, 0);
587 z80_bus_cmd(Release);
588
589 if (fifo_addr != 0) {
590 z80_memfifo_init(fifo_msgin, fifo_addr);
591 state = 1;
592 } else
593 state = 0;
594
595 } else {
596 check_msg_fifo();
597 }
598 }
599
600 return state;
601 }
602
603
604 static int handle_msg_handling;
605
606 void setup_z180_serv(void)
607 {
608
609 handle_msg_handling = bg_register(msg_handling, 0);
610 handle_cpm_drv_to = bg_register(cpm_drv_to, 0);
611 }
612
613 void restart_z180_serv(void)
614 {
615 z80_bus_cmd(Request);
616 z80_memset(0x40, 0, 4);
617 z80_bus_cmd(Release);
618
619 for (int i = 0; i < NUM_FIFOS; i++)
620 z80_memfifo_init(i, 0);
621 bg_setstat(handle_msg_handling, 0);
622
623 }
624
625 #if 0
626 /*--------------------------------------------------------------------------*/
627
628 const FLASH uint8_t iniprog[] = {
629 0xAF, // xor a
630 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
631 0x3E, 0x30, // ld a,030h
632 0xED, 0x39, 0x32 //out0 (dcntl),a ;0 mem, max i/0 wait states
633 };
634
635 const FLASH uint8_t sertest[] = {
636 0xAF, // xor a
637 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
638 0x3E, 0x30, // ld a,030h
639 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
640 0x3E, 0x80, // ld a,M_MPBT ;no MP, PS=10, DR=16, SS=0
641 0xED, 0x39, 0x03, // out0 (cntlb1),a
642 0x3E, 0x64, // ld a,M_RE + M_TE + M_MOD2 ;
643 0xED, 0x39, 0x01, // out0 (cntla1),a
644 0x3E, 0x00, // ld a,0
645 0xED, 0x39, 0x05, // out0 (stat1),a ;Enable rx interrupts
646 0xED, 0x38, 0x05, //l0:in0 a,(stat1)
647 0xE6, 0x80, // and 80h
648 0x28, 0xF9, // jr z,l0
649 0xED, 0x00, 0x09, // in0 b,(rdr1)
650 0xED, 0x38, 0x05, //l1:in0 a,(stat1)
651 0xE6, 0x02, // and 02h
652 0x28, 0xF9, // jr z,l1
653 0xED, 0x01, 0x07, // out0 (tdr1),b
654 0x18, 0xEA, // jr l0
655 };
656
657 const FLASH uint8_t test1[] = {
658 0xAF, // xor a
659 0xED, 0x39, 0x36, // out0 (rcr),a ;disable DRAM refresh
660 0x3E, 0x30, // ld a,030h
661 0xED, 0x39, 0x32, // out0 (dcntl),a ;0 mem, max i/0 wait states
662 0x21, 0x1E, 0x00, // ld hl,dmclrt ;load DMA registers
663 0x06, 0x08, // ld b,dmct_e-dmclrt
664 0x0E, 0x20, // ld c,sar0l
665 0xED, 0x93, // otimr
666 0x3E, 0xC3, // ld a,0c3h ;dst +1, src +1, burst
667 0xED, 0x39, 0x31, // out0 (dmode),a ;
668 0x3E, 0x62, // ld a,062h ;enable dma0,
669 0xED, 0x39, 0x30, //cl_1: out0 (dstat),a ;copy 64k
670 0x18, 0xFB, // jr cl_1 ;
671 0x00, 0x00, //dmclrt: dw 0 ;src (inc)
672 0x00, // db 0 ;src
673 0x00, 0x00, // dw 0 ;dst (inc),
674 0x00, // db 0 ;dst
675 0x00, 0x00, // dw 0 ;count (64k)
676 };
677 #endif
Z180 Stamp Monitor