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3
4 extrn buf.init
5 extrn isv_sw
6
7
8 global ser.init
9 global ser.instat,ser.in
10 global ser.out
11
12 ;TODO: define a trampoline area somewhere in top ram.
13 rtxisvjmp equ 0FF60h ;momentan frei...
14
15 include config.inc
16 include z180reg.inc
17
18
19 ;-----------------------------------------------------
20
21 dseg
22
23 buf_start:
24 mkbuf ser1.inbuf,s1.rx_len
25 mkbuf ser1.outbuf,s1.tx_len
26 buf_end:
27
28
29
30 ;-----------------------------------------------------
31
32 cseg
33 ;
34 ; Init Serial I/O for console input and output (ASCI1)
35 ;
36
37
38 ser.init:
39 ; ld a,i
40 ; push af ;save IFF
41 ; di
42
43 xor a ;
44 out0 (stat1),a ;Disable rx/tx interrupts
45
46 ld hl,rxtx_src ;move rx and tx isv to common ram
47 ld de,rxtx_dst ;
48 ld bc,rxtx_src_e-rxtx_src ;
49 ldir ;
50
51 ld hl,rtxisvjmp ;rx/tx int vector
52 ld (ivtab + IV$ASCI1),hl;
53 ld a,0cdh ;
54 ld (rtxisvjmp),a ;
55 ld hl,isv_sw ;
56 ld (rtxisvjmp + 1),hl ;
57 ld hl,rxtxisv ;
58 ld (rtxisvjmp + 3),hl ;
59
60 ; ASCI1: 8N1, highest baudrate (56700), CTS disabled
61
62 ld a,M_MPBT
63 out0 (cntlb1),a
64 ld a,M_RE + M_TE + M_MOD2
65 out0 (cntla1),a
66 ld a,M_RIE
67 out0 (stat1),a ;Enable rx interrupts
68
69 ld ix,ser1.inbuf
70 ld a,ser1.inbuf.mask
71 call buf.init
72 ld ix,ser1.outbuf
73 ld a,ser1.outbuf.mask
74 call buf.init
75
76 ; pop af
77 ; ret po
78 ; ei
79 ret ;
80
81 ser.instat:
82 push ix
83 ld ix,ser1.inbuf ;
84
85 buf.empty:
86 ld a,(ix+o.in_idx) ;
87 sub (ix+o.out_idx) ;
88 pop ix
89 ret z
90 or 0ffh
91 ret
92
93 ser.in:
94 push hl ;11
95 push de ;11
96 ld hl,ser1.inbuf-1 ; 9 hl = &rx.out_idx
97 ld a,(hl) ; 6 a = rx.out_idx
98 dec hl ; 4 hl = &rx.in_idx
99 jr bg.w1
100 bg.wait:
101 halt
102 bg.w1:
103 cp (hl) ; 6 while (out_idx==in_idx)
104 jr z,bg.wait ; 6 (/8) ;
105
106 inc a ; 4
107 ld e,a ; 4
108 inc e ; 4
109 ld d,0 ; 6
110
111 ex de,hl ; 3
112 add hl,de ;10
113 ld l,(hl) ; 6
114 ex de,hl ; 3
115
116 dec hl ; 4
117 and (hl) ; 6
118 inc hl ; 4
119 inc hl ; 4
120 ld (hl),a ; 7
121
122 ld a,e ; 4
123 pop de ; 9
124 pop hl ; 9
125 ret ; 9
126 ; 153
127
128 ser.outstat:
129 push ix
130 ld ix,ser1.outbuf ;
131 buf.full:
132 ld a,(ix+o.in_idx) ;
133 inc a
134 and (ix+o.mask)
135 sub (ix+o.out_idx) ;
136 pop ix
137 ret z
138 or 0ffh
139 ret
140
141
142 ser.out:
143 push ix
144 ld ix,ser1.outbuf ;
145 buf.put:
146 push hl ;
147 push bc
148 push ix
149 pop hl
150 ld c,(ix+o.in_idx) ;
151 ld b,0
152 add hl,bc
153 ld b,a
154
155 ld a,c ;
156 inc a
157 and (ix+o.mask)
158 bp.wait:
159 cp (ix+o.out_idx) ;
160 jr z,bp.wait
161 ld (hl),b
162 ld (ix+o.in_idx),a
163
164 di ;036f
165 in0 a,(stat1) ;0374
166 set TIE,a ;0377
167 out0 (stat1),a ;0379
168 ei ;037c
169
170 ld a,b
171 pop bc
172 pop hl
173 pop ix
174 ret
175
176
177 ;------------------------------------------
178 ; ASCI 1 Transmit/Receive interupt routines
179 ; moved to common ram
180
181 rxtx_src:
182 dseg
183 rxtx_dst: ; (0c097h) old
184
185 rxtxisv:
186 inidat
187 in0 a,(stat1) ;receive flag set?
188 jp p,txisv ;
189
190 in0 d,(rdr1) ;todo: break detection
191 bit FE,a ;framing error?
192 jr nz,??ri_1
193
194 push ix
195 ld ix,ser1.inbuf ;
196 ld hl,ser1.inbuf ;
197 ld c,(ix+o.in_idx) ;
198 ld b,0
199 add hl,bc
200
201 ld a,c ;
202 inc a
203 and (ix+o.mask)
204 cp (ix+o.out_idx) ;
205 jr z,??ri_0
206 ld (hl),d
207 ld (ix+o.in_idx),a
208 ??ri_0:
209 pop ix
210 ??ri_1:
211 in0 a,(cntla1) ;0705 c0c0
212 res EFR,a ;0708
213 out0 (cntla1),a ;070a
214 ret
215
216 inidate
217
218 txisv:
219 inidat
220 push ix
221 ld ix,ser1.outbuf ;
222
223 ld a,(ix+o.out_idx) ;
224 cp (ix+o.in_idx) ;
225 jr z,??ti_2
226
227 ld hl,ser1.outbuf ;
228 add a,l
229 ld l,a
230 jr nc,??ti_1
231 inc h
232 ??ti_1:
233 ld l,(hl)
234 out0 (tdr1),l ;071b
235
236 ld a,(ix+o.out_idx) ;
237 inc a
238 and (ix+o.mask)
239 ld (ix+o.out_idx),a
240 jr ??ti_3
241 ??ti_2:
242 in0 a,(stat1) ;0730 disable tx-int
243 res TIE,a ;0733
244 out0 (stat1),a ;0735
245 ??ti_3:
246 pop ix
247 ret
248
249 inidate
250
251 cseg
252 rxtx_src_e:
253
254
255 end
256
257