Add polling driver for ASCI0/1

[z180-stamp.git] / z180 / z180reg.inc

diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 5bbd088d68277901ccb0230569bb4096692b310c..271a4468a1593074f44bb7790c0ec9cbadc5cf28 100644 (file)
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -76,6 +76,13 @@ tcr  equ     IOBASE+10h      ;Timer Control Register
 \r
 asext0 equ     IOBASE+12h      ;ASCI Extension Control Register\r
 asext1 equ     IOBASE+13h      ;ASCI Extension Control Register\r
+       b2m DCD0DIS,6           ;DCD0 Disable\r
+       b2m CTS0DIS,5           ;CTS0 Disable\r
+       b2m X1,4                ;CKA * 1 Clock/Samle Rate Divider\r
+       b2m BRGMOD,3            ;BRG Mode (Baud rate generator)\r
+       b2m BREAKEN,2           ;Break Enable\r
+       b2m BREAK,1             ;Break detected\r
+       b2m SENDBREAK,0         ;Send Break\r
 \r
 tmdr1l equ     IOBASE+14h      ;Timer Data Register Channel 1\r
 tmdr1h equ     IOBASE+15h      ;\r