Add polling driver for ASCI0/1

diff --git a/avr/command_tbl.c b/avr/command_tbl.c
index 6c1c10de579073ac7ea72c0351265b6a2373cf21..b3c401ce14b9e7fedafcf68dd3adde1ea5307a2d 100644 (file)
--- a/avr/command_tbl.c
+++ b/avr/command_tbl.c
@@ -150,7 +150,7 @@ CMD_TBL_ITEM(
        ""
 ),
 CMD_TBL_ITEM(
-       connect, 1, 1,  do_console,
+       connect, 1, 0,  do_console,
        "Connect to CPU console i/o",
        ""
 ),

diff --git a/z180/Tupfile b/z180/Tupfile
index 46aae4e0bd46077c0872a299b1b0308d4070eb29..23855f8bc086b12c6e7eebd076facd376514f30f 100644 (file)
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -4,8 +4,8 @@ PROG    = hdrom
 
 SRC    = init.180
 SRC    += ddtz.180
-#SRC   += fifoio.180 msgbuf.180 asci1-i.180 console.180
-SRC    += msgbuf-a.180 conbuf-a.180 asci1-i.180 bioscio.180 chario.180
+#SRC   += fifoio.180 msgbuf.180 asci-p.180 console.180
+SRC    += msgbuf-a.180 conbuf-a.180 asci-p.180 bioscio.180 chario.180
 # serial (asci1) console only:
 #SRC   += asci1-i.180 console.180
 SRC    += romend.180

diff --git a/z180/asci-p.180 b/z180/asci-p.180
new file mode 100644 (file)
index 0000000..956faf1
--- /dev/null
+++ b/z180/asci-p.180
@@ -0,0 +1,133 @@
+       page    200\r
+\r
+       extrn   ioiniml\r
+\r
+       global  as0init\r
+       global  as0ista,as0inp\r
+       global  as0osta,as0out\r
+       global  as1init\r
+       global  as1ista,as1inp\r
+       global  as1osta,as1out\r
+\r
+       include config.inc\r
+       include z180reg.inc\r
+\r
+\r
+;-----------------------------------------------------\r
+;\r
+;\r
+; TC = (f PHI /(2*baudrate*Clock_mode)) - 2\r
+;\r
+; TC = (f PHI / (32 * baudrate)) - 2\r
+;\r
+\r
+       cseg\r
+;\r
+; Init Serial I/O for console input and output (ASCI1)\r
+;\r
+       \r
+\r
+\r
+as0init:\r
+       ld      hl,initab0\r
+       jp      ioiniml\r
+\r
+as1init:\r
+       ld      hl,initab1\r
+       jp      ioiniml\r
+\r
+               \r
+       ld      a,M_MPBT \r
+       out0    (cntlb1),a\r
+       ld      a,M_RE + M_TE + M_MOD2  ;Rx/Tx enable \r
+       out0    (cntla1),a\r
+       ld      a,M_RIE\r
+       out0    (stat1),a       ;Enable rx interrupts\r
+\r
+       ret                     ;\r
+\r
+\r
+initab0:\r
+       db      1,stat0,0               ;Disable rx/tx interrupts\r
+                                       ;Enable baud rate generator\r
+       db      1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS\r
+       db      2,astc0l,low 28, high 28\r
+       db      1,cntlb0,M_MPBT         ;No MP Mode, X16\r
+       db      1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
+       db      0\r
+\r
+initab1:\r
+       db      1,stat1,0               ;Disable rx/tx ints, disable CTS1\r
+       db      1,asext1,M_BRGMOD       ;Enable baud rate generator\r
+       db      2,astc1l,low 3, high 3\r
+       db      1,cntlb1,M_MPBT         ;No MP Mode, X16\r
+       db      1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
+       db      0\r
+\r
+\r
+\r
+as0ista:\r
+       in0     a,(stat0)\r
+       and     M_RDRF\r
+       ret     z\r
+       or      0ffh\r
+       ret\r
+       \r
+as1ista:\r
+       in0     a,(stat1)\r
+       and     M_RDRF\r
+       ret     z\r
+       or      0ffh\r
+       ret\r
+       \r
+\r
+as0inp:\r
+       in0     a,(stat0)\r
+       rlca\r
+       jr      nc,as0inp\r
+       in0     a,rdr0\r
+       ret\r
+\r
+as1inp:\r
+       in0     a,(stat1)\r
+       rlca\r
+       jr      nc,as1inp\r
+       in0     a,rdr1\r
+       ret\r
+\r
+\r
+\r
+as0osta:\r
+       in0     a,(stat0)\r
+       and     M_TDRE\r
+       ret     z\r
+       or      0ffh\r
+       ret\r
+\r
+as1osta:\r
+       in0     a,(stat1)\r
+       and     M_TDRE\r
+       ret     z\r
+       or      0ffh\r
+       ret\r
+\r
+\r
+as0out:\r
+       in0     a,(stat0)\r
+       and     M_TDRE\r
+       jr      z,as0out\r
+       out0    (tdr0),c\r
+       ld      a,c\r
+       ret\r
+\r
+as1out:\r
+       in0     a,(stat1)\r
+       and     M_TDRE\r
+       jr      z,as1out\r
+       out0    (tdr1),c\r
+       ld      a,c\r
+       ret\r
+\r
+       end\r
+\r
+\r

diff --git a/z180/bioscio.180 b/z180/bioscio.180
index b0fd4daa98fd7b2b513132cf4e0acd73624d0836..2d8e5e032ac13c86c60f6de9282abb93f69abb14 100644 (file)
--- a/z180/bioscio.180
+++ b/z180/bioscio.180
@@ -66,7 +66,7 @@ c$init$loop:
        jp      p,c$init$loop\r
 \r
 ;      ld      hl,1000000000000000b    ; assign console to HOST\r
-       ld      hl,0100000000000000b    ; assign console to ASCI1\r
+       ld      hl,0010000000000000b    ; assign console to ASCI1\r
        ld      (@civec),hl\r
        ld      (@covec),hl\r
        ld      hl,0000000000000000b    ; assign auxiliary to nothing\r

diff --git a/z180/chario.180 b/z180/chario.180
index 6632690688b0cf4c6f6070b6dfea462b8e1e1c2b..8313658571b1711a841124b19ee6d6b1a13a8642 100644 (file)
--- a/z180/chario.180
+++ b/z180/chario.180
@@ -8,14 +8,15 @@
        public  @ctbl\r
 \r
        extrn   ff.init,ff.i.st,ff.in,ff.o.st,ff.out\r
-       extrn   ser.init,ser.ist,ser.in,ser.ost,ser.out\r
+       extrn   as0init,as0ista,as0inp,as0osta,as0out\r
+       extrn   as1init,as1ista,as1inp,as1osta,as1out\r
        \r
        include config.inc\r
        include z180reg.inc\r
        include modebaud.inc    ; define mode bits and baud eqautes\r
 \r
 \r
-max$device     equ 2\r
+max$device     equ 3\r
 \r
        cseg\r
 \r
@@ -25,7 +26,8 @@ max$device    equ 2
        ld      b,c\r
        call    vector$io\r
        dw      ff.init\r
-       dw      ser.init\r
+       dw      as0init\r
+       dw      as1init\r
        dw      rret\r
 \r
 ; b = device, c = output char, a = input char\r
@@ -33,25 +35,29 @@ max$device  equ 2
 ?ci:                           ; character input\r
        call    vector$io\r
        dw      ff.in\r
-       dw      ser.in\r
+       dw      as0inp\r
+       dw      as1inp\r
        dw      null$input\r
 \r
 ?cist:                         ; character input status\r
        call    vector$io\r
        dw      ff.i.st\r
-       dw      ser.ist\r
+       dw      as0ista\r
+       dw      as1ista\r
        dw      null$status\r
 \r
 ?co:                           ; character output\r
        call    vector$io\r
        dw      ff.out\r
-       dw      ser.out\r
+       dw      as0out\r
+       dw      as1out\r
        dw      rret\r
 \r
 ?cost:                         ; character output status\r
        call    vector$io\r
        dw      ff.o.st\r
-       dw      ser.ost\r
+       dw      as0osta\r
+       dw      as1osta\r
        dw      ret$true\r
 \r
 vector$io:\r
@@ -89,10 +95,15 @@ null$status:
 \r
 @ctbl:\r
        db      'HOST  '        ; device 0\r
-       db      mb$output\r
+       db      mb$in$out\r
        db      baud$none\r
 \r
-       db      'ASCI1 '        ; device 0\r
+       db      'ASCI1 '        ; device 1\r
+       db      mb$in$out+mb$serial+mb$soft$baud\r
+ser0$baud:\r
+       db      baud$19200\r
+\r
+       db      'ASCI1 '        ; device 2\r
        db      mb$in$out+mb$serial+mb$soft$baud\r
 ser1$baud:\r
        db      baud$19200\r

diff --git a/z180/init.180 b/z180/init.180
index 0bd37c1d68bbb2874fea672c3563e0d81dc4a6fa..39b03fcdb6a5cf98dbfe7d89f94904862317498f 100644 (file)
--- a/z180/init.180
+++ b/z180/init.180
@@ -5,7 +5,6 @@
        extrn $stack\r
        extrn charini,?const,?conin\r
        extrn ?cono,?conos\r
-\r
        extrn romend\r
 \r
 \r
@@ -75,14 +74,12 @@ start:
 \r
 hwini0:\r
     if CPU_Z180\r
-\r
        db      3               ;count\r
        db      rcr,CREFSH      ;configure DRAM refresh\r
        db      dcntl,INIWAITS  ;wait states\r
        db      cbar,SYS$CBAR\r
-    else\r
-       db     0\r
     endif\r
+       db     0\r
 \r
     if CPU_Z180\r
 dmclrt:                                ;clear ram per dma\r
@@ -95,6 +92,7 @@ nullbyte:
        db      00h             ;dst\r
        dw      0-romend        ;count (64k)\r
 dmct_e:\r
+       db      0\r
     endif\r
 \r
 \r
@@ -165,7 +163,7 @@ kstart:
      if 0\r
        \r
        ld      hl,dmclrt       ;load DMA registers\r
-       call    io.ini.m\r
+       call    ioiniml\r
        ld      a,0cbh          ;01ef   dst +1, src fixed, burst\r
        out0    (dmode),a       ;01f1\r
 \r
@@ -434,7 +432,7 @@ prt0_init:
        inc     hl\r
        ld      (hl),high iprt0\r
        ld      hl,prt0itab\r
-       call    io.ini.m\r
+       call    ioiniml\r
        ret\r
 \r
 prt0itab:\r
@@ -444,6 +442,7 @@ prt0itab:
        dw      PRT_TC10MS\r
        db      M_TIE0+M_TDE0   ;enable timer 0 interrupt and down count.\r
 prt0it_e:\r
+       db      0\r
     endif\r
 \r
 \r
@@ -451,24 +450,55 @@ prt0it_e:
 ;----------------------------------------------------------------------\r
 ;\r
 \r
+    if CPU_Z180\r
 io.ini:\r
+     if 0\r
        push    bc\r
-    if CPU_Z180\r
-\r
        ld      b,0             ;high byte port adress\r
+ioi_nxt:\r
        ld      a,(hl)          ;count\r
        inc     hl\r
        or      a\r
        jr      z,ioi_e\r
-ioi_1:\r
+\r
        ld      c,(hl)          ;port address\r
        inc     hl\r
+ioi_r:\r
        outi\r
        inc     b               ;outi decrements b\r
        dec     a\r
-       jr      nz,ioi_1\r
+       jr      nz,ioi_r\r
+       jr      ioi_nxt\r
 ioi_e: \r
+       pop     bc\r
+       ret\r
+       \r
+     else ;(if 1/0)\r
+     \r
+       push    bc\r
+       jr      ioi_nxt\r
+ioi_l:\r
+       ld      c,(hl)          ;port address\r
+       inc     hl\r
+       inc     c\r
+ioi_r:\r
+       dec     c               ;otim increments c\r
+       otim\r
+       jr      z,ioi_r\r
+ioi_nxt:\r
+       ld      b,(hl)          ;count\r
+       inc     hl\r
+       inc     b               ;stop if count == 0\r
+       djnz    ioi_l\r
+       pop     bc\r
+       ret\r
+       \r
+     endif ;(1/0)\r
+\r
     else\r
+\r
+io.ini:\r
+       push    bc\r
        jr      ioi_nxt\r
 ioi_l:\r
        ld      c,(hl)          ;port address\r
@@ -483,16 +513,28 @@ ioi_nxt:
        pop     bc\r
        ret\r
 \r
+;----------------------------------------------------------------------\r
+\r
     if CPU_Z180\r
-io.ini.m:\r
+\r
+       global ioiniml\r
+\r
+ioiniml:\r
        push    bc\r
+       xor     a\r
+ioml_lp:\r
        ld      b,(hl)\r
        inc     hl\r
+       cp      b\r
+       jr      z,ioml_e\r
+       \r
        ld      c,(hl)\r
        inc     hl\r
        otimr\r
+       jr      ioml_lp\r
+ioml_e:\r
        pop     bc\r
-       ret\r
+       ret     z\r
     endif\r
 \r
 io.ini.l:\r

diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 5bbd088d68277901ccb0230569bb4096692b310c..271a4468a1593074f44bb7790c0ec9cbadc5cf28 100644 (file)
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -76,6 +76,13 @@ tcr  equ     IOBASE+10h      ;Timer Control Register
 \r
 asext0 equ     IOBASE+12h      ;ASCI Extension Control Register\r
 asext1 equ     IOBASE+13h      ;ASCI Extension Control Register\r
+       b2m DCD0DIS,6           ;DCD0 Disable\r
+       b2m CTS0DIS,5           ;CTS0 Disable\r
+       b2m X1,4                ;CKA * 1 Clock/Samle Rate Divider\r
+       b2m BRGMOD,3            ;BRG Mode (Baud rate generator)\r
+       b2m BREAKEN,2           ;Break Enable\r
+       b2m BREAK,1             ;Break detected\r
+       b2m SENDBREAK,0         ;Send Break\r
 \r
 tmdr1l equ     IOBASE+14h      ;Timer Data Register Channel 1\r
 tmdr1h equ     IOBASE+15h      ;\r