+ page 200\r
+\r
+ extrn ioiniml\r
+\r
+ global as0init\r
+ global as0ista,as0inp\r
+ global as0osta,as0out\r
+ global as1init\r
+ global as1ista,as1inp\r
+ global as1osta,as1out\r
+\r
+ include config.inc\r
+ include z180reg.inc\r
+\r
+\r
+;-----------------------------------------------------\r
+;\r
+;\r
+; TC = (f PHI /(2*baudrate*Clock_mode)) - 2\r
+;\r
+; TC = (f PHI / (32 * baudrate)) - 2\r
+;\r
+\r
+ cseg\r
+;\r
+; Init Serial I/O for console input and output (ASCI1)\r
+;\r
+ \r
+\r
+\r
+as0init:\r
+ ld hl,initab0\r
+ jp ioiniml\r
+\r
+as1init:\r
+ ld hl,initab1\r
+ jp ioiniml\r
+\r
+ \r
+ ld a,M_MPBT \r
+ out0 (cntlb1),a\r
+ ld a,M_RE + M_TE + M_MOD2 ;Rx/Tx enable \r
+ out0 (cntla1),a\r
+ ld a,M_RIE\r
+ out0 (stat1),a ;Enable rx interrupts\r
+\r
+ ret ;\r
+\r
+\r
+initab0:\r
+ db 1,stat0,0 ;Disable rx/tx interrupts\r
+ ;Enable baud rate generator\r
+ db 1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS\r
+ db 2,astc0l,low 28, high 28\r
+ db 1,cntlb0,M_MPBT ;No MP Mode, X16\r
+ db 1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
+ db 0\r
+\r
+initab1:\r
+ db 1,stat1,0 ;Disable rx/tx ints, disable CTS1\r
+ db 1,asext1,M_BRGMOD ;Enable baud rate generator\r
+ db 2,astc1l,low 3, high 3\r
+ db 1,cntlb1,M_MPBT ;No MP Mode, X16\r
+ db 1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
+ db 0\r
+\r
+\r
+\r
+as0ista:\r
+ in0 a,(stat0)\r
+ and M_RDRF\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+ \r
+as1ista:\r
+ in0 a,(stat1)\r
+ and M_RDRF\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+ \r
+\r
+as0inp:\r
+ in0 a,(stat0)\r
+ rlca\r
+ jr nc,as0inp\r
+ in0 a,rdr0\r
+ ret\r
+\r
+as1inp:\r
+ in0 a,(stat1)\r
+ rlca\r
+ jr nc,as1inp\r
+ in0 a,rdr1\r
+ ret\r
+\r
+\r
+\r
+as0osta:\r
+ in0 a,(stat0)\r
+ and M_TDRE\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+\r
+as1osta:\r
+ in0 a,(stat1)\r
+ and M_TDRE\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+\r
+\r
+as0out:\r
+ in0 a,(stat0)\r
+ and M_TDRE\r
+ jr z,as0out\r
+ out0 (tdr0),c\r
+ ld a,c\r
+ ret\r
+\r
+as1out:\r
+ in0 a,(stat1)\r
+ and M_TDRE\r
+ jr z,as1out\r
+ out0 (tdr1),c\r
+ ld a,c\r
+ ret\r
+\r
+ end\r
+\r
+\r