message buffer init changes. cp/m r/w for new memory map

[z180-stamp.git] / z180 / z180reg.inc

diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 616138c045937f40778b55593abb915447eb4ccc..a248f5f43e958dc5d6c53f08f46898249d1b34cd 100644 (file)
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -24,7 +24,7 @@ cntla1        equ     IOBASE+01h      ;ASCI Control Register A Channel 1
        b2m MPBR, 3             ;Multiprocessor Bit Receive (Read)\r
        b2m EFR, 3              ;Error Flag Reset (Write)\r
        b2m MOD2, 2             ;Data Format Mode 1 = 8-Bit data\r
-       b2m NOD1, 1             ;1 = Parity enabled\r
+       b2m MOD1, 1             ;1 = Parity enabled\r
        b2m MOD0, 0             ;1 = 2 stop bits\r
 \r
 cntlb0 equ     IOBASE+02h      ;ASCI Control Register B Channel 0\r
@@ -51,10 +51,10 @@ stat1       equ     IOBASE+05h      ;ASCI Status Channel 1
        b2m TDRE,1              ;Transmit Data Register Empty\r
        b2m TIE,0               ;Transmit Interrupt Enable\r
 \r
-tdr0   equ     IOBASE+06h      ;ASCI Transmit Data \r
-tdr1   equ     IOBASE+07h      ;ASCI Transmit Data \r
-rdr0   equ     IOBASE+08h      ;ASCI Receive Data \r
-rdr1   equ     IOBASE+09h      ;ASCI Receive Data \r
+tdr0   equ     IOBASE+06h      ;ASCI Transmit Data\r
+tdr1   equ     IOBASE+07h      ;ASCI Transmit Data\r
+rdr0   equ     IOBASE+08h      ;ASCI Receive Data\r
+rdr1   equ     IOBASE+09h      ;ASCI Receive Data\r
 \r
 cntr   equ     IOBASE+0Ah      ;CSI/O Control Register\r
 trdr   equ     IOBASE+0Bh      ;CSI/O Transmit/Receive Data Register\r
@@ -76,6 +76,13 @@ tcr  equ     IOBASE+10h      ;Timer Control Register
 \r
 asext0 equ     IOBASE+12h      ;ASCI Extension Control Register\r
 asext1 equ     IOBASE+13h      ;ASCI Extension Control Register\r
+       b2m DCD0DIS,6           ;DCD0 Disable\r
+       b2m CTS0DIS,5           ;CTS0 Disable\r
+       b2m X1,4                ;CKA * 1 Clock/Samle Rate Divider\r
+       b2m BRGMOD,3            ;BRG Mode (Baud rate generator)\r
+       b2m BREAKEN,2           ;Break Enable\r
+       b2m BREAK,1             ;Break detected\r
+       b2m SENDBREAK,0         ;Send Break\r
 \r
 tmdr1l equ     IOBASE+14h      ;Timer Data Register Channel 1\r
 tmdr1h equ     IOBASE+15h      ;\r
@@ -94,6 +101,7 @@ cmr  equ     IOBASE+1Eh      ;Clock Mutiplier Register
        b2m LNC,6               ;Low Noise Crystal\r
 \r
 ccr    equ     IOBASE+1Fh      ;CPU Control Register\r
+       b2m NCD 7               ;No Clock Divide\r
 \r
 sar0l  equ     IOBASE+20h      ;DMA Src Adr Register Channel 0\r
 sar0h  equ     IOBASE+21h      ;\r