#define MAX_DRIVE 4
#define BLOCK_SIZE 512
-#define TPA_BASE 0x10000
-#define COMMON_BASE 0xC000
+//#define TPA_BASE 0x10000
+//#define COMMON_BASE 0xC000
struct cpm_drive_s {
uint8_t drv;
res = f_lseek(&drv_table[drv].fd, pos);
while (!res && secs--) {
- unsigned int cnt, br;
-
- /* check bank boundary crossing */
- cnt = 0;
- if (addr < (TPA_BASE + COMMON_BASE) &&
- (addr + BLOCK_SIZE) > (TPA_BASE + COMMON_BASE)) {
- cnt = (TPA_BASE + COMMON_BASE) - addr;
- }
-
- if (cnt) {
- debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr, cnt);
- debug_cpmsd("## %67c addr: %.5lx, cnt: %3d\n", ' ', addr+cnt-TPA_BASE, BLOCK_SIZE-cnt);
- }
-
+ unsigned int brw;
if (dowrite) {
if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
buserr = 1;
break;
} else {
- if (cnt) {
- z80_read_block(disk_buffer, addr, cnt);
- addr = addr + cnt - TPA_BASE;
- }
- z80_read_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
+ z80_read_block(disk_buffer, addr, BLOCK_SIZE);
z80_bus_cmd(Release);
}
- res = f_write(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
+ res = f_write(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &brw);
} else {
- res = f_read(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &br);
- if (res == FR_OK && br == BLOCK_SIZE) {
+ res = f_read(&drv_table[drv].fd, disk_buffer, BLOCK_SIZE, &brw);
+ if (res == FR_OK && brw == BLOCK_SIZE) {
if (!(z80_bus_cmd(Request) & ZST_ACQUIRED)) {
buserr = 1;
break;
} else {
- if (cnt) {
- z80_write_block(disk_buffer, addr, cnt);
- addr = addr + cnt - TPA_BASE;
- }
- z80_write_block(disk_buffer+cnt, addr, BLOCK_SIZE - cnt);
+ z80_write_block(disk_buffer, addr, BLOCK_SIZE);
z80_bus_cmd(Release);
}
}
}
- if (br != BLOCK_SIZE) {
- debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res, br);
+ if (brw != BLOCK_SIZE) {
+ debug_cpmsd("## %7lu f_read res: %d, bytes rd/wr: %u\n", get_timer(0), res, brw);
dump_ram(disk_buffer, 0, 64, "Read Data");
res = -1;
}
init_request = z80_read(0x43);
z80_bus_cmd(Release);
if ( init_request != 0) {
- /* Get address of fifo_list */
- uint32_t fifo_addr = 0;
+ /* Get address of fifo 0 */
z80_bus_cmd(Request);
- uint32_t fifo_list = z80_read(0x40) +
- ((uint16_t) z80_read(0x41) << 8) +
- ((uint32_t) z80_read(0x42) << 16);
- if (fifo_list != 0) {
- /* Get address of fifo 0 */
- fifo_addr = z80_read(fifo_list) +
- ((uint16_t) z80_read(fifo_list+1) << 8);
- /* TODO: log to phys addr translation
- ((uint32_t) z80_read(fifo_list+2) << 16);
- */
- }
+ uint32_t fifo_addr = z80_read(0x40) +
+ ((uint16_t) z80_read(0x40+1) << 8) +
+ ((uint32_t) z80_read(0x40+2) << 16);
z80_write(0x43, 0);
z80_bus_cmd(Release);
;\r
global ff.init,ff.in,ff.out,ff.i.st,ff.o.st\r
\r
- extrn buf.init\r
+ extrn bufinit\r
\r
include config.inc\r
if CPU_Z180\r
\r
ff.init:\r
ld ix,ci.fifo\r
- ld a,ci.fifo.mask\r
- call buf.init\r
+ call bufinit\r
ld ix,co.fifo\r
- ld a,co.fifo.mask\r
- jp buf.init\r
+ jp bufinit\r
\r
\r
ff.i.st:\r
\r
COMMON_SIZE equ 16*1024 ;Common Area size in bytes\r
;must be multiple of 4K\r
-\r
if (COMMON_SIZE mod 1000h)\r
.printx COMMON_SIZE not multiple of 4K!\r
end ;stop assembly\r
endif\r
+CMN_SIZE equ COMMON_SIZE/1000h ;4K units\r
+BNK_SIZE equ 64/4 - CMN_SIZE ;bank size (4K units)\r
+BANKS equ (512/4 - CMN_SIZE)/BNK_SIZE ;max nr. of banks\r
+\r
+; Logical address space, CBAR values\r
\r
-CSK equ COMMON_SIZE/1000h ;\r
-CA equ 10h - CSK ;common area start\r
-BA equ 0 ;banked area start\r
+CA equ 10h - CMN_SIZE ;common area start (64K - common size)\r
+BA equ 0 ;banked area start\r
+\r
+ if 0\r
\r
SYS$CBR equ 0\r
SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r
USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r
\r
+ endif\r
+ if 1\r
+\r
+SYS$CBR equ BNK_SIZE\r
+SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r
+USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r
+\r
+ endif\r
\r
-BANKS equ 18 ;max nr. of banks\r
\r
;-----------------------------------------------------\r
\r
DC 'F'\r
DB 0\r
b_0x136C_start:\r
- if ROMSYS\r
- defb 000h\r
- defw uromen\r
+ if ROMSYS\r
+ defb 000h\r
+ defw uromen\r
endif\r
if CPU_Z180\r
- defb 000h\r
- defw ucbar\r
- defb 000h\r
- defw ubbr\r
+ defb 000h\r
+ defw ucbar\r
+ defb 000h\r
+ defw ubbr\r
else\r
- defb 000h\r
- defw ubnk\r
+ defb 000h\r
+ defw ubnk\r
endif\r
- defb 003h\r
- defw reg.c2\r
- defb 003h\r
- defw reg.e2\r
- defb 003h\r
- defw reg.l2\r
- defb 003h\r
- defw reg.c\r
- defb 003h\r
- defw reg.e\r
- defb 003h\r
- defw reg.l\r
- defb 000h\r
- defw reg.a2\r
- defb 000h\r
- defw reg.b2\r
- defb 000h\r
- defw reg.c2\r
- defb 000h\r
- defw reg.d2\r
- defb 000h\r
- defw reg.e2\r
- defb 000h\r
- defw reg.h2\r
- defb 000h\r
- defw reg.l2\r
- defb 000h\r
- defw reg.a\r
- defb 000h\r
- defw reg.b\r
- defb 000h\r
- defw reg.c\r
- defb 000h\r
- defw reg.d\r
- defb 000h\r
- defw reg.e\r
- defb 000h\r
- defw reg.h\r
- defb 000h\r
- defw reg.l\r
- defb 003h\r
- defw reg.ix\r
- defb 003h\r
- defw reg.iy\r
- defb 003h\r
- defw reg.sp\r
- defb 003h\r
- defw reg.pc\r
- defb 003h\r
- defw reg.ix\r
- defb 003h\r
- defw reg.iy\r
- defb 003h\r
- defw reg.sp\r
- defb 003h\r
- defw reg.pc\r
- defb 000h\r
- defw reg.i\r
- defb 000h\r
- defw reg.f2\r
- defb 000h\r
- defw reg.f\r
+ defb 003h\r
+ defw reg.c2\r
+ defb 003h\r
+ defw reg.e2\r
+ defb 003h\r
+ defw reg.l2\r
+ defb 003h\r
+ defw reg.c\r
+ defb 003h\r
+ defw reg.e\r
+ defb 003h\r
+ defw reg.l\r
+ defb 000h\r
+ defw reg.a2\r
+ defb 000h\r
+ defw reg.b2\r
+ defb 000h\r
+ defw reg.c2\r
+ defb 000h\r
+ defw reg.d2\r
+ defb 000h\r
+ defw reg.e2\r
+ defb 000h\r
+ defw reg.h2\r
+ defb 000h\r
+ defw reg.l2\r
+ defb 000h\r
+ defw reg.a\r
+ defb 000h\r
+ defw reg.b\r
+ defb 000h\r
+ defw reg.c\r
+ defb 000h\r
+ defw reg.d\r
+ defb 000h\r
+ defw reg.e\r
+ defb 000h\r
+ defw reg.h\r
+ defb 000h\r
+ defw reg.l\r
+ defb 003h\r
+ defw reg.ix\r
+ defb 003h\r
+ defw reg.iy\r
+ defb 003h\r
+ defw reg.sp\r
+ defb 003h\r
+ defw reg.pc\r
+ defb 003h\r
+ defw reg.ix\r
+ defb 003h\r
+ defw reg.iy\r
+ defb 003h\r
+ defw reg.sp\r
+ defb 003h\r
+ defw reg.pc\r
+ defb 000h\r
+ defw reg.i\r
+ defb 000h\r
+ defw reg.f2\r
+ defb 000h\r
+ defw reg.f\r
CMD.S:\r
- ld hl,(lst.S)\r
- call get_lastarg_def\r
+ ld hl,(lst.S)\r
+ call get_lastarg_def\r
l13d8h:\r
- ld (lst.S),hl\r
- call out.hl.@\r
- call OUTBL\r
+ ld (lst.S),hl\r
+ call out.hl.@\r
+ call OUTBL\r
comst\r
- ld a,(hl)\r
+ ld a,(hl)\r
comend\r
- call out.hex\r
- call outbl2\r
- call INLINE\r
- call SKIPBL\r
- inc hl\r
- jr z,l13d8h\r
- dec hl\r
- inc de\r
- cp '.'\r
- jp z,assert_eol\r
- cp '-'\r
- jr nz,l1406h\r
- ld a,(de)\r
- or a\r
- dec hl\r
- jr z,l13d8h\r
- inc hl\r
+ call out.hex\r
+ call outbl2\r
+ call INLINE\r
+ call SKIPBL\r
+ inc hl\r
+ jr z,l13d8h\r
+ dec hl\r
+ inc de\r
+ cp '.'\r
+ jp z,assert_eol\r
+ cp '-'\r
+ jr nz,l1406h\r
+ ld a,(de)\r
+ or a\r
+ dec hl\r
+ jr z,l13d8h\r
+ inc hl\r
l1406h:\r
- dec de\r
- call get_bytes_m\r
- jr l13d8h\r
+ dec de\r
+ call get_bytes_m\r
+ jr l13d8h\r
\r
CMD.@:\r
- call assert_eol\r
- ld hl,MSG_at\r
- ld de,offs.@\r
- ld c,001h\r
- jp l1279h\r
+ call assert_eol\r
+ ld hl,MSG_at\r
+ ld de,offs.@\r
+ ld c,001h\r
+ jp l1279h\r
MSG_at:\r
dc '@'\r
\r
CMD.I:\r
- ld hl,CMD.I\r
- ld (CMD_RPT),hl\r
- ld hl,(lst.IP)\r
- call get_lastarg_def\r
- ld (lst.IP),hl\r
- ld b,h\r
- ld c,l\r
+ ld hl,CMD.I\r
+ ld (CMD_RPT),hl\r
+ ld hl,(lst.IP)\r
+ call get_lastarg_def\r
+ ld (lst.IP),hl\r
+ ld b,h\r
+ ld c,l\r
if CPU_Z180\r
- ld a,b\r
- or a\r
- jr nz,l1442h\r
- ld a,c\r
- ld hl,ucbar\r
- cp cbar\r
- jr z,l143fh\r
- ld hl,ubbr\r
- cp bbr\r
- jr nz,l1442h\r
+ ld a,b\r
+ or a\r
+ jr nz,l1442h\r
+ ld a,c\r
+ ld hl,ucbar\r
+ cp cbar\r
+ jr z,l143fh\r
+ ld hl,ubbr\r
+ cp bbr\r
+ jr nz,l1442h\r
l143fh:\r
- ld a,(hl)\r
- jr l1444h\r
+ ld a,(hl)\r
+ jr l1444h\r
l1442h:\r
endif\r
- in a,(c)\r
+ in a,(c)\r
l1444h:\r
- push af\r
- call out.hex\r
- call outbl4\r
- pop af\r
- call out.bin.b\r
- jp CRLF\r
+ push af\r
+ call out.hex\r
+ call outbl4\r
+ pop af\r
+ call out.bin.b\r
+ jp CRLF\r
CMD.O:\r
- ld hl,CMD.O\r
- ld (CMD_RPT),hl\r
- ld hl,(lst.OD)\r
- call get_arg_def\r
- ld a,l\r
- ld (lst.OD),a\r
- push af\r
- call skip_to_nextarg\r
- ld hl,(lst.OP)\r
- call get_lastarg_def\r
- ld (lst.OP),hl\r
- ld b,h\r
- ld c,l\r
+ ld hl,CMD.O\r
+ ld (CMD_RPT),hl\r
+ ld hl,(lst.OD)\r
+ call get_arg_def\r
+ ld a,l\r
+ ld (lst.OD),a\r
+ push af\r
+ call skip_to_nextarg\r
+ ld hl,(lst.OP)\r
+ call get_lastarg_def\r
+ ld (lst.OP),hl\r
+ ld b,h\r
+ ld c,l\r
if CPU_Z180\r
- ld a,b\r
- or a\r
- jr nz,l1489h\r
- ld a,c\r
- ld hl,ucbar\r
- cp cbar\r
- jr z,l148dh\r
- ld hl,ubbr\r
- cp bbr\r
- jr z,l148dh\r
- cp cbr\r
- jp z,ERROR\r
+ ld a,b\r
+ or a\r
+ jr nz,l1489h\r
+ ld a,c\r
+ ld hl,ucbar\r
+ cp cbar\r
+ jr z,l148dh\r
+ ld hl,ubbr\r
+ cp bbr\r
+ jr z,l148dh\r
+ cp cbr\r
+ jp z,ERROR\r
l1489h:\r
endif\r
- pop af\r
- out (c),a\r
+ pop af\r
+ out (c),a\r
ret\r
if CPU_Z180\r
l148dh:\r
- pop af\r
- ld (hl),a\r
- ret\r
+ pop af\r
+ ld (hl),a\r
+ ret\r
endif\r
\r
CMD.V:\r
- call get_arg3 ;1490 get from, size, to\r
+ call get_arg3 ;1490 get from, size, to\r
cmp_mem:\r
- push bc\r
+ push bc\r
comst\r
- ld a,(de)\r
- ld b,(hl)\r
+ ld a,(de)\r
+ ld b,(hl)\r
comend\r
- cp b\r
- jr z,l14bah\r
- ld c,a\r
- call out.hl.@\r
- call OUTBL\r
- ld a,b\r
- call out.hex\r
- call outbl2\r
- ld a,c\r
- call out.hex\r
- call OUTBL\r
- ex de,hl\r
- call out.hl.@\r
- ex de,hl\r
- call CRLF\r
+ cp b\r
+ jr z,l14bah\r
+ ld c,a\r
+ call out.hl.@\r
+ call OUTBL\r
+ ld a,b\r
+ call out.hex\r
+ call outbl2\r
+ ld a,c\r
+ call out.hex\r
+ call OUTBL\r
+ ex de,hl\r
+ call out.hl.@\r
+ ex de,hl\r
+ call CRLF\r
l14bah:\r
- pop bc\r
- inc hl\r
- inc de\r
- dec bc\r
- ld a,b\r
- or c\r
- jr nz,cmp_mem\r
+ pop bc\r
+ inc hl\r
+ inc de\r
+ dec bc\r
+ ld a,b\r
+ or c\r
+ jr nz,cmp_mem\r
ret\r
\r
CMD.M:\r
- ld a,(de)\r
- cp 'V'\r
- jr nz,bm_nv\r
- inc de\r
+ ld a,(de)\r
+ cp 'V'\r
+ jr nz,bm_nv\r
+ inc de\r
bm_nv:\r
- push af ;14c9 save 'V' flag\r
- call get_arg3\r
- push hl\r
- push de\r
- push bc\r
- call CP.HL.DE\r
- jr nc,bm_mvdown\r
- add hl,bc\r
- ex de,hl\r
- add hl,bc\r
- ex de,hl\r
- dec hl\r
- dec de\r
+ push af ;14c9 save 'V' flag\r
+ call get_arg3\r
+ push hl\r
+ push de\r
+ push bc\r
+ call CP.HL.DE\r
+ jr nc,bm_mvdown\r
+ add hl,bc\r
+ ex de,hl\r
+ add hl,bc\r
+ ex de,hl\r
+ dec hl\r
+ dec de\r
comst\r
- lddr\r
+ lddr\r
comend\r
- jr bm_done\r
+ jr bm_done\r
bm_mvdown:\r
comst\r
ldir\r
comend\r
bm_done:\r
- pop bc\r
- pop de\r
- pop hl\r
- pop af\r
- jr z,cmp_mem ;14ed validate?\r
+ pop bc\r
+ pop de\r
+ pop hl\r
+ pop af\r
+ jr z,cmp_mem ;14ed validate?\r
ret\r
CMD.H:\r
- call EXPR\r
- jp c,l173ch\r
- call skip_to_nextarg\r
- push hl\r
- call EXPR\r
- push af\r
- call assert_eol\r
- pop af\r
- ex de,hl\r
- pop hl\r
- jr c,l1511h\r
- push hl\r
- push de\r
- add hl,de\r
- call l1511h\r
- pop de\r
- pop hl\r
- and a\r
- sbc hl,de\r
+ call EXPR\r
+ jp c,l173ch\r
+ call skip_to_nextarg\r
+ push hl\r
+ call EXPR\r
+ push af\r
+ call assert_eol\r
+ pop af\r
+ ex de,hl\r
+ pop hl\r
+ jr c,l1511h\r
+ push hl\r
+ push de\r
+ add hl,de\r
+ call l1511h\r
+ pop de\r
+ pop hl\r
+ and a\r
+ sbc hl,de\r
l1511h:\r
- call out.hl ;1511 val\r
- call outbl2\r
- call sub_0928h ;1517 -val\r
- call outbl4\r
- call out.hl.dec ;151d dec\r
- call outbl2\r
- call out.hl.decm ;1523 -dec\r
- call outbl4\r
- call out.bin.w ;1529 bin\r
- call outbl2\r
- ld a,l\r
- call out.ascii\r
- jp CRLF\r
+ call out.hl ;1511 val\r
+ call outbl2\r
+ call sub_0928h ;1517 -val\r
+ call outbl4\r
+ call out.hl.dec ;151d dec\r
+ call outbl2\r
+ call out.hl.decm ;1523 -dec\r
+ call outbl4\r
+ call out.bin.w ;1529 bin\r
+ call outbl2\r
+ ld a,l\r
+ call out.ascii\r
+ jp CRLF\r
\r
CMD.Q:\r
ld a,(de)\r
\r
hwini0:\r
if CPU_Z180\r
- db 3 ;count\r
+ db ;count\r
db rcr,CREFSH ;configure DRAM refresh\r
db dcntl,INIWAITS ;wait states\r
db cbr,SYS$CBR\r
\r
kstart:\r
if CPU_Z180\r
- ld a,SYS$CBR\r
+ ld a,SYS$CBR ;TODO:\r
out0 (cbr),a\r
ld a,SYS$CBAR\r
out0 (cbar),a\r
; call prt0_init\r
endif\r
\r
+ call msginit\r
call charini\r
- call bufferinit\r
\r
if CPU_Z80\r
ld a,0\r
;----------------------------------------------------------------------\r
;\r
\r
- global buf.init\r
+ global bufinit\r
\r
-buf.init:\r
- ld (ix+o.in_idx),0\r
+bufinit:\r
+ ld (ix+o.in_idx),0 ;reset pointers (empty fifo)\r
ld (ix+o.out_idx),0\r
-\r
ld a,(ix+o.id)\r
- cp 4\r
- ret nc\r
-\r
- push de\r
- push hl\r
- ld hl,fifo_list\r
- push hl ;save fifo_list\r
+ ld hl,fifolst\r
ld e,a\r
ld d,0\r
add hl,de\r
add hl,de\r
push ix\r
pop de\r
+ cp 4\r
+ jr nc,bfi_skip\r
+\r
ld (hl),e\r
inc hl\r
ld (hl),d\r
- pop hl ;get fifo_list back\r
- or a\r
- jr nz,bufi_ex\r
\r
- ld (040h),hl\r
- ld (040h+2),a\r
-bufi_ex:\r
- pop hl\r
- pop de\r
+bfi_skip:\r
+ ex de,hl\r
+ call hwl2phy ;get phys. address of fifo\r
+ ld c,a\r
+ ld a,(ix+o.id) ;fifo id\r
+ or a ;test if fifo 0\r
+ ret z\r
\r
+ ld b,a\r
+ push bc ;c: bank-addr, b: ignored\r
+ push hl ;address\r
+ ld c,0\r
+ push bc ;c: function, b:subf\r
+ ld b,5\r
+ ld h,c\r
+ ld l,c\r
+ add hl,sp\r
+ call msg.sm\r
+ pop hl\r
+ pop hl\r
+ pop hl\r
ret\r
\r
-\r
-fifo_list:\r
+ public fifolst\r
+fifolst :\r
rept 4\r
dw 0\r
endm\r
\r
;----------------------------------------------------------------------\r
\r
+ extrn msg.sm\r
extrn msginit,msg.sout\r
extrn mtx.fifo,mrx.fifo\r
- extrn co.fifo,ci.fifo\r
+ extrn ff.init,co.fifo,ci.fifo\r
\r
\r
-bufferinit:\r
+fifoinit:\r
if CPU_Z180\r
- call msginit\r
-\r
- ld hl,buffers\r
- ld b,buftablen\r
-bfi_1:\r
- ld a,(hl)\r
- inc hl\r
- ld (bufdat+0),a\r
- ld e,(hl)\r
- inc hl\r
- ld d,(hl)\r
- inc hl\r
- ex de,hl\r
\r
- or a\r
- jr nz,bfi_2\r
-; call hwl2phy\r
-; ld (40h+0),hl\r
-; ld (40h+2),a\r
- out (AVRINT5),a\r
- jr bfi_3\r
-bfi_2:\r
- call hwl2phy\r
- ld (bufdat+1),hl\r
- ld (bufdat+3),a\r
- ld hl,inimsg\r
- call msg.sout\r
-bfi_3:\r
- ex de,hl\r
- djnz bfi_1\r
ret\r
\r
else ;CPU_Z180\r
ret\r
endif\r
\r
-buffers:\r
- db 0\r
- dw mtx.fifo\r
- db 1\r
- dw mrx.fifo\r
- db 2\r
- dw ci.fifo\r
- db 3\r
- dw co.fifo\r
-buftablen equ ($ - buffers)/3\r
-\r
-inimsg:\r
- db inimsg_e - $ -1\r
- db 0AEh\r
- db inimsg_e - $ -1\r
- db 0\r
-bufdat:\r
- db 0\r
- dw 0\r
- db 0\r
-inimsg_e:\r
+\r
\r
\r
;\r
;\r
;out ahl: Phys. (linear) Address\r
\r
+ public hwl2phy\r
\r
hwl2phy:\r
push bc ;\r
page 255\r
.z80\r
\r
- global mrx.fifo,mtx.fifo\r
+ public mrx.fifo,mtx.fifo\r
\r
- global msginit,msgi.st,msg.in,msgo.st,msg.out\r
- global msg.sout\r
+ public msginit,msgi.st,msg.in,msgo.st\r
+ public msg.sm,msg.sout\r
\r
- extrn buf.init\r
+ extrn bufinit,hwl2phy\r
+ extrn fifolst\r
\r
include config.inc\r
if CPU_Z180\r
;\r
\r
msginit:\r
+ ld a,(043h)\r
+;TODO: value should be 0\r
ld ix,mtx.fifo\r
- ld a,mtx.fifo.mask\r
- call buf.init\r
+ call bufinit\r
+ push ix\r
+ pop hl\r
+ call hwl2phy\r
+ ld (040h),hl\r
+ ld (040h+2),a\r
+ ld a,0ffh\r
+ ld (043h),a\r
+ out (AVRINT5),a\r
+wait:\r
+ ld a,(043h)\r
+ or a\r
+ jr nz,wait\r
+\r
ld ix,mrx.fifo\r
- ld a,mrx.fifo.mask\r
- jp buf.init\r
+ jp bufinit\r
\r
;--------------------------------------------------------------\r
\r
\r
;--------------------------------------------------------------\r
\r
-\r
+ if 0\r
\r
msg.out:\r
push ix\r
pop ix\r
ret\r
\r
+ endif\r
+\r
+;----------------------------------------------------------------------\r
+;\r
+; Put char in message buffer:\r
+; ix: buffer to put into\r
+; c: char\r
+\r
+buf.put:\r
+ push ix ;15\r
+ push bc ;11\r
+ ld a,(ix+o.in_idx) ;19\r
+ ld c,a ;4\r
+ ld b,0 ;7\r
+ add ix,bc ;11\r
+ pop bc ;10\r
+ ld (ix),c ;7\r
+ pop ix ;14\r
+\r
+ inc a ;4\r
+ and (ix+o.mask) ;19 =121\r
+bufp.wait:\r
+ cp (ix+o.out_idx) ;19\r
+ jr z,bufp.wait ;12/7\r
+ ld (ix+o.in_idx),a ;19\r
+\r
+ out (AVRINT5),a ;11\r
+ ld a,c ;4\r
+ ret ;10 =191\r
+\r
\r
;--------------------------------------------------------------\r
\r
\r
;----------------------------------------------------------------------\r
\r
+;----------------------------------------------------------------------\r
+; Send message MEMORY\r
+;\r
+; hl: pointer to message (netto)\r
+; b: msg length\r
+\r
+msg.sm:\r
+ push ix\r
+ ld ix,mtx.fifo\r
+ ld c,0AEh\r
+ call buf.put\r
+ ld c,b\r
+ call buf.put\r
+msm_l:\r
+ ld c,(hl)\r
+ inc hl\r
+ call buf.put\r
+ djnz msm_l\r
+ pop ix\r
+ ret\r
+\r
+\r
end\r
projects / z180-stamp.git / commitdiff