z180/config.inc

   1
   2 FALSE   equ     0
   3 TRUE    equ     NOT FALSE
   4
   5
   6 DEBUG   equ     true
   7
   8 banked  equ     true
   9
  10 ;-----------------------------------------------------
  11 ; CPU and BANKING types
  12
  13
  14 CPU_Z180        equ     TRUE
  15 CPU_Z80         equ     FALSE
  16
  17 ROMSYS          equ     FALSE
  18
  19 AVRCLK          equ     18432           ;[KHz]
  20
  21     if CPU_Z180
  22
  23 ;-----------------------------------------------------
  24 ;FOSC           equ     AVRCLK/2        ;Oscillator frequency [KHz]
  25 ;PHI            equ     FOSC*2          ;CPU frequency (clock doubler enabled)
  26
  27 ;----------------------------------------------------------------------
  28 ; Baudrate Generator for x16 clock mode:
  29 ; TC = (f PHI / (32 * baudrate)) - 2
  30 ;
  31 ;     PHI [MHz]: 9.216 18.432
  32 ;     baudrate     TC     TC
  33 ;     ----------------------
  34 ;      115200       -      3
  35 ;       57600       3      8
  36 ;       38400       -     13
  37 ;       19200      13     28
  38 ;        9600      28     58
  39
  40
  41 ;-----------------------------------------------------
  42 ; Programmable Reload Timer (PRT)
  43
  44 PRT_PRE         equ     20              ;PRT prescaler
  45
  46 ;-----------------------------------------------------
  47 ; MMU
  48
  49 COMMON_SIZE     equ     16*1024         ;Common Area size in bytes
  50                                         ;must be multiple of 4K
  51 if (COMMON_SIZE mod 1000h)
  52         .printx COMMON_SIZE not multiple of 4K!
  53         end     ;stop assembly
  54 endif
  55 CMN_SIZE        equ     COMMON_SIZE/1000h               ;4K units
  56 BNK_SIZE        equ     64/4 - CMN_SIZE                 ;bank size (4K units)
  57 BANKS           equ     (512/4 - CMN_SIZE)/BNK_SIZE     ;max nr. of banks
  58
  59 ; Logical address space, CBAR values
  60
  61 CA              equ     10h - CMN_SIZE          ;common area start (64K - common size)
  62 BA              equ     0                       ;banked area start
  63
  64    if 0
  65
  66 SYS$CBR         equ     0
  67 SYS$CBAR        equ     CA*16 + CA      ;CBAR in system mode
  68 USR$CBAR        equ     CA*16 + BA      ;CBAR in user mode (CP/M)
  69
  70    endif
  71    if 1
  72
  73 SYS$CBR         equ     BNK_SIZE
  74 SYS$CBAR        equ     CA*16 + CA      ;CBAR in system mode
  75 USR$CBAR        equ     CA*16 + BA      ;CBAR in user mode (CP/M)
  76
  77    endif
  78
  79
  80 ;-----------------------------------------------------
  81
  82 CREFSH          equ     0               ;Refresh rate register (disable refresh)
  83 CWAITIO         equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States
  84 PHI_X2          equ     0               ;set to M_X2CM to enable the clock doubler
  85
  86     endif               ;CPU_Z180
  87     if  CPU_Z80
  88
  89 PHI             equ     AVRCLK/5        ;CPU frequency [KHz]
  90 BAUDCLCK        equ     AVRCLK/10       ;Baudrate clock [KHz]
  91 ;BDCLK16                equ
  92
  93 SIOAD   EQU     0bch
  94 SIOAC   EQU     0bdh
  95 SIOBD   EQU     0beh
  96 SIOBC   EQU     0bfh
  97
  98 CTC0    EQU     0f4h
  99 CTC1    EQU     0f5h
 100 CTC2    EQU     0f6h
 101 CTC3    EQU     0f7h
 102
 103 ;
 104 ; Init Serial I/O for console input and output (SIO-A)
 105 ;
 106 ; Baudrate clock: 1843200 Hz (Bus connector pin A17)
 107 ;
 108 ; Baudrate   Divider    SIO     CTC
 109 ; ---------------------------------
 110 ; 115200          16     16       1
 111 ;  57600          32     16       2
 112 ;  38400          48     16       3
 113 ;  19200          96     16       6
 114 ;   9600         192     16      12
 115 ;   4800         384     16      24
 116 ;   2400         768     16      48
 117 ;   1200        1536     16      96
 118 ;    600        3072     16     192
 119 ;    300        6144     64      92
 120
 121     endif       ; CPU_Z80
 122
 123     if  ROMSYS
 124 c$rom           equ     0a5h
 125 ROM_EN          equ     0C0h
 126 ROM_DIS         equ     ROMEN+1
 127      if CPU_Z180
 128 CWAITROM        equ     2 shl MWI0
 129      endif
 130     endif
 131
 132
 133 DDTZRSTVEC      equ     030h            ;DDTZ Restart vector (breakpoints)
 134
 135 INIDONE         equ     03Fh            ;CP/M skip hw init, if this address
 136 INIDONEVAL      equ     080h            ;    is set to this value.
 137
 138 mtx.fifo_len    equ     64              ;Message transfer fifos
 139 mtx.fifo_id     equ     0               ;    This *must* have #0
 140 mrx.fifo_len    equ     64
 141 mrx.fifo_id     equ     1
 142
 143 ci.fifo_len     equ     32              ;AVRCON Character I/O via AVR
 144 ci.fifo_id      equ     2
 145 co.fifo_len     equ     32
 146 co.fifo_id      equ     3
 147
 148 s1.rx_len       equ     128             ;Serial 1 (ASCI1) buffers
 149 s1.rx_id        equ     4               ;
 150 s1.tx_len       equ     128             ;
 151 s1.tx_id        equ     5               ;
 152
 153 AVRINT5         equ     4Fh
 154 AVRINT6         equ     5Fh
 155 ;PMSG           equ     80h
 156
 157 ;-----------------------------------------------------
 158 ; Definition of (logical) top 2 memory pages
 159
 160 sysram_start    equ     0FE00h
 161 bs$stack$size   equ     80
 162
 163 isvsw_loc       equ     0FEE0h
 164
 165 ivtab           equ     0ffc0h          ;int vector table
 166 iv2tab          equ     ivtab + 2*9
 167
 168
 169
 170 ;-----------------------------------------------------
 171
 172 o.id            equ     -4
 173 o.mask          equ     -3
 174 o.in_idx        equ     -2
 175 o.out_idx       equ     -1
 176
 177         .lall
 178
 179 mkbuf   macro   id,name,size
 180   if ((size AND (size-1)) NE 0) OR (size GT 256)
 181     .printx Error: buffer ^size must be power of 2 and in range 0..256!
 182     name&.mask equ ;wrong size error
 183   else
 184     db id
 185     db size-1
 186     ds 2
 187     name:: ds size
 188     name&.mask equ low (size-1)
 189     if size ne 0
 190       name&.end equ $-1
 191       name&.len equ size
 192       name&.id equ id
 193     endif
 194   endif
 195 endm
 196
 197 ;-----------------------------------------------------
 198
 199 inidat  macro
 200         cseg
 201 ??ps.a  defl    $
 202         endm
 203
 204 inidate macro
 205 ??ps.len defl   $ - ??ps.a
 206         dseg
 207         ds      ??ps.len
 208         endm
 209
 210 ;-----------------------------------------------------
 211
 212 b0call  macro   address
 213         call    _b0call
 214         dw      address
 215         endm