Init ports for single step logic on ECB adapter. Use timer 5 instead of timer 4 for...

diff --git a/avr/main.c b/avr/main.c
index 113b4f24310f2cea292503f9e274d7b6fbdba42a..2199454fa0bd9654ea83804c2ebf051594a59d4b 100644 (file)
--- a/avr/main.c
+++ b/avr/main.c
@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
  *
- * SPDX-License-Identifier:    GPL-2.0+
+ * SPDX-License-Identifier:    GPL-2.0
  */
 
 
@@ -9,7 +9,6 @@
 #include <avr/interrupt.h>
 #include <avr/wdt.h>
 #include <stdlib.h>
-#include <stdio.h>
 
 #include "config.h"
 #include "ff.h"
@@ -232,7 +231,7 @@ const char *bootdelay_process(void)
 static
 void autoboot_command(const char *s)
 {
-       debug("### main_loop: bootcmd=\"%s\"\n", s ? s : PSTR("<UNDEFINED>"));
+       debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
        _delay_ms(20);
 
        if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) {
@@ -255,12 +254,12 @@ int main(void)
 {
        extern void setup_mmc(void);
 
+       setup_avr();
        for (int i = 0; i < GPIO_MAX; i++)
                gpio_config(i, INPUT_PULLUP);
-       setup_avr();
        setup_mmc();
-       z80_setup_bus();
        env_init();
+       z80_setup_bus();
 
        if (reset_reason_is_power_on())
                _delay_ms(CONFIG_PWRON_DELAY);

diff --git a/avr/z80-if.c b/avr/z80-if.c
index c49d2146c9e63b058ccb5a2d63ec7b4e4ba4cfd2..e0e230c51f9e00dcad2dc1054a0466748e324c41 100644 (file)
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -1,69 +1,63 @@
 /*
  * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
  *
- * SPDX-License-Identifier:    GPL-2.0+
+ * SPDX-License-Identifier:    GPL-2.0
  */
 
 /**
  *
  * Pin assignments
  *
- * | Z180-Sig   |   AVR-Port    | Dir   |   Special Function    |
- * +------------+---------------+-------+-----------------------+
- * |    A0      | PA    0       |  O    |                       |
- * |    A1      | PA    1       |  O    |                       |
- * |    A2      | PA    2       |  O    |                       |
- * |    A3      | PA    3       |  O    |                       |
- * |    A4      | PA    4       |  O    |                       |
- * |    A5      | PA    5       |  O    |                       |
- * |    A6      | PA    6       |  O    |                       |
- * |    A7      | PA    7       |  O    |                       |
- * |    A8      | PC    0       |  O    |                       |
- * |    A9      | PC    1       |  O    |                       |
- * |    A10     | PC    2       |  O    |                       |
- * |    A11     | PC    3       |  O    |                       |
- * |    A12     | PC    4       |  O    |                       |
- * |    A13     | PC    5       |  O    |                       |
- * |    A14     | PC    6       |  O    |                       |
- * |    A15     | PC    7       |  O    |                       |
- * |    A16     | PE    2       |  O    |                       |
- * |    A17     | PE    3       |  O    |                       |
- * |    A18     | PE    4       |  O    |                       |
- * |    D0      | PF    0       |  I/O  |                       |
- * |    D1      | PF    1       |  I/O  |                       |
- * |    D2      | PF    2       |  I/O  |                       |
- * |    D3      | PF    3       |  I/O  |                       |
- * |    D4      | PF    4       |  I/O  |                       |
- * |    D5      | PF    5       |  I/O  |                       |
- * |    D6      | PF    6       |  I/O  |                       |
- * |    D7      | PF    7       |  I/O  |                       |
- * |    RD      | PD    3       |  O    |                       |
- * |    WR      | PD    2       |  O    |                       |
- * |    MREQ    | PD    4       |  O    |                       |
- * |    RST     | PD    5       |  O    |                       |
- * |    BUSREQ  | PD    7       |  O    |                       |
- * |    BUSACK  | PD    6       |  I    |                       |
- * |    IOCS1   | PE    5       |  I    |                       |
- * |*   HALT    | P             |       |                       |
- * |*   NMI     | P             |       |                       |
- * |            | P             |       |                       |
- * |            | P             |       |  af1   USART1_TX      |
- * |            | P             |       |  af1   USART1_RX      |
- * |            | P             |JTDI   |  remap SPI1_NSS'      |
- * |            | P             |JTDO   |  remap SPI1_SCK'      |
- * |            | P             |JTRST  |  remap SPI1_MISO'     |
- * |            | P             |       |  remap SPI1_MOSI'     |
- * |            | P             |       |  af1   OSC32          |
- * |            | P             |       |  af1   OSC32          |
+ * | Z180-Sig   |   AVR-Port    | Dir   |
+ * +------------+---------------+-------+
+ * |    A0      | PA    0       |  O    |
+ * |    A1      | PA    1       |  O    |
+ * |    A2      | PA    2       |  O    |
+ * |    A3      | PA    3       |  O    |
+ * |    A4      | PA    4       |  O    |
+ * |    A5      | PA    5       |  O    |
+ * |    A6      | PA    6       |  O    |
+ * |    A7      | PA    7       |  O    |
+ * |    A8      | PC    0       |  O    |
+ * |    A9      | PC    1       |  O    |
+ * |    A10     | PC    2       |  O    |
+ * |    A11     | PC    3       |  O    |
+ * |    A12     | PC    4       |  O    |
+ * |    A13     | PC    5       |  O    |
+ * |    A14     | PC    6       |  O    |
+ * |    A15     | PC    7       |  O    |
+ * |    A16     | PE    2       |  O    |
+ * |    A17     | PE    3       |  O    |
+ * |    A18     | PE    4       |  O    |
+ * |    D0      | PF    0       |  I/O  |
+ * |    D1      | PF    1       |  I/O  |
+ * |    D2      | PF    2       |  I/O  |
+ * |    D3      | PF    3       |  I/O  |
+ * |    D4      | PF    4       |  I/O  |
+ * |    D5      | PF    5       |  I/O  |
+ * |    D6      | PF    6       |  I/O  |
+ * |    D7      | PF    7       |  I/O  |
+ * |    RD      | PD    3       |  O    |
+ * |    WR      | PD    2       |  O    |
+ * |    MREQ    | PD    4       |  O    |
+ * |    RST     | PD    5       |  O    |
+ * |    BUSREQ  | PD    7       |  O    |
+ * |    BUSACK  | PD    6       |  I    |
+ * |
+ * | Optional
+ * +------------------------------------+
+ * |    STEP    | PG    0       |  O    |
+ * |    RUN     | PG    1       |  O    |
+ * |    WAIT    | PG    2       |  I    |
 
  */
 
 
-#include "common.h"
+#include "z80-if.h"
 #include <util/atomic.h>
 #include "debug.h"
-#include "z80-if.h"
-
+#include "config.h"
+#include "env.h"
 
 
 //#define P_ZCLK               PORTB
@@ -83,13 +77,6 @@
 #define PIN_BUSACK     PIND
 #define BUSACK         6
 #define DDR_BUSACK     DDRD
-//#define P_HALT               PORTA
-//#define HALT         12
-#define P_IOCS1                PORTE
-#define IOCS1          5
-#define DDR_IOCS1              DDRE
-//#define P_NMI                PORTB
-//#define NMI          7
 #define P_RST          PORTD
 #define DDR_RST                DDRD
 #define RST            5
@@ -122,6 +109,24 @@
 #define Z80_I_BUSACK   SBIT(PIN_BUSACK, 6)
 //#define Z80_I_HALT   SBIT(P_HALT, )
 
+/* Optional */
+#define P_RUN          PORTG
+#define RUN                    1
+#define DDR_RUN                DDRG
+#define P_STEP         PORTG
+#define STEP           0
+#define DDR_STEP       DDRG
+#define P_WAIT         PORTG
+#define WAIT           2
+#define DDR_WAIT       DDRG
+/* All three signals are on the same Port (PortG) */
+#define PORT_SS                PORTG
+#define DDR_SS         DDRG
+#define PIN_SS         PING
+#define        Z80_O_RUN       SBIT(PORT_SS, RUN)
+#define        Z80_O_STEP      SBIT(PORT_SS, STEP)
+#define        Z80_I_WAIT      SBIT(PORT_SS, WAIT)
+
 
 #define BUS_TO 20
 
@@ -130,13 +135,6 @@
 #define SMASK(w,s) (MASK(w) << (s))
 
 
-typedef union {
-       uint32_t l;
-       uint16_t w[2];
-       uint8_t b[4];
-} addr_t;
-
-
 static zstate_t zstate;
 static volatile uint8_t timer;         /* used for bus timeout */
 
@@ -144,7 +142,7 @@ static volatile uint8_t timer;              /* used for bus timeout */
 /* 10Hz timer interrupt generated by OC4A                  */
 /*---------------------------------------------------------*/
 
-ISR(TIMER4_COMPA_vect)
+ISR(TIMER5_COMPA_vect)
 {
 
        uint8_t i = timer;
@@ -156,7 +154,7 @@ ISR(TIMER4_COMPA_vect)
 /*--------------------------------------------------------------------------*/
 
 
-static void z80_addrbus_set_tristate(void)
+static void z80_addrbus_set_in(void)
 {
        /* /MREQ, /RD, /WR: Input, no pullup */
        DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
@@ -173,7 +171,7 @@ static void z80_addrbus_set_tristate(void)
 }
 
 
-static void z80_addrbus_set_active(void)
+static void z80_addrbus_set_out(void)
 {
        /* /MREQ, /RD, /WR: Output and high */
        Z80_O_MREQ = 1;
@@ -210,32 +208,38 @@ static void z80_reset_pulse(void)
 
 void z80_setup_bus(void)
 {
-       /* /ZRESET: Output and low */
-       Z80_O_RST = 0;
-       DDR_RST |= _BV(RST);
+       ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+
+               /* /ZRESET: Output and low */
+               Z80_O_RST = 0;
+               DDR_RST |= _BV(RST);
 
-       /* /BUSREQ: Output and high */
-       Z80_O_BUSREQ = 1;
-       DDR_BUSREQ |= _BV(BUSREQ);
+               /* /BUSREQ: Output and high */
+               Z80_O_BUSREQ = 1;
+               DDR_BUSREQ |= _BV(BUSREQ);
 
-       /* /BUSACK: Input, no pullup */
-       DDR_BUSACK &= ~_BV(BUSACK);
-       P_BUSACK &= ~_BV(BUSACK);
+               /* /BUSACK: Input, no pullup */
+               DDR_BUSACK &= ~_BV(BUSACK);
+               P_BUSACK &= ~_BV(BUSACK);
 
-       /* /IOCS1: Input, no pullup */
-       DDR_IOCS1 &= ~_BV(IOCS1);
-       P_IOCS1 &= ~_BV(IOCS1);
+               z80_addrbus_set_in();
+               z80_dbus_set_in();
 
-       z80_addrbus_set_tristate();
-       z80_dbus_set_in();
+               if (getenv_yesno(PSTR(ENV_SINGLESTEP))) {
+                       /* /RUN & /STEP: output, /WAIT: input */
 
-       zstate = RESET;
+                       PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP);
+                       DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
+               }
+
+               zstate = RESET;
+       }
 
-       /* Timer 4 */
-       PRR1 &= ~_BV(PRTIM4);
-       OCR4A = F_CPU / 1024 / 10 - 1;            /* Timer: 10Hz interval (OC4A) */
-       TCCR4B = (0b01<<WGM42)|(0b101<<CS30); /* CTC Mode, Prescaler 1024 */
-       TIMSK4 = _BV(OCIE4A);                             /* Enable oca interrupt */
+       /* Timer 5 */
+       PRR1 &= ~_BV(PRTIM5);
+       OCR5A = F_CPU / 1024 / 10 - 1;            /* Timer: 10Hz interval (OC4A) */
+       TCCR5B = (0b01<<WGM52)|(0b101<<CS40); /* CTC Mode, Prescaler 1024 */
+       TIMSK5 = _BV(OCIE5A);                             /* Enable oca interrupt */
 
 }
 
@@ -249,20 +253,34 @@ zstate_t z80_bus_state(void)
 static void z80_busreq_hpulse(void)
 {
        z80_dbus_set_in();
-       z80_addrbus_set_tristate();
+       z80_addrbus_set_in();
 
+#if 0
        ATOMIC_BLOCK(ATOMIC_FORCEON) {
                Z80_O_BUSREQ = 1;
                Z80_O_BUSREQ = 1;       /* 2 AVR clock cycles */
                Z80_O_BUSREQ = 0;       /* 2 AVR clock cycles */
        }
+#endif
+
+       ATOMIC_BLOCK(ATOMIC_FORCEON) {
+               Z80_O_BUSREQ = 1;
+
+               do {
+                       if (Z80_I_BUSACK == 1)  {
+                               Z80_O_BUSREQ = 0;
+                               break;
+                       }
+               } while (1);
+       }
+
 
        if (zstate & ZST_ACQUIRED) {
                timer = BUS_TO;
                while (Z80_I_BUSACK == 1 && timer)
                        ;
                if (Z80_I_BUSACK == 0)
-                       z80_addrbus_set_active();
+                       z80_addrbus_set_out();
        }
 }
 
@@ -302,7 +320,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 
        case Reset:
                z80_dbus_set_in();
-               z80_addrbus_set_tristate();
+               z80_addrbus_set_in();
                Z80_O_RST = 0;
                Z80_O_BUSREQ = 1;
                zstate = RESET;
@@ -317,7 +335,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
                        while (Z80_I_BUSACK == 1 && timer)
                                ;
                        if (Z80_I_BUSACK == 0) {
-                               z80_addrbus_set_active();
+                               z80_addrbus_set_out();
                                zstate = RESET_AQRD;
                        } else {
                                Z80_O_RST = 0;
@@ -331,7 +349,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
                        while (Z80_I_BUSACK == 1 && timer)
                                ;
                        if (Z80_I_BUSACK == 0) {
-                               z80_addrbus_set_active();
+                               z80_addrbus_set_out();
                                zstate = RUNNING_AQRD;
                        } else {
                                Z80_O_BUSREQ = 1;
@@ -347,14 +365,14 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
                switch (zstate) {
                case RESET_AQRD:
                        z80_dbus_set_in();
-                       z80_addrbus_set_tristate();
+                       z80_addrbus_set_in();
                        Z80_O_RST = 0;
                        Z80_O_BUSREQ = 1;
                        zstate = RESET;
                        break;
                case RUNNING_AQRD:
                        z80_dbus_set_in();
-                       z80_addrbus_set_tristate();
+                       z80_addrbus_set_in();
                        Z80_O_BUSREQ = 1;
                        zstate = RUNNING;
                        break;
@@ -372,9 +390,9 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 
                case RESET_AQRD:
                        z80_dbus_set_in();
-                       z80_addrbus_set_tristate();
+                       z80_addrbus_set_in();
                        z80_reset_pulse();
-                       z80_addrbus_set_active();
+                       z80_addrbus_set_out();
                        zstate = RUNNING_AQRD;
                        break;
                default:
@@ -412,11 +430,9 @@ static
 //inline __attribute__ ((always_inline))
 void z80_setaddress(uint32_t addr)
 {
-       addr_t x; x.l = addr;
-
-       P_ADL = x.b[0];
-       P_ADH = x.b[1];
-       PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ;
+       P_ADL = addr;
+       P_ADH = (addr & 0xff00) >> 8;
+       PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
 }
 
 void z80_write(uint32_t addr, uint8_t data)

diff --git a/include/common.h b/include/common.h
index 10c4417d8b0c147de15a20e142a81fb93265a9d6..dea638aa7d0261f808890992a4065a4d30317e85 100644 (file)
--- a/include/common.h
+++ b/include/common.h
@@ -1,12 +1,15 @@
 /*
  * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
  *
- * SPDX-License-Identifier:    GPL-2.0+
+ * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef COMMON_H
 #define COMMON_H
 
+#include <stdio.h>
+#include <stdint.h>
+
 #ifdef __AVR__
 #include <avr/io.h>
 #include <avr/pgmspace.h>
@@ -36,8 +39,6 @@ struct bits {
 // TODO: stm32
 #endif /* __AVR__ */
 
-#include <stdio.h>
-
 #ifdef __FLASH
 #define FLASH __flash
 #define MEMX __memx

diff --git a/include/config.h b/include/config.h
index e4e609679c31c3926e68090d262ca0dcc8293320..7fc1b5ef38eaf7d16c68c742bdf0014269fe74ce 100644 (file)
--- a/include/config.h
+++ b/include/config.h
@@ -9,32 +9,34 @@
 
 /* Environment variables */
 
-#define ENV_BAUDRATE   "baudrate"
-#define ENV_BOOTDELAY  "bootdelay"
-#define ENV_BOOTCMD    "bootcmd"
+#define ENV_BAUDRATE                   "baudrate"
+#define ENV_BOOTDELAY                  "bootdelay"
+#define ENV_BOOTCMD                            "bootcmd"
 
-#define ENV_CPM3_SYSFILE       "cpm3_file"
+#define ENV_CPM3_SYSFILE               "cpm3_file"
 #define ENV_CPM3_COMMON_BASE   "cpm3_commonbase"
 #define ENV_CPM3_BANKED_BASE   "cpm3_bankedbase"
 
-#define ENV_PINALIAS   "pin_alias"
-#define ENV_STARTADDRESS       "startaddress"
-#define ENV_ESC_CHAR           "esc_char"
+#define ENV_PINALIAS                   "pin_alias"
+#define ENV_STARTADDRESS               "startaddress"
+#define ENV_ESC_CHAR                   "esc_char"
 
-#define CONFIG_ENV_SIZE                1600
-#define CONFIG_ENV_OFFSET      0
-#define CONFIG_ENVVAR_MAX      20
+#define ENV_SINGLESTEP                 "singlestep"
 
-#define CONFIG_BAUDRATE                115200L
-#define CONFIG_PWRON_DELAY     2000    /* ms to wait after power on */
-#define CONFIG_BOOTDELAY       4
+#define CONFIG_ENV_SIZE                        1600
+#define CONFIG_ENV_OFFSET              0
+#define CONFIG_ENVVAR_MAX              20
+
+#define CONFIG_BAUDRATE                        115200L
+#define CONFIG_PWRON_DELAY             2000    /* ms to wait after power on */
+#define CONFIG_BOOTDELAY               4
 //#define CONFIG_ZERO_BOOTDELAY_CHECK  1
 
-#define CONFIG_CPM3_SYSFILE    "1:/cpm3.sys"
-#define CONFIG_CPM3_COMMON_BASE        0xC000
-#define CONFIG_CPM3_BANKED_BASE        0x0
-#define CONFIG_CPM3_COMMON_BASE_STR "C000"
-#define CONFIG_CPM3_BANKED_BASE_STR "0"
+#define CONFIG_CPM3_SYSFILE                    "1:/cpm3.sys"
+#define CONFIG_CPM3_COMMON_BASE                0xC000
+#define CONFIG_CPM3_BANKED_BASE                0x0
+#define CONFIG_CPM3_COMMON_BASE_STR    "C000"
+#define CONFIG_CPM3_BANKED_BASE_STR    "0"
 
 #define CONFIG_CMD_MEMTEST
 #define CONFIG_MX_CYCLIC

diff --git a/include/z80-if.h b/include/z80-if.h
index 676d37d9b23e9121d8e4b623cb02f0b4d8c3486c..ef87e5ae0435194f0264f0ab86b539925b4387b3 100644 (file)
--- a/include/z80-if.h
+++ b/include/z80-if.h
@@ -1,8 +1,9 @@
 /*
  * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
  *
- * SPDX-License-Identifier:    GPL-2.0+
+ * SPDX-License-Identifier:    GPL-2.0
  */
+#include "common.h"
 
 #define ZST_ACQUIRED   0x01
 #define ZST_RUNNING    0x02