#endif
+ISR(INT5_vect)
+{
+ Stat |= S_MSG_PENDING;
+}
+
static
void setup_avr(void)
{
OCR3A = F_CPU / 1000 - 1; /* Timer3: 1000Hz interval (OC3A) */
TCCR3B = (0b01<<WGM32)|(0b001<<CS30); /* CTC Mode, Prescaler 1 */
TIMSK3 = _BV(OCIE3A); /* Enable TC2.oca interrupt */
+
+ /* INT5 falling edge */
+ EICRB = (EICRB & ~(0b11 << ISC50)) | 0b10 << ISC50;
+ /* Enable INT5 */
+ EIMSK |= _BV(INT5);
}
static
/*--------------------------------------------------------------------------*/
-uint32_t z80_sram_cmp(uint32_t addr, uint32_t length, uint8_t wval, int inc)
-{
- uint8_t rval;
- int_fast8_t errors = 0;
-
- DBG_P(1, "SRAM: Check 0x%.5lx byte... ", length);
- while (length--) {
- if ((rval = z80_read(addr)) != wval) {
- if (errors == 0) {
- DBG_P(1, "\nSRAM: Address W R\n" \
- " ------------------\n");
- }
- errors++;
- if (errors > 20) {
- DBG_P(1, " ...\n");
- break;
- }
- DBG_P(1, " 0x%.5lx 0x%.2x 0x%.2x\n", addr, wval, rval);
- }
- addr++;
- wval += inc;
- }
- DBG_P(1, "Done.\n");
-
- return addr;
-}
-
-void z80_sram_fill(uint32_t addr, uint32_t length, uint8_t startval, int inc)
-{
- printf("SRAM: Write 0x%.5lx byte... ", length);
- while (length--) {
- z80_write(addr, startval);
- ++addr;
- startval += inc;
- }
- printf("Done.\n");
-}
-
-
-#if 0
-void z80_sram_fill_string(uint32_t addr, int length, const char *text)
-{
- char c;
- const char *p = text;
-
- while (length--) {
- z80_write(addr++, c = *p++);
- if (c == 0)
- p = text;
- }
-}
-
-
-uint32_t z80_sram_cmp_string(uint32_t addr, int length, const char *text)
-{
- char c;
- const char *p = text;
-
- while (length--) {
- c = *p++;
- if (z80_read(addr) != c)
- break;
- ++addr;
- if (c == 0)
- p = text;
- }
- return addr;
-}
-
-const char * const qbfox = "Zhe quick brown fox jumps over the lazy dog!";
-const char * const qbcat = "Zhe quick brown fox jumps over the lazy cat!";
-
-#endif
uint8_t z80_get_byte(uint32_t adr)
{
{
int rc = 1;
- if (fifo_dsc[f].base != 0) {
+ if (((Stat & S_MSG_PENDING) || f != fifo_in) && fifo_dsc[f].base != 0)
+ {
uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
uint8_t idx;
z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
z80_bus_cmd(Release);
}
-
-/*--------------------------------------------------------------------------*/
-/*
- TODO: Rewrite msg_fifo routines for AVR
-*/
-
-static struct {
- uint32_t base;
- //uint8_t idx_out, idx_in;
- uint16_t count;
- uint8_t buf[256];
- } msg_fifo;
-
-/*--------------------------------------------------------------------------*/
-
-#if 0
-
-static void tim1_setup(void)
-{
- RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
- RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
-
- TIM1_CR1 = 0;
-
- TIM1_SMCR = 0
- /* | TIM_SMCR_ETP */
- /* | TIM_SMCR_ETF_CK_INT_N_2 */
- | TIM_SMCR_TS_ETRF
- | TIM_SMCR_SMS_OFF
- ;
-
- TIM1_DIER = TIM_DIER_TDE;
-
-
- TIM1_CCMR1 = 0
- | TIM_CCMR1_OC1M_FORCE_LOW
- | TIM_CCMR1_CC1S_OUT;
-
- TIM1_SMCR |= TIM_SMCR_SMS_TM;
-}
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-void z80_setup_msg_fifo(void)
-{
-
-
-// gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
-// GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
-
-//...
-
-// msg_fifo.count = NELEMS(msg_fifo.buf);
- msg_fifo.count = 0;
- msg_fifo.base = 0;
-
-}
-
-
-void z80_init_msg_fifo(uint32_t addr)
-{
-
-DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
-
- z80_bus_cmd(Request);
- z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
- z80_bus_cmd(Release);
- msg_fifo.base = addr;
-}
-
-
-int z80_msg_fifo_getc(void)
-{
- int c = -1;
-
-#if 0
- if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
- c = msg_fifo.buf[msg_fifo.count];
- if (++msg_fifo.count == NELEMS(msg_fifo.buf))
- msg_fifo.count = 0;
-
- if (msg_fifo.base != 0) {
- z80_bus_cmd(Request);
- z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
- z80_bus_cmd(Release);
- }
- }
-#endif
-
- return c;
-}
#endif /* __AVR__ */
#define S_10MS_TO (1<<0)
-#define S_Z180_RUNNING (2<<0)
+#define S_MSG_PENDING (2<<0)
static inline
void my_puts(const char *s)
uint8_t z80_memfifo_getc(const fifo_t f);
void z80_memfifo_putc(fifo_t f, uint8_t val);
-void z80_setup_msg_fifo(void);
-void z80_init_msg_fifo(uint32_t addr);
-int z80_msg_fifo_getc(void);
SRC = r3init.180
SRC += ddtz.180
#SRC += fifoio.180 msgbuf.180 ser1-i.180 console.180
-SRC += ser1-i.180 console.180
+SRC += msgfifo.180 ser1-i.180 console.180
+#SRC += ser1-i.180 console.180
SRC += romend.180
DRSTNUM equ 30h ;DDTZ Restart vector (breakpoints)\r
\r
\r
-msg_fb_len equ 256\r
-rx.buf_len equ 20h\r
-tx.buf_len equ 80h\r
-rx.buf_len equ 20h\r
-tx.buf_len equ 80h\r
+msg_rx_fifo_len equ 256\r
+msg_tx_fifo_len equ 256\r
\r
\r
s1.rx_len equ 256 ;Serial 1 (ASCI1) buffers\r
s1.tx_len equ 256 ;\r
\r
-PMSG equ 80h\r
+AVRINT5 equ 40h\r
+AVRINT6 equ 50h\r
+;PMSG equ 80h\r
\r
;-----------------------------------------------------\r
; Definition of (locical) top 2 memory pages\r
\r
\r
extrn ser.init,ser.instat,ser.in,ser.out\r
-; extrn f.init,f.in,f.out,f.i.st\r
-; extrn msg.co\r
+ extrn msginit,msg.in,msg.out,msgi.st\r
+ extrn msg.co\r
\r
\r
include config.inc\r
;\r
\r
$coninit:\r
-; call f.init\r
+ call msginit\r
call ser.init\r
ret\r
\r
$cists:\r
-; call f.i.st\r
-; ret nz\r
+ call msgi.st\r
+ ret nz\r
call ser.instat\r
ret\r
\r
$ci:\r
-; call f.i.st\r
-; jp nz,f.in\r
+ call msgi.st\r
+ jp nz,msg.in\r
call ser.instat\r
jp nz,ser.in\r
jr $ci\r
; jp f.o.st\r
\r
$co:\r
-; call msg.co\r
+ call msg.co\r
jp ser.out\r
\r
end\r
--- /dev/null
+ page 255\r
+ .z80\r
+ \r
+ global msg_rx_fifo,msg_tx_fifo\r
+\r
+ global msginit,msgi.st,msg.in,msgo.st,msg.out\r
+ global msg.sout,msg.co\r
+ \r
+ extrn buf.init\r
+\r
+ include config.inc\r
+ include z180reg.inc\r
+\r
+;--------------------------------------------------------------\r
+\r
+ dseg\r
+\r
+ mkbuf msg_rx_fifo,msg_rx_fifo_len\r
+ mkbuf msg_tx_fifo,msg_tx_fifo_len\r
+\r
+\r
+\r
+;--------------------------------------------------------------\r
+\r
+ cseg\r
+\r
+;\r
+; Init buffer\r
+;\r
+ \r
+msginit:\r
+ ld ix,msg_rx_fifo\r
+ ld a,msg_rx_fifo.mask\r
+ call buf.init\r
+ ld ix,msg_tx_fifo\r
+ ld a,msg_tx_fifo.mask\r
+ jp buf.init\r
+\r
+;--------------------------------------------------------------\r
+\r
+msgi.st:\r
+ push ix\r
+ ld ix,msg_rx_fifo ;\r
+\r
+buf.empty:\r
+ ld a,(ix+o.in_idx) ;\r
+ sub (ix+o.out_idx) ;\r
+ pop ix\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+ \r
+;--------------------------------------------------------------\r
+\r
+msg.in:\r
+ push ix\r
+ ld ix,msg_rx_fifo ;\r
+\r
+buf.get:\r
+ ld a,(ix+o.out_idx) ;\r
+bg.wait:\r
+ cp (ix+o.in_idx) ;\r
+ jr z,bg.wait\r
+\r
+ push hl ;\r
+ push ix\r
+ pop hl\r
+ add a,l\r
+ ld l,a\r
+ jr nc,bg.nc\r
+ inc h\r
+bg.nc:\r
+ ld l,(hl)\r
+ \r
+ ld a,(ix+o.out_idx) ;\r
+ inc a\r
+ and (ix+o.mask)\r
+ ld (ix+o.out_idx),a\r
+ \r
+ ld a,l\r
+ pop hl\r
+ pop ix\r
+ ret\r
+\r
+;--------------------------------------------------------------\r
+\r
+msgo.st:\r
+ push ix\r
+ ld ix,msg_tx_fifo ;\r
+\r
+buf.full:\r
+ ld a,(ix+o.in_idx) ;\r
+ inc a\r
+ and (ix+o.mask)\r
+ sub (ix+o.out_idx) ;\r
+ pop ix\r
+ ret z\r
+ or 0ffh\r
+ ret\r
+\r
+;--------------------------------------------------------------\r
+\r
+msg.out:\r
+ push ix\r
+ ld ix,msg_tx_fifo ;\r
+\r
+buf.put:\r
+ push hl ;\r
+ push bc\r
+ push ix\r
+ pop hl\r
+ ld c,(ix+o.in_idx) ;\r
+ ld b,0\r
+ add hl,bc\r
+ ld b,a\r
+\r
+ ld a,c ;\r
+ inc a\r
+ and (ix+o.mask)\r
+bp.wait:\r
+ cp (ix+o.out_idx) ;\r
+ jr z,bp.wait\r
+ ld (hl),b\r
+ ld (ix+o.in_idx),a\r
+ \r
+ ld a,b\r
+ out0 (AVRINT5),a\r
+ pop bc\r
+ pop hl\r
+ pop ix\r
+ ret\r
+\r
+\r
+;--------------------------------------------------------------\r
+;--------------------------------------------------------------\r
+;--------------------------------------------------------------\r
+\r
+if 0\r
+msg.out:\r
+ push ix\r
+ ld ix,msg_fifo ;\r
+\r
+ push bc\r
+ ld b,a ;save char\r
+ ld a,(ix+o.in_idx) ;\r
+ inc a\r
+ and (ix+o.mask)\r
+bp.wait:\r
+ cp (ix+o.out_idx) ;\r
+ jr z,bp.wait\r
+ ld c,a\r
+ ld a,b\r
+ out (PMSG),a\r
+ ld (ix+o.in_idx),c\r
+ \r
+ pop bc\r
+ pop ix\r
+ ret\r
+endif\r
+\r
+;--------------------------------------------------------------\r
+;\r
+; (hl): data\r
+\r
+msg.sout:\r
+ push ix\r
+ ld ix,msg_tx_fifo ;\r
+\r
+ push bc\r
+ push de\r
+ ld b,(hl) ;\r
+ inc hl\r
+ ex de,hl\r
+ \r
+ms.ol:\r
+ push ix\r
+ pop hl\r
+ ld c,(ix+o.in_idx) ;\r
+ ld a,c\r
+ add l\r
+ ld l,a\r
+ jr nc,ms.on\r
+ inc h\r
+ms.on:\r
+ ld a,c ;\r
+ inc a\r
+ and (ix+o.mask)\r
+ms.wait:\r
+ cp (ix+o.out_idx) ;\r
+ jr z,ms.wait\r
+ ld c,a\r
+ ld a,(de)\r
+ inc de\r
+ ld (hl),a\r
+ ld (ix+o.in_idx),c\r
+ djnz ms.ol\r
+ out0 (AVRINT5),a\r
+ ex de,hl\r
+ pop de\r
+ pop bc\r
+ pop ix\r
+ ret\r
+\r
+;--------------------------------------------------------------\r
+\r
+if 0\r
+msg.sout:\r
+ push ix\r
+ ld ix,msg_fifo ;\r
+ push bc\r
+\r
+ ld b,(hl) ;count\r
+ inc hl\r
+obs_1:\r
+ ld a,(ix+o.out_idx) ;\r
+ sub (ix+o.in_idx) ;\r
+ dec a\r
+ and (ix+o.mask)\r
+ cp b\r
+ jr c,obs_1\r
+\r
+ ld c,(hl) ;port address\r
+ inc hl\r
+ ld a,b\r
+ otir\r
+ add (ix+o.in_idx)\r
+ and (ix+o.mask)\r
+ ld (ix+o.in_idx),a\r
+ pop bc\r
+ pop ix\r
+ ret\r
+\r
+;----------------------------------------------------------------------\r
+endif\r
+\r
+msg.co:\r
+ push af\r
+ push hl\r
+ ld (buf_char),a\r
+ ld hl,buf\r
+ call msg.sout\r
+ pop hl\r
+ pop af\r
+ ret\r
+ \r
+ \r
+buf:\r
+ db buf_end - $ - 1 ;output string length\r
+ db 081h ; message start token\r
+ db buf_end - $ - 1 ; message length\r
+ db 1 ; command\r
+ db 1 ; subcommand\r
+buf_char:\r
+ db 0 ; pay load\r
+buf_end:\r
+\r
+;----------------------------------------------------------------------\r
+\r
+ end\r
+\r
\r
ld a,M_NCD ;No Clock Divide\r
out0 (ccr),a\r
- ld a,M_X2CM ;X2 Clock Multiplier\r
- out0 (cmr),a\r
+; ld a,M_X2CM ;X2 Clock Multiplier\r
+; out0 (cmr),a\r
\r
; search warm start mark\r
\r
\r
call prt0_init\r
\r
-\r
-;;; call bufferinit\r
-\r
-\r
call $coninit\r
\r
+ call bufferinit\r
\r
\r
\r
ld e,a ;\r
jp ddtz ;0290\r
\r
-\r
;\r
;----------------------------------------------------------------------\r
;\r
ret\r
\r
;----------------------------------------------------------------------\r
-if 0\r
- extrn msginit,msg.sout,msg_fifo\r
- extrn tx.buf,rx.buf\r
\r
+ extrn msginit,msg_tx_fifo,msg_rx_fifo\r
+ extrn msg.sout\r
\r
bufferinit:\r
- call msginit\r
\r
- ld hl,buffers\r
- ld bc,0300h\r
-bfi_1:\r
- ld e,(hl)\r
- inc hl\r
- ld d,(hl)\r
- inc hl\r
- push hl\r
+ ld de,msg_tx_fifo\r
in0 a,cbr\r
call log2phys\r
ld (40h+0),hl\r
ld (40h+2),a\r
- ld a,c\r
+\r
+ ld (bufdat+1),hl\r
+ ld (bufdat+3),a\r
+ xor a\r
ld (bufdat+0),a\r
ld hl,inimsg\r
call msg.sout\r
- pop hl\r
- inc c\r
- djnz bfi_1\r
- ret\r
\r
- rept 20\r
- db 0\r
- endm\r
+ ld de,msg_rx_fifo\r
+ in0 a,cbr\r
+ call log2phys\r
+ ld (bufdat+1),hl\r
+ ld (bufdat+3),a\r
+ ld a,1\r
+ ld (bufdat+0),a\r
+ ld hl,inimsg\r
+ call msg.sout\r
\r
-buffers:\r
- dw msg_fifo\r
- dw tx.buf\r
- dw rx.buf\r
+ ret\r
\r
inimsg:\r
- db inimsg_e - $ -2\r
- db PMSG\r
+ db inimsg_e - $ - 1\r
db 81h\r
- db inimsg_e - $ -1\r
+ db inimsg_e - $ - 1\r
db 0\r
bufdat:\r
db 0\r
dw 0\r
db 0\r
inimsg_e:\r
-endif\r
+\r
;----------------------------------------------------------------------\r
;\r
if 0\r
call msginit\r
\r
ld hl,buffers\r
- ld bc,0300h\r
+ ld bc,0300h ; b:count, c:buffer nr\r
bfi_1:\r
ld e,(hl)\r
inc hl\r
projects / z180-stamp.git / commitdiff