Add unique id to fifos

diff --git a/z180/asci1-i.180 b/z180/asci1-i.180
index 2410e3804ed64b6f0e3126f7a0830fbdea0ab330..15e121a0775d11bc63961b7e129c9ca639230475 100644 (file)
--- a/z180/asci1-i.180
+++ b/z180/asci1-i.180
@@ -4,12 +4,12 @@
        extrn   buf.init\r
        extrn   isv_sw\r
 \r
-       \r
+\r
        global  ser.init\r
        global  ser.ist,ser.in\r
        global  ser.ost,ser.out\r
 \r
-;TODO: define a trampoline area somewhere in top ram. \r
+;TODO: define a trampoline area somewhere in top ram.\r
 rtxisvjmp      equ     0FF60h  ;momentan frei...\r
 \r
        include config.inc\r
@@ -19,10 +19,10 @@ rtxisvjmp   equ     0FF60h  ;momentan frei...
 ;-----------------------------------------------------\r
 \r
        dseg\r
-       \r
+\r
 buf_start:\r
-       mkbuf   ser1.inbuf,s1.rx_len\r
-       mkbuf   ser1.outbuf,s1.tx_len\r
+       mkbuf   s1.rx_id, ser1.inbuf, s1.rx_len\r
+       mkbuf   s1.tx_id, ser1.outbuf, s1.tx_len\r
 buf_end:\r
 \r
 \r
@@ -33,7 +33,7 @@ buf_end:
 ;\r
 ; Init Serial I/O for console input and output (ASCI1)\r
 ;\r
-       \r
+\r
 \r
 ser.init:\r
 ;      ld      a,i\r
@@ -42,10 +42,10 @@ ser.init:
 \r
        xor     a               ;\r
        out0    (stat1),a       ;Disable rx/tx interrupts\r
-               \r
+\r
        ld hl,rxtx_src          ;move rx and tx isv to common ram\r
        ld de,rxtx_dst          ;\r
-       ld bc,rxtx_src_e-rxtx_src ;     \r
+       ld bc,rxtx_src_e-rxtx_src ;\r
        ldir                    ;\r
 \r
        ld hl,rtxisvjmp         ;rx/tx int vector\r
@@ -59,7 +59,7 @@ ser.init:
 \r
 ; ASCI1: 8N1, highest baudrate (56700), CTS disabled\r
 \r
-       ld      a,M_MPBT \r
+       ld      a,M_MPBT\r
        out0    (cntlb1),a\r
        ld      a,M_RE + M_TE + M_MOD2\r
        out0    (cntla1),a\r
@@ -89,21 +89,21 @@ buf.empty:
        ret     z\r
        or      0ffh\r
        ret\r
-       \r
+\r
 ser.in:\r
-       push    hl                      ;11     \r
+       push    hl                      ;11\r
        push    de                      ;11\r
-       ld      hl,ser1.inbuf-1         ; 9     hl = &rx.out_idx        \r
+       ld      hl,ser1.inbuf-1         ; 9     hl = &rx.out_idx\r
        ld      a,(hl)                  ; 6     a = rx.out_idx\r
        dec     hl                      ; 4     hl = &rx.in_idx\r
        jr      bg.w1\r
 bg.wait:\r
        halt\r
 bg.w1:\r
-       cp      (hl)                    ; 6     while (out_idx==in_idx) \r
+       cp      (hl)                    ; 6     while (out_idx==in_idx)\r
        jr      z,bg.wait               ; 6 (/8)        ;\r
 \r
-       ld      e,a                     ; 4     \r
+       ld      e,a                     ; 4\r
        ld      d,0                     ; 6\r
        inc     de\r
        inc     de\r
@@ -111,20 +111,20 @@ bg.w1:
        ex      de,hl                   ; 3\r
        add     hl,de                   ;10\r
        ld      l,(hl)                  ; 6\r
-       ex      de,hl                   ; 3     \r
+       ex      de,hl                   ; 3\r
 \r
        inc     a                       ; 4\r
        dec     hl                      ; 4\r
-       and     (hl)                    ; 6     \r
+       and     (hl)                    ; 6\r
        inc     hl                      ; 4\r
        inc     hl                      ; 4\r
        ld      (hl),a                  ; 7\r
-       \r
+\r
        ld      a,e                     ; 4\r
        pop     de                      ; 9\r
        pop     hl                      ; 9\r
        ret                             ; 9\r
-                                       ;   153 \r
+                                       ;   153\r
 \r
 ser.ost:\r
        push    ix\r
@@ -191,7 +191,7 @@ rxtxisv:
        in0     d,(rdr1)                ;todo: break detection\r
        bit     FE,a                    ;framing error?\r
        jr      nz,??ri_1\r
-       \r
+\r
        push    ix\r
        ld      ix,ser1.inbuf           ;\r
        ld      hl,ser1.inbuf           ;\r
@@ -233,7 +233,7 @@ txisv:
 ??ti_1:\r
        ld      l,(hl)\r
        out0    (tdr1),l                ;071b\r
-       \r
+\r
        ld      a,(ix+o.out_idx)        ;\r
        inc     a\r
        and     (ix+o.mask)\r
@@ -254,5 +254,3 @@ rxtx_src_e:
 \r
 \r
        end\r
-\r
-\r

diff --git a/z180/chario.180 b/z180/chario.180
index 8313658571b1711a841124b19ee6d6b1a13a8642..4d37b89a2310afe888d7604e932bbd94bdcdb226 100644 (file)
--- a/z180/chario.180
+++ b/z180/chario.180
@@ -2,7 +2,7 @@
        .z80\r
 \r
 \r
-;      CP/M 3  compatible character i/o \r
+;      CP/M 3  compatible character i/o\r
 \r
        public  ?cinit,?ci,?co,?cist,?cost\r
        public  @ctbl\r
@@ -10,7 +10,7 @@
        extrn   ff.init,ff.i.st,ff.in,ff.o.st,ff.out\r
        extrn   as0init,as0ista,as0inp,as0osta,as0out\r
        extrn   as1init,as1ista,as1inp,as1osta,as1out\r
-       \r
+\r
        include config.inc\r
        include z180reg.inc\r
        include modebaud.inc    ; define mode bits and baud eqautes\r
@@ -98,7 +98,7 @@ null$status:
        db      mb$in$out\r
        db      baud$none\r
 \r
-       db      'ASCI1 '        ; device 1\r
+       db      'ASCI0 '        ; device 1\r
        db      mb$in$out+mb$serial+mb$soft$baud\r
 ser0$baud:\r
        db      baud$19200\r
@@ -111,4 +111,3 @@ ser1$baud:
        db      0               ; table terminator\r
 \r
        end\r
-\r

diff --git a/z180/conbuf-a.180 b/z180/conbuf-a.180
index 096bbf932125430a9946b096ddb8e3e34cae3ddc..e86b8b25ea26c374a0ed3bfbca515c2399dc4303 100644 (file)
--- a/z180/conbuf-a.180
+++ b/z180/conbuf-a.180
@@ -1,6 +1,6 @@
        page    255\r
        .z80\r
-       \r
+\r
 ;\r
 ; FIFO channels for communication with avr\r
 ;\r
@@ -17,10 +17,10 @@
 ;--------------------------------------------------------------\r
 \r
        dseg\r
-       \r
 \r
-       mkbuf   co.fifo,co.fifo_len\r
-       mkbuf   ci.fifo,ci.fifo_len\r
+\r
+       mkbuf   co.fifo_id, co.fifo, co.fifo_len\r
+       mkbuf   ci.fifo_id, ci.fifo, ci.fifo_len\r
 \r
 \r
 ;--------------------------------------------------------------\r
@@ -50,7 +50,7 @@ buf.empty:
        ret     z\r
        or      0ffh\r
        ret\r
-       \r
+\r
 \r
 ff.in:\r
        push    ix\r
@@ -71,12 +71,12 @@ bg.wait:
        inc     h\r
 bg.nc:\r
        ld      l,(hl)\r
-       \r
+\r
        ld      a,(ix+o.out_idx)        ;\r
        inc     a\r
        and     (ix+o.mask)\r
        ld      (ix+o.out_idx),a\r
-       \r
+\r
        ld      a,l\r
        pop     hl\r
        pop     ix\r
@@ -122,7 +122,7 @@ bp.wait:
        cp      (ix+o.out_idx)          ;19\r
        jr      z,bp.wait               ;12/7\r
        ld      (ix+o.in_idx),a         ;19\r
-       \r
+\r
        out     (AVRINT6),a             ;11\r
        ld      a,b                     ;4\r
        pop     bc                      ;10\r
@@ -163,4 +163,3 @@ bp.wait:
        endif\r
 \r
        end\r
-\r

diff --git a/z180/config.inc b/z180/config.inc
index 33152de2bd8beb1d214264eb76080d5c643629d3..0c945ae747b21a35bc812ce5e055487da9ec0d44 100644 (file)
--- a/z180/config.inc
+++ b/z180/config.inc
@@ -47,8 +47,8 @@ CA    equ     10h - CSK               ;common area start
 BA     equ     0                       ;banked area start\r
 \r
 SYS$CBR                equ     0\r
-SYS$CBAR       equ     CA<<4 + CA      ;CBAR in system mode\r
-USR$CBAR       equ     CA<<4 + BA      ;CBAR in user mode (CP/M)\r
+SYS$CBAR       equ     CA*16 + CA      ;CBAR in system mode\r
+USR$CBAR       equ     CA*16 + BA      ;CBAR in user mode (CP/M)\r
 \r
 \r
 BANKS          equ     18              ;max nr. of banks\r
@@ -57,6 +57,7 @@ BANKS         equ     18              ;max nr. of banks
 \r
 CREFSH         equ     0               ;Refresh rate register (disable refresh)\r
 CWAITIO                equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States\r
+PHI_X2         equ     0               ;set to M_X2CM to enable the clock doubler\r
 \r
     endif              ;CPU_Z180\r
     if CPU_Z80\r
@@ -108,14 +109,20 @@ CWAITROM  equ     2 shl MWI0
 DRSTNUM        equ     30h             ;DDTZ Restart vector (breakpoints)\r
 \r
 \r
-mrx.fifo_len   equ     256\r
-mtx.fifo_len   equ     256\r
+mtx.fifo_len   equ     32      ;Message transfer fifos\r
+mtx.fifo_id            equ     0       ;    This *must* have #0\r
+mrx.fifo_len   equ     32\r
+mrx.fifo_id            equ     1\r
 \r
-ci.fifo_len    equ     128\r
-co.fifo_len    equ     256\r
+ci.fifo_len    equ     32              ;AVRCON Character I/O via AVR\r
+ci.fifo_id     equ     2\r
+co.fifo_len    equ     32\r
+co.fifo_id     equ     3\r
 \r
-s1.rx_len      equ     256             ;Serial 1 (ASCI1) buffers\r
-s1.tx_len      equ     256             ;\r
+s1.rx_len      equ     128             ;Serial 1 (ASCI1) buffers\r
+s1.rx_id       equ     4               ;\r
+s1.tx_len      equ     128             ;\r
+s1.tx_id       equ     5               ;\r
 \r
 AVRINT5                equ     4Fh\r
 AVRINT6                equ     5Fh\r
@@ -136,24 +143,26 @@ iv2tab            equ     ivtab + 2*9
 \r
 ;-----------------------------------------------------\r
 \r
-\r
+o.id           equ     -4\r
 o.mask         equ     -3\r
 o.in_idx       equ     -2\r
 o.out_idx      equ     -1\r
 \r
        .lall\r
 \r
-mkbuf  macro   name,size\r
-  if ((size & (size-1)) ne 0) or (size gt 256)\r
+mkbuf  macro   id,name,size\r
+  if ((size AND (size-1)) NE 0) OR (size GT 256)\r
     .printx Error: buffer ^size must be power of 2 and in range 0..256!\r
     name&.mask equ ;wrong size error\r
   else\r
+    db id\r
     ds 3\r
     name:: ds size\r
     name&.mask equ low (size-1)\r
     if size ne 0\r
       name&.end equ $-1\r
       name&.len equ size\r
+      name&.id equ id\r
     endif\r
   endif\r
 endm\r

diff --git a/z180/fifoio.180 b/z180/fifoio.180
index dd99c53500a1876ccc62f21d6111115d57f4a20d..cbcece9152635a5d309ac41dda8fff3783861c5f 100644 (file)
--- a/z180/fifoio.180
+++ b/z180/fifoio.180
@@ -1,6 +1,6 @@
        page    255\r
        .z80\r
-       \r
+\r
 ;\r
 ; FIFO channels for communication with stm32\r
 ;\r
@@ -15,10 +15,10 @@
 ;--------------------------------------------------------------\r
 \r
        dseg\r
-       \r
 \r
-       mkbuf   rx.buf,rx.buf_len\r
-       mkbuf   tx.buf,tx.buf_len\r
+\r
+       mkbuf   ci.fifo_id, rx.buf,rx.buf_len\r
+       mkbuf   co.fifo_id, tx.buf,tx.buf_len\r
 \r
 \r
 ;--------------------------------------------------------------\r
@@ -48,7 +48,7 @@ buf.empty:
        ret     z\r
        or      0ffh\r
        ret\r
-       \r
+\r
 \r
 f.in:\r
        push    ix\r
@@ -69,12 +69,12 @@ bg.wait:
        inc     h\r
 bg.nc:\r
        ld      l,(hl)\r
-       \r
+\r
        ld      a,(ix+o.out_idx)        ;\r
        inc     a\r
        and     (ix+o.mask)\r
        ld      (ix+o.out_idx),a\r
-       \r
+\r
        ld      a,l\r
        pop     hl\r
        pop     ix\r
@@ -118,7 +118,7 @@ bp.wait:
        jr      z,bp.wait\r
        ld      (hl),b\r
        ld      (ix+o.in_idx),a\r
-       \r
+\r
        ld      a,b\r
        pop     bc\r
        pop     hl\r
@@ -126,4 +126,3 @@ bp.wait:
        ret\r
 \r
        end\r
-\r

diff --git a/z180/msgbuf-a.180 b/z180/msgbuf-a.180
index ddb2d93888cc869416d99658089022852d99cb21..ff2a657640f5af3984ae8a8ea01a58e5730d625c 100644 (file)
--- a/z180/msgbuf-a.180
+++ b/z180/msgbuf-a.180
@@ -17,8 +17,8 @@
 \r
        dseg\r
 \r
-       mkbuf   mrx.fifo,mrx.fifo_len\r
-       mkbuf   mtx.fifo,mtx.fifo_len\r
+       mkbuf   mtx.fifo_id, mtx.fifo, mtx.fifo_len\r
+       mkbuf   mrx.fifo_id, mrx.fifo, mrx.fifo_len\r
 \r
 ;--------------------------------------------------------------\r
 \r

diff --git a/z180/msgfifo.180 b/z180/msgfifo.180
index 582c219aebf974aae8b9f964b94db433019dca79..cf1ae2a4eb8b53d98c63398a11a845bc3b802775 100644 (file)
--- a/z180/msgfifo.180
+++ b/z180/msgfifo.180
@@ -1,11 +1,11 @@
        page    255\r
        .z80\r
-       \r
+\r
        global  msg_rx_fifo,msg_tx_fifo\r
 \r
        global  msginit,msgi.st,msg.in,msgo.st,msg.out\r
        global  msg.sout,msg.co\r
-       \r
+\r
        extrn   buf.init\r
 \r
        include config.inc\r
@@ -15,8 +15,8 @@
 \r
        dseg\r
 \r
-       mkbuf   msg_rx_fifo,msg_rx_fifo_len\r
-       mkbuf   msg_tx_fifo,msg_tx_fifo_len\r
+       mkbuf   mtx.fifo_id, msg_tx_fifo, msg_tx_fifo_len\r
+       mkbuf   mrx.fifo_id, msg_rx_fifo, msg_rx_fifo_len\r
 \r
 \r
 \r
@@ -27,7 +27,7 @@
 ;\r
 ; Init buffer\r
 ;\r
-       \r
+\r
 msginit:\r
        ld      ix,msg_rx_fifo\r
        ld      a,msg_rx_fifo.mask\r
@@ -49,7 +49,7 @@ buf.empty:
        ret     z\r
        or      0ffh\r
        ret\r
-       \r
+\r
 ;--------------------------------------------------------------\r
 \r
 msg.in:\r
@@ -71,12 +71,12 @@ bg.wait:
        inc     h\r
 bg.nc:\r
        ld      l,(hl)\r
-       \r
+\r
        ld      a,(ix+o.out_idx)        ;\r
        inc     a\r
        and     (ix+o.mask)\r
        ld      (ix+o.out_idx),a\r
-       \r
+\r
        ld      a,l\r
        pop     hl\r
        pop     ix\r
@@ -122,7 +122,7 @@ bp.wait:
        jr      z,bp.wait\r
        ld      (hl),b\r
        ld      (ix+o.in_idx),a\r
-       \r
+\r
        ld      a,b\r
        out0    (AVRINT5),a\r
        pop     bc\r
@@ -152,7 +152,7 @@ bp.wait:
        ld      a,b\r
        out     (PMSG),a\r
        ld      (ix+o.in_idx),c\r
-       \r
+\r
        pop     bc\r
        pop     ix\r
        ret\r
@@ -171,7 +171,7 @@ msg.sout:
        ld      b,(hl)                  ;\r
        inc     hl\r
        ex      de,hl\r
-       \r
+\r
 ms.ol:\r
        push    ix\r
        pop     hl\r
@@ -242,8 +242,8 @@ msg.co:
        pop     hl\r
        pop     af\r
        ret\r
-       \r
-       \r
+\r
+\r
 buf:\r
        db      buf_end - $ - 1         ;output string length\r
        db      081h                    ; message start token\r
@@ -257,4 +257,3 @@ buf_end:
 ;----------------------------------------------------------------------\r
 \r
        end\r
-\r