Simplify Console I/O. Switch back to IOBYTE.

7 files changed, 781 insertions, 60 deletions

diff --git a/z180/Makefile b/z180/Makefile
index 11f9093..c6727b9 100644
--- a/z180/Makefile
+++ b/z180/Makefile
@@ -1,7 +1,9 @@
 
 
 SRC :=  init.180 ddtz.180
-SRC += fifoio.180 msgbuf.180 asci1-i.180 console.180
+SRC += console.180
+SRC += msgbuf-a.180 conbuf-a.180
+SRC += asci1-p.180
 SRC += romend.180
 
 INC := config.inc z180reg.inc z180.lib
diff --git a/z180/Tupfile b/z180/Tupfile
index 23855f8..50ede98 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -4,10 +4,10 @@ PROG	= hdrom
 
 SRC 	= init.180
 SRC	+= ddtz.180
-#SRC	+= fifoio.180 msgbuf.180 asci-p.180 console.180
-SRC	+= msgbuf-a.180 conbuf-a.180 asci-p.180 bioscio.180 chario.180
-# serial (asci1) console only:
-#SRC	+= asci1-i.180 console.180
+SRC	+= msgbuf-a.180 conbuf-a.180
+#SRC	+= bioscio.180 chario.180
+SRC	+= console.180
+SRC	+= asci-p.180
 SRC	+= romend.180
 
 
diff --git a/z180/conbuf-a.180 b/z180/conbuf-a.180
index 8534f73..096bbf9 100644
--- a/z180/conbuf-a.180
+++ b/z180/conbuf-a.180
@@ -9,7 +9,9 @@
 	extrn	buf.init

 

 	include config.inc

+	if CPU_Z180

 	include	z180reg.inc

+	endif

 

 

 ;--------------------------------------------------------------

@@ -96,36 +98,69 @@ buf.full:
 	ret

 

 

+	if 1

 ff.out:

-	push	ix

-	ld	ix,co.fifo		;

+	push	ix			;15

+	ld	ix,co.fifo		;14

 

 buf.put:

-	push	hl			;

-	push	bc

-	push	ix

-	pop	hl

-	ld	a,c

-	ld	c,(ix+o.in_idx)		;

-	ld	b,0

-	add	hl,bc

-	ld	b,a

-

-	ld	a,c			;

-	inc	a

-	and	(ix+o.mask)

+	push	hl			;11

+	push	bc			;11

+	push	ix			;15

+	pop	hl			;10

+	ld	a,c			;4

+	ld	c,(ix+o.in_idx)		;19

+	ld	b,0			;7

+	add	hl,bc			;11

+	ld	(hl),a			;7

+	ld	b,a			;4

+

+	ld	a,c			;4

+	inc	a			;4

+	and	(ix+o.mask)		;19

 bp.wait:

-	cp	(ix+o.out_idx)		;

-	jr	z,bp.wait

-	ld	(hl),b

-	ld	(ix+o.in_idx),a

+	cp	(ix+o.out_idx)		;19

+	jr	z,bp.wait		;12/7

+	ld	(ix+o.in_idx),a		;19

 	

-	out	(AVRINT6),a

-	ld	a,b

-	pop	bc

-	pop	hl

-	pop	ix

-	ret

+	out	(AVRINT6),a		;11

+	ld	a,b			;4

+	pop	bc			;10

+	pop	hl			;10

+	pop	ix			;14

+	ret				;10

+

+	else

+

+ff.out:

+	push	ix			;15

+	ld	ix,co.fifo		;14

+

+buf.put:

+	push	hl			;11

+	push	ix			;15

+	pop	hl			;10

+	ld	a,(ix+o.in_idx)		;19

+	add	a,l			;4

+	ld	l,a			;4

+	jr	nc,bp.1			;12/7

+	inc	l			;4

+	ld	(hl),c			;7

+	ld	a,(ix+o.in_idx)		;19

+	inc	a			;4

+	and	(ix+o.mask)		;19

+bp.wait:

+	cp	(ix+o.out_idx)		;19

+	jr	z,bp.wait		;12/7

+	ld	(ix+o.in_idx),a		;19

+

+	out	(AVRINT6),a		;11

+	ld	a,c			;4

+	pop	hl			;10

+	pop	ix			;14

+	ret				;10		|

+

+	endif

 

 	end

 

diff --git a/z180/console.180 b/z180/console.180
index d4f4130..1241d5a 100644
--- a/z180/console.180
+++ b/z180/console.180
@@ -2,47 +2,136 @@
 	.z80

 	

 

-	global	$coninit

-	global	$cists,$ci

-	global	$co

+; iobyte:

+;		0 = console on AVR-System

+;		1 = console on SIO/ASCI

 

 

-	extrn	ser.init,ser.ist,ser.in,ser.ost,ser.out

+	extrn	iobyte

 	extrn	ff.init,ff.i.st,ff.in

 	extrn	ff.o.st,ff.out

+    if CPU_Z180

+	extrn	as0init,as0ista,as0inp,as0osta,as0out

+	extrn	as1init,as1ista,as1inp,as1osta,as1out

+    else

+	extrn	ser.init,ser.ist,ser.in,ser.ost,ser.out

+    endif

 	

+	public	charini

+	public	?const,?conin

+	public	?conos,?cono

 

 	include config.inc

+    if CPU_Z180

 	include	z180reg.inc

+    endif

 

 	cseg

-;

-;

 

-$coninit:

+    if CPU_Z180

+charini:

+	call	ff.init

+	call	as0init

+	jp	as1init

+

+?const:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.i.st

+	dec	a

+	jp	z,as0ista

+	dec	a

+	jp	z,as1ista

+	jr	nullstatus

+

+?conin:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.in

+	dec	a

+	jp	z,as0inp

+	dec	a

+	jp	z,as1inp

+	jr	nullinput

+

+?conos:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.o.st

+	dec	a

+	jp	z,as0osta

+	dec	a

+	jp	z,as1osta

+	jr	rettrue

+

+?cono:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.out

+	dec	a

+	jp	z,as0out

+	dec	a

+	jp	z,as1out

+	jr	nulloutput

+

+    else

+

+charini:

 	call	ff.init

+	ld	c,0

 	call	ser.init

+	ld	c,1

+	jp	ser.init

+

+?const:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.i.st

+	dec	a

+	ld	b,a

+	jp	ser.ist

+

+?conin:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.in

+	dec	a

+	ld	b,a

+	jp	ser.in

+

+?conos:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.o.st

+	dec	a

+	ld	b,a

+	jp	ser.ost

+

+?cono:

+	ld	a,(iobyte)

+	and	03h

+	jp	z,ff.out

+	dec	a

+	ld	b,a

+	jp	ser.out

+    endif

+

+

+nullinput:

+	ld	a,1Ah

 	ret

-	

-$cists:

-	call	ff.i.st

-	ret	nz

-	call	ser.ist

+

+nulloutput:

+	ld	a,c

 	ret

-	

-$ci:

-	call	ff.i.st

-	jp	nz,ff.in

-	call	ser.ist

-	jp	nz,ser.in

-	jr	$ci

-	

-;$costs:

-;	jp	f.o.st

-	

-$co:

-	call	ff.out

-	jp	ser.out

-	

+

+rettrue:

+	or	0FFh

+	ret

+

+nullstatus:

+	xor	a

+	ret

+

 	end

 

diff --git a/z180/init-80.180 b/z180/init-80.180
new file mode 100644
index 0000000..8b71993
--- /dev/null
+++ b/z180/init-80.180
@@ -0,0 +1,591 @@
+	page	255

+	.z80

+

+	extrn ddtz,bpent

+	extrn $stack

+	extrn charini,?const,?conin

+	extrn ?cono,?conos

+

+	extrn romend

+

+	global	iobyte

+	global	isv_sw

+

+	include config.inc

+

+

+

+

+;----------------------------------------------------------------------

+

+	cseg

+romstart equ	$

+

+	org	romstart+0

+	jp	start

+

+iobyte:	db	0

+

+; restart vectors

+

+rsti	defl	1

+	rept	7

+

+	org	8*rsti + romstart

+	 jp bpent

+rsti	 defl rsti+1

+	endm

+

+;----------------------------------------------------------------------

+	

+	org	romstart+40h

+

+	dw	0

+	db	0

+

+	cseg

+

+	if ROMSYS

+$crom:	 defb c$rom		;

+	else

+	 db	0		;

+	endif

+

+

+hwini0:

+	db	0		;count

+;	db	rcr,CREFSH	;configure DRAM refresh

+;	db	dcntl,INIWAITS	;wait states

+;	db	cbar,SYS$CBAR

+

+

+;----------------------------------------------------------------------

+

+	org	romstart+50h

+

+start:

+	jp	cstart

+	jp	wstart

+	jp	?const

+	jp	?conin

+	jp	?cono

+	jp	?conos

+	jp	charini

+

+cstart:

+	di

+

+	xor	a

+	ld	(@cbnk),a

+

+; search warm start mark

+

+	ld ix,mark_55AA		; top of common area

+	ld a,0aah		;

+	cp (ix+000h)		;

+	jr nz,kstart		;

+	cp (ix+002h)		;

+	jr nz,kstart		;

+	cpl			;

+	cp (ix+001h)		;

+	jr nz,kstart		;

+	cp (ix+003h)		;

+	jr nz,kstart		;

+	ld sp,$stack		; mark found, check

+;	call checkcrc_alv	;

+	jp z,wstart		; check ok,

+

+;

+; ram not ok, initialize    --  kstart --

+

+kstart:

+	ld	sp,$stack	;01e1

+

+; Clear RAM 

+

+; Init bank manager

+

+;----------------------------------------------------------------------

+;

+

+	ld	hl,055AAh	;set warm start mark

+	ld	(mark_55AA),hl	;

+	ld	(mark_55AA+2),hl;

+

+;

+;       --  wstart  --

+;

+wstart:

+	call	sysram_init	;027f

+	call	ivtab_init

+

+	call	charini

+	call	bufferinit

+

+	ld	c,0

+	call	selbnk

+

+

+	im 2			;?030e

+	ei			;0282

+

+	call ?const		;0284

+	call ?const		;0287

+	or a			;028a

+	call nz,?conin		;028d

+

+;;;	ld a,(banktab)		;

+;;;	ld e,a			;

+	jp ddtz			;0290

+

+

+;----------------------------------------------------------------------

+;

+

+;TODO: Make a ringbuffer module.

+

+	global	buf.init

+

+buf.init:

+	ld	(ix+o.in_idx),0

+	ld	(ix+o.out_idx),0

+	ld	(ix+o.mask),a

+	ret

+

+;----------------------------------------------------------------------

+

+

+	extrn	msginit,msg.sout

+	extrn	mtx.fifo,mrx.fifo

+	extrn	co.fifo,ci.fifo

+

+

+bufferinit:

+	call	 msginit

+

+	ld	hl,buffers

+	ld	b,buftablen

+bfi_1:

+	ld	a,(hl)

+	inc	hl

+	ld	(bufdat+0),a

+	ld	e,(hl)

+	inc	hl

+	ld	d,(hl)

+	inc	hl

+	ex	de,hl

+

+	or	a

+	jr	nz,bfi_2

+

+	ld	a,(@cbnk)

+	call	bnk2phys

+

+	ld	(40h+0),hl

+	ld	(40h+2),a

+	out	(AVRINT5),a

+	jr	bfi_3

+bfi_2:

+

+	ld	a,(@cbnk)

+	call	bnk2phys

+

+	ld	(bufdat+1),hl

+	ld	(bufdat+3),a

+	ld	hl,inimsg

+	call	msg.sout

+bfi_3:

+	ex	de,hl

+	djnz	bfi_1

+	ret

+

+

+buffers:

+	db	0

+	dw	mtx.fifo

+	db	1

+	dw	mrx.fifo

+	db	2

+	dw	co.fifo

+	db	3

+	dw	ci.fifo

+buftablen equ	($ - buffers)/3

+

+inimsg:

+	db	inimsg_e - $ -1

+	db	0AEh

+	db	inimsg_e - $ -1

+	db	0

+bufdat:

+	db	0

+	dw	0

+	db	0

+inimsg_e:

+

+

+;

+;----------------------------------------------------------------------

+;

+

+bnk2phys:

+	sla	h

+	jr	nc,b2p_1		;A15=1 --> common

+	ld	a,3

+b2p_1:

+	srl	a

+	rr	h

+	ret

+

+;

+;----------------------------------------------------------------------

+;

+

+sysram_init:

+	ld hl,sysramw

+	ld de,topcodsys

+	ld bc,sysrame-sysramw

+	ldir

+

+	ret

+

+;----------------------------------------------------------------------

+

+ivtab_init:

+	ld	hl,ivtab	;

+	ld	a,h		;

+	ld	i,a		;

+;	out0	(il),l		;

+

+; Let all vectors point to spurious int routines.

+

+	ld	d,high sp.int0

+	ld	a,low  sp.int0

+	ld	b,9

+ivt_i1:

+	ld	(hl),a

+	inc	l

+	ld	(hl),d

+	inc	l

+	add	a,sp.int.len

+	djnz	ivt_i1

+	ret

+

+;----------------------------------------------------------------------

+;

+

+	global io.ini

+	

+io.ini:

+	push	bc

+

+	if CPU_Z180

+

+	ld	b,0		;high byte port adress

+	ld	a,(hl)		;count

+	inc	hl

+	or	a

+	jr	z,ioi_e

+ioi_1:

+	ld	c,(hl)		;port address

+	inc	hl

+	outi

+	inc	b		;outi decrements b

+	dec	a

+	jr	nz,ioi_1

+

+	else

+	jr	ioi_nxt

+ioi_l:

+	ld	c,(hl)		;port address

+	inc	hl

+	otir

+ioi_nxt:

+	ld	b,(hl)		;count

+	inc	hl

+	inc	b

+	djnz	ioi_l

+	endif

+ioi_e:	

+	pop	bc

+	ret

+

+	if CPU_Z180

+io.ini.m:

+	push	bc

+	ld	b,(hl)

+	inc	hl

+	ld	c,(hl)

+	inc	hl

+	otimr

+	pop	bc

+	ret

+	endif

+

+io.ini.l:

+;

+

+

+;----------------------------------------------------------------------

+;

+;return:

+; hl = hl + a

+; Flags undefined

+;

+

+add_hl_a:

+	add a,l

+	ld l,a

+	ret nc

+	inc h

+	ret

+

+; ---------------------------------------------------------

+

+sysramw:

+

+	.phase isvsw_loc

+topcodsys:

+

+; Trampoline for interrupt routines in banked ram.

+; Switch stack pointer to "system" stack in top ram

+

+; todo: z80 bank switch

+

+isv_sw:				;

+	ex (sp),hl		; save hl, return adr in hl

+	push de			;

+	push af			;

+	ex de,hl		;

+	ld hl,0			;

+	add hl,sp		;

+	ld a,h			;

+	cp 0f8h			;

+	jr nc,isw_1		;

+	ld sp,$stack		;

+isw_1:

+	push hl			;

+				; save current bank

+;	in0 h,(cbar)		;

+	push hl			;

+				; switch to system bank

+;	ld a,SYS$CBAR		;

+;	out0 (cbar),a		; 

+	ex de,hl		;

+	ld e,(hl)		;

+	inc hl			;

+	ld d,(hl)		;

+	ex de,hl		;

+	push bc			;

+	call jphl		;

+

+	pop bc			;

+	pop hl			; restore bank

+;	out0 (cbar),h		;

+	pop hl			;

+	ld sp,hl		;

+	pop af			;

+	pop de			;

+	pop hl			;

+	ei			;

+	ret			;

+jphl:

+	jp (hl)			;

+

+; ---------------------------------------------------------

+

+sp.int0:

+	ld	a,0d0h

+	jr	sp.i.1

+sp.int.len equ	$-sp.int0

+	ld	a,0d1h

+	jr	sp.i.1

+	ld	a,0d2h

+	jr	sp.i.1

+	ld	a,0d3h

+	jr	sp.i.1

+	ld	a,0d4h

+	jr	sp.i.1

+	ld	a,0d5h

+	jr	sp.i.1

+	ld	a,0d6h

+	jr	sp.i.1

+	ld	a,0d7h

+	jr	sp.i.1

+	ld	a,0d8h

+sp.i.1:

+;	out	(80h),a

+	halt

+

+; ---------------------------------------------------------

+

+; Get IFF2

+; This routine may not be loaded in page zero

+;

+; return Carry clear, if INTs are enabled.

+;

+	global getiff

+getiff:

+	xor	a		;clear accu and carry

+	push	af		;stack bottom := 00xxh

+	pop	af

+	ld	a,i		;P flag := IFF2

+	ret	pe		;exit carry clear, if enabled

+	dec	sp

+	dec	sp		;has stack bottom been overwritten?

+	pop	af

+	and	a		;if not 00xxh, INTs were

+	ret	nz		;actually enabled

+	scf			;Otherwise, they really are disabled

+	ret

+

+;----------------------------------------------------------------------

+

+	global	selbnk

+

+; a: bank (0..2)

+

+selbnk:

+	push	bc

+	ld	c,a

+	call	getiff

+	push	af

+

+	ld	a,c

+	di

+	ld	(@cbnk),a

+	ld	a,5

+	out	(SIOAC),a

+	ld	a,(mm_sio0)

+	rla

+	srl	c

+	rra

+	out	(SIOAC),a

+	ld	(mm_sio0),a

+

+	ld	a,5

+	out	(SIOBC),a

+	ld	a,(mm_sio1)

+	rla

+	srl	c

+	rra

+	out	(SIOBC),a

+	ld	(mm_sio1),a

+	pop	af

+	pop	bc

+	ret	c			;INTs were disabled

+	ei

+	ret

+

+;----------------------------------------------------------------------

+

+; c: bank (0..2)

+

+	if 0

+

+selbnk:

+	ld	a,(@cbnk)

+	xor	c

+	and	3

+	ret	z		;no change

+

+	call	getiff

+	push	af

+	ld	a,c

+	di

+	ld	(@cbnk),a

+	ld	a,5

+	out	(SIOAC),a

+	ld	a,(mm_sio0)

+	rla

+	srl	c

+	rra

+	out	(SIOAC),a

+	ld	(mm_sio0),a

+

+	ld	a,5

+	out	(SIOBC),a

+	ld	a,(mm_sio1)

+	rla

+	srl	c

+	rra

+	out	(SIOBC),a

+	ld	(mm_sio1),a

+	pop	af

+	ret	nc			;INTs were disabled

+	ei

+	ret

+

+	endif

+

+;----------------------------------------------------------------------

+

+	if 0

+	ex	af,af'

+	push	af

+	ex	af,af'

+

+	rra

+	jr	nc,stbk1

+	ex	af,af'

+	ld	a,5

+	out	(SIOAC),a

+	ld	a,(mm_sio0)

+	rla

+	srl	c

+	rra

+	out	(SIOAC),a

+	ld	(mm_sio1),a

+	ex	af,af'

+

+stbk1:

+	rra

+	jr	nc,stbk2

+	ex	af,af'

+	ld	a,5

+	out	(SIOBC),a

+	ld	a,(mm_sio1)

+	rla

+	srl	c

+	rra

+	out	(SIOBC),a

+	ld	(mm_sio1),a

+	ex	af,af'

+

+stbk2:

+	endif

+

+	global	@cbnk

+	global	mm_sio0, mm_sio1

+

+@cbnk:	db	0		; current bank (0..2)

+mm_sio0:

+	ds	1

+mm_sio1:

+	ds	1

+

+;----------------------------------------------------------------------

+

+curph	defl	$

+	.dephase

+sysrame:

+	.phase curph

+tim_ms:	db	0

+tim_s:	dw	0

+	.dephase

+

+;-----------------------------------------------------

+

+	cseg

+

+	;.phase	0ffc0h

+;ivtab	equ	0ffc0h		; 0ffc0h	;int vector table

+	;.dephase

+

+	;.phase	0fffch

+mark_55AA equ 0fffch

+	;ds	4		; 0fffch

+	;.dephase

+

+

+	end

+

diff --git a/z180/init.180 b/z180/init.180
index 39b03fc..73a77bb 100644
--- a/z180/init.180
+++ b/z180/init.180
@@ -8,6 +8,7 @@
 	extrn romend

 

 

+	global	iobyte

 	global	isv_sw

 

 	include config.inc

@@ -27,7 +28,8 @@ romstart equ	$
 	org	romstart+0

 	jp start

 

-iobyte:	db	0

+iobyte:	db	2

+

 ; restart vectors

 

 rsti	defl	1

diff --git a/z180/msgbuf-a.180 b/z180/msgbuf-a.180
index 36e0871..1bdd826 100644
--- a/z180/msgbuf-a.180
+++ b/z180/msgbuf-a.180
@@ -9,7 +9,9 @@
 	extrn	buf.init

 

 	include config.inc

+	if CPU_Z180

 	include	z180reg.inc

+	endif

 

 ;--------------------------------------------------------------

 

@@ -122,7 +124,7 @@ bp.wait:
 	ld	(ix+o.in_idx),a

 	

 	ld	a,b

-	out0	(AVRINT5),a

+	out	(AVRINT5),a

 	pop	bc

 	pop	hl

 	pop	ix

@@ -165,7 +167,7 @@ ms.wait:
 	ld	(hl),a

 	ld	(ix+o.in_idx),c

 	djnz	ms.ol

-	out0	(AVRINT5),a

+	out	(AVRINT5),a

 	ex	de,hl

 	pop	de

 	pop	bc