Continue Integration

4 files changed, 394 insertions, 39 deletions

diff --git a/z180/Tupfile b/z180/Tupfile
index 3105c94..1becb04 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -38,7 +38,8 @@ grep -q '^ 0 Error(s) Detected' ${OUTPUT}; ERROR=$?;\
 rm -f ${OUTPUT}; exit ${ERROR} \
 |> %B.rel | %B.lst 
 
-!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) -D $(LN_DATA) %f |> | %O.map
+#!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) -D $(LN_DATA) %f |> | %O.map
+!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) %f |> | %O.map
 
 #ifndef DEBUG
 
diff --git a/z180/bioscio.180 b/z180/bioscio.180
index 5ec55c6..b0fd4da 100644
--- a/z180/bioscio.180
+++ b/z180/bioscio.180
@@ -65,7 +65,8 @@ c$init$loop:
 	dec	c

 	jp	p,c$init$loop

 

-	ld	hl,1000000000000000b	; assign console to HOST

+;	ld	hl,1000000000000000b	; assign console to HOST

+	ld	hl,0100000000000000b	; assign console to ASCI1

 	ld	(@civec),hl

 	ld	(@covec),hl

 	ld	hl,0000000000000000b	; assign auxiliary to nothing

diff --git a/z180/ddtz.180 b/z180/ddtz.180
index 5f8bf20..490b829 100644
--- a/z180/ddtz.180
+++ b/z180/ddtz.180
@@ -6130,7 +6130,8 @@ l28dbh:
 ;------------------------------------------

 

 vartab:

-	dseg

+;	dseg

+	cseg

 ddtram:				

 ;todo:

 ; The following 2 params are changeable by user.

diff --git a/z180/init.180 b/z180/init.180
index 9edeaf2..16ca852 100644
--- a/z180/init.180
+++ b/z180/init.180
@@ -4,6 +4,7 @@
 	extrn ddtz,bpent

 	extrn $stack

 	extrn charini,?const,?conin

+	extrn ?cono,?conos

 

 	extrn romend

 

@@ -11,32 +12,35 @@
 	global	isv_sw

 

 	include config.inc

-	include	z180reg.inc

-	include z180.lib

+	if CPU_Z180

+	 include	z180reg.inc

+	 include z180.lib

+	endif

 

-;CR	equ	0dh

 

 

 

 ;----------------------------------------------------------------------

 

 	cseg

+romstart equ	$

 

+	org	romstart+0

 	jp start

 

+iobyte:	db	0

 ; restart vectors

 

 rsti	defl	1

 	rept	7

-	 db 0, 0, 0, 0, 0

+	org	8*rsti + romstart

 	 jp bpent

 rsti	 defl rsti+1

 	endm

-	 db 0, 0, 0, 0, 0

 

 ;----------------------------------------------------------------------

 	

-	;org	40h

+	org	romstart+40h

 

 	dw	0

 	db	0

@@ -48,6 +52,36 @@ $crom:	 defb c$rom		;
 	 db	0		;

 	endif

 

+INIWAITS defl	CWAITIO

+	if	ROMSYS

+INIWAITS defl	INIWAITS+CWAITROM

+	endif

+

+hwini0:

+	if CPU_Z180

+

+	 db	3		;count

+	 db	rcr,CREFSH	;configure DRAM refresh

+	 db	dcntl,INIWAITS	;wait states

+	 db	cbar,SYS$CBAR

+	else

+	 db     0

+	endif

+

+;----------------------------------------------------------------------

+

+	org	romstart+50h

+start:

+	jp	cstart

+	jp	wstart

+	jp	?const

+	jp	?conin

+	jp	?cono

+	jp	?conos

+	jp	charini

+

+;----------------------------------------------------------------------

+

 dmclrt:				;clear ram per dma

 	db	dmct_e-dmclrt-2 ;

 	db	sar0l		;first port

@@ -59,22 +93,9 @@ nullbyte:
 	dw 	0-romend	;count (64k)

 dmct_e:

 

-INIWAITS defl	CWAITIO

-	if	ROMSYS

-INIWAITS defl	INIWAITS+CWAITROM

-	endif

-

-hwini0:

-	db	3		;count

-	db	rcr,CREFSH	;configure DRAM refresh

-	db	dcntl,INIWAITS	;wait states

-	db	cbar,SYS$CBAR

+cstart:

+	if CPU_Z180

 

-;----------------------------------------------------------------------

-

-start:

-	ld	(tmpstack),sp

-	ld	sp,tmpstack

 	push af

 	in0 a,(itc)		;Illegal opcode trap?

 	jp m,??st01

@@ -82,10 +103,10 @@ start:
 	jr z,??st02		;    yes, harware reset

 

 ??st01:

+; TODO: SYS$CBR

 	ld	a,(syscbr)

 	out0	(cbr),a

 	pop af			;restore registers

-	ld	sp,(tmpstack)	;

 	jp bpent		;

 

 ??st02:

@@ -99,9 +120,16 @@ start:
 	out0	(ccr),a

 ;	ld	a,M_X2CM	;X2 Clock Multiplier

 ;	out0	(cmr),a

+	else

+	di

+	xor	a

+	ld	(@cbnk),a

+	endif

 

 ; search warm start mark

 

+	if CPU_Z180

+

 	ld ix,mark_55AA		;00b8	; top of common area

 	ld a,SYS$CBAR		;

 	out0 (cbar),a		;

@@ -127,11 +155,28 @@ swsm_l:
 	ld sp,$stack		;00e0	mark found, check

 	call checkcrc_alv	;00e3

 	jp z,wstart		;00e6	check ok,

-

+	else

+	ld ix,mark_55AA		; top of common area

+	ld a,0aah		;

+	cp (ix+000h)		;

+	jr nz,kstart		;

+	cp (ix+002h)		;

+	jr nz,kstart		;

+	cpl			;

+	cp (ix+001h)		;

+	jr nz,kstart		;

+	cp (ix+003h)		;

+	jr nz,kstart		;

+	ld sp,$stack		; mark found, check

+	jp z,wstart		; check ok,

+	endif

 ;

 ; ram not ok, initialize    --  kstart --

 

 kstart:

+	if CPU_Z180

+	

+	if 0

 

 	ld	a,088h		;00e9	0000-7fff: common 0

 	out0	(cbar),a	;00eb   8000-ffff: common 1

@@ -168,6 +213,14 @@ kstart:
 	add	a,8

 	cp	078h		;	stop at 078000

 	jr	nz,??cp_0

+	

+	else

+	

+	ld	de,0ffffh

+	ld	a,070h

+	out0	(cbr),a

+	

+	endif

 

 ;

 ;  ram test found 1 or more error free blocks (32k)

@@ -194,10 +247,15 @@ alloc:
 	out0	(cbr),c		;01de

 	ld	a,c

 	ld	(syscbr),a

+	endif

 	ld	sp,$stack	;01e1

 

 ; Clear RAM using DMA0

 

+	if CPU_Z180

+

+	if 0

+	

 	ld	hl,dmclrt	;load DMA registers

 	call	io.ini.m

 	ld	a,0cbh		;01ef	dst +1, src fixed, burst

@@ -208,6 +266,8 @@ alloc:
 ??cl_1:

 	out0	(dstat),a	;01f9	clear (up to) 64k

 	djnz	??cl_1		;	end of RAM?

+	

+	endif

 

 ; Init bank manager

 

@@ -271,24 +331,29 @@ l024ah:
 	ld	c,l		;

 	or	a		;

 	call	z,sub_04b5h	;

+	endif

 

 	ld	hl,055AAh	;set warm start mark

 	ld	(mark_55AA),hl	;

 	ld	(mark_55AA+2),hl;

 

 ;

-; crc ok       --  wstart  --

+; (crc ok)      --  wstart  --

 ;

 wstart:

 	call	sysram_init	;027f

 	call	ivtab_init

-

-	call	prt0_init

+	if CPU_Z180

+	 call	prt0_init

+	endif

 

 	call	charini

-

 	call	bufferinit

 

+	iff CPU_Z180

+	 ld	a,0

+	 call	selbnk

+	endif

 

 

 	im 2			;?030e

@@ -299,15 +364,19 @@ wstart:
 	or a			;028a

 	call nz,?conin		;028d

 

-	ld a,(banktab)		;

-	ld e,a			;

+	if CPU_Z180

+	 ld a,(banktab)		;

+	 ld e,a			;

+	else

+; TODO:

+	endif

 	jp ddtz			;0290

 

 

-	ds	8

-tmpstack:

-	dw	2

+	if CPU_Z180

+; TODO: SYS$CBR

 syscbr:	db	1

+	endif

 

 ;

 ;----------------------------------------------------------------------

@@ -376,6 +445,7 @@ endif
 

 

 bufferinit:

+	if CPU_Z180

 	call	 msginit

 

 	ld	hl,buffers

@@ -392,15 +462,15 @@ bfi_1:
 

 	or	a

 	jr	nz,bfi_2

-	in0	a,cbr

-	call	log2phys

+;	in0	a,(cbr)

+	call	hw_log2phys

 	ld	(40h+0),hl

 	ld	(40h+2),a

 	out0	(AVRINT5),a

 	jr	bfi_3	

 bfi_2:

-	in0	a,cbr

-	call	log2phys

+;	in0	a,(cbr)

+	call	hw_log2phys

 	ld	(bufdat+1),hl

 	ld	(bufdat+3),a

 	ld	hl,inimsg

@@ -409,6 +479,45 @@ bfi_3:
 	pop	hl

 	djnz	bfi_1

 	ret

+	else

+	call	 msginit

+

+	ld	hl,buffers

+	ld	b,buftablen

+bfi_1:

+	ld	a,(hl)

+	inc	hl

+	ld	(bufdat+0),a

+	ld	e,(hl)

+	inc	hl

+	ld	d,(hl)

+	inc	hl

+	ex	de,hl

+

+	or	a

+	jr	nz,bfi_2

+

+	ld	a,(@cbnk)

+	call	bnk2phys

+

+	ld	(40h+0),hl

+	ld	(40h+2),a

+	out	(AVRINT5),a

+	jr	bfi_3

+bfi_2:

+

+	ld	a,(@cbnk)

+	call	bnk2phys

+

+	ld	(bufdat+1),hl

+	ld	(bufdat+3),a

+	ld	hl,inimsg

+	call	msg.sout

+bfi_3:

+	ex	de,hl

+	djnz	bfi_1

+	ret

+	endif

 

 buffers:

 	db	0

@@ -451,7 +560,9 @@ ivtab_init:
 	ld	hl,ivtab	;

 	ld	a,h		;

 	ld	i,a		;

+	if CPU_Z180

 	out0	(il),l		;

+	endif

 

 ; Let all vectors point to spurious int routines.

 

@@ -469,6 +580,7 @@ ivt_i1:
 

 ;----------------------------------------------------------------------

 

+	if CPU_Z180

 prt0_init:

 	ld	a,i

 	ld	h,a

@@ -490,6 +602,7 @@ prt0itab:
 	dw	PRT_TC10MS

 	db	M_TIE0+M_TDE0	;enable timer 0 interrupt and down count.

 prt0it_e:

+	endif

 

 

 ;

@@ -498,9 +611,13 @@ prt0it_e:
 

 io.ini:

 	push	bc

+	if CPU_Z180

+

 	ld	b,0		;high byte port adress

 	ld	a,(hl)		;count

 	inc	hl

+	or	a

+	jr	z,ioi_e

 ioi_1:

 	ld	c,(hl)		;port address

 	inc	hl

@@ -508,9 +625,24 @@ ioi_1:
 	inc	b		;outi decrements b

 	dec	a

 	jr	nz,ioi_1

+

+	else

+	jr	ioi_nxt

+ioi_l:

+	ld	c,(hl)		;port address

+	inc	hl

+	otir

+ioi_nxt:

+	ld	b,(hl)		;count

+	inc	hl

+	inc	b

+	djnz	ioi_l

+	endif

+ioi_e:	

 	pop	bc

 	ret

 

+	if CPU_Z180

 io.ini.m:

 	push	bc

 	ld	b,(hl)

@@ -520,13 +652,17 @@ io.ini.m:
 	otimr

 	pop	bc

 	ret

+	endif

 

 io.ini.l:

 ;

 

+;

 ;----------------------------------------------------------------------

 ;

 

+	if CPU_Z180

+

 ; compute crc

 ; hl: start adr

 ; bc: len

@@ -802,6 +938,61 @@ log2phys:
 	pop	bc		;

 	ret			;

 

+;--------------------------------------------------------------

+;

+; de: Log. Address

+; 

+;

+; OP: ahl = (bankbase<<12) + (d<<8) + e

+;

+;out ahl: Phys. (linear) Address

+

+

+hw_log2phys:

+	push	bc		;

+	in0	c,(cbar)

+	ld	a,d

+	or	00fh

+	cp	c

+	jr	c,hlp_1

+	in0	c,(cbr)

+	jr	hlp_e

+hlp_1:

+	ld	b,16

+	mlt	bc

+	ld	a,d

+	cp	c

+	ld	c,0

+	jr	c,hlp_e

+	in0	c,(bbr)

+hlp_e:	

+	ld	b,16		;

+	mlt	bc		;bc = a<<4

+	ld	l,d		;

+	ld	h,0		;

+	add	hl,bc		;bc + d == a<<4 + d

+	ld	a,h		;

+	ld	h,l		;

+	ld	l,e		;

+	pop	bc		;

+	ret			;

+

+	else

+

+;

+;----------------------------------------------------------------------

+;

+

+bnk2phys:

+	sla	h

+	jr	nc,b2p_1		;A15=1 --> common

+	ld	a,3

+b2p_1:

+	srl	a

+	rr	h

+	ret

+

+	endif

 

 ;--------------------------------------------------------------

 ;

@@ -868,6 +1059,7 @@ jphl:
 

 ; ---------------------------------------------------------

 

+	if CPU_Z180

 

 iprt0:

 	push	af

@@ -890,6 +1082,8 @@ iprt_1:
 	ei

 	ret

 

+	endif

+

 ; ---------------------------------------------------------

 

 sp.int0:

@@ -915,6 +1109,160 @@ sp.i.1:
 ;	out	(80h),a

 	halt

 

+; ---------------------------------------------------------

+

+	iff CPU_Z180

+

+; Get IFF2

+; This routine may not be loaded in page zero

+;

+; return Carry clear, if INTs are enabled.

+;

+	global getiff

+getiff:

+	xor	a		;clear accu and carry

+	push	af		;stack bottom := 00xxh

+	pop	af

+	ld	a,i		;P flag := IFF2

+	ret	pe		;exit carry clear, if enabled

+	dec	sp

+	dec	sp		;has stack bottom been overwritten?

+	pop	af

+	and	a		;if not 00xxh, INTs were

+	ret	nz		;actually enabled

+	scf			;Otherwise, they really are disabled

+	ret

+

+;----------------------------------------------------------------------

+

+	global	selbnk

+

+; a: bank (0..2)

+

+selbnk:

+	push	bc

+	ld	c,a

+	call	getiff

+	push	af

+

+	ld	a,c

+	di

+	ld	(@cbnk),a

+	ld	a,5

+	out	(SIOAC),a

+	ld	a,(mm_sio0)

+	rla

+	srl	c

+	rra

+	out	(SIOAC),a

+	ld	(mm_sio0),a

+

+	ld	a,5

+	out	(SIOBC),a

+	ld	a,(mm_sio1)

+	rla

+	srl	c

+	rra

+	out	(SIOBC),a

+	ld	(mm_sio1),a

+	pop	af

+	pop	bc

+	ret	c			;INTs were disabled

+	ei

+	ret

+

+;----------------------------------------------------------------------

+

+; c: bank (0..2)

+

+	if 0

+

+selbnk:

+	ld	a,(@cbnk)

+	xor	c

+	and	3

+	ret	z		;no change

+

+	call	getiff

+	push	af

+	ld	a,c

+	di

+	ld	(@cbnk),a

+	ld	a,5

+	out	(SIOAC),a

+	ld	a,(mm_sio0)

+	rla

+	srl	c

+	rra

+	out	(SIOAC),a

+	ld	(mm_sio0),a

+

+	ld	a,5

+	out	(SIOBC),a

+	ld	a,(mm_sio1)

+	rla

+	srl	c

+	rra

+	out	(SIOBC),a

+	ld	(mm_sio1),a

+	pop	af

+	ret	nc			;INTs were disabled

+	ei

+	ret

+

+	endif

+

+;----------------------------------------------------------------------

+

+	if 0

+	ex	af,af'

+	push	af

+	ex	af,af'

+

+	rra

+	jr	nc,stbk1

+	ex	af,af'

+	ld	a,5

+	out	(SIOAC),a

+	ld	a,(mm_sio0)

+	rla

+	srl	c

+	rra

+	out	(SIOAC),a

+	ld	(mm_sio1),a

+	ex	af,af'

+

+stbk1:

+	rra

+	jr	nc,stbk2

+	ex	af,af'

+	ld	a,5

+	out	(SIOBC),a

+	ld	a,(mm_sio1)

+	rla

+	srl	c

+	rra

+	out	(SIOBC),a

+	ld	(mm_sio1),a

+	ex	af,af'

+

+stbk2:

+	endif

+

+	global	@cbnk

+	global	mm_sio0, mm_sio1

+

+@cbnk:	db	0		; current bank (0..2)

+mm_sio0:

+	ds	1

+mm_sio1:

+	ds	1

+

+

+	endif

+

+;----------------------------------------------------------------------

+

 curph	defl	$

 	.dephase

 sysrame:

@@ -925,6 +1273,8 @@ tim_s:	dw	0
 

 ;-----------------------------------------------------

 

+	if CPU_Z180

+

 	dseg

 

 	ds	1

@@ -941,6 +1291,8 @@ crc_len	equ	$-banktabsys
 crc_memalv:

 	ds	2	;

 

+	endif

+

 	cseg

 

 	;.phase	0ffc0h