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-rw-r--r--Makefile15
-rw-r--r--avr/cmd_boot.c18
-rw-r--r--avr/cmd_cpu.c523
-rw-r--r--avr/cmd_misc.c2
-rw-r--r--avr/main.c1
-rw-r--r--avr/z80-if.c4
-rw-r--r--include/common.h1
-rw-r--r--z180/cpuinfo.18095
8 files changed, 197 insertions, 462 deletions
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..a05b308
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,15 @@
+SUBDIRS = avr z180
+
+.PHONY: subdirs $(SUBDIRS) clean
+
+subdirs: $(SUBDIRS)
+
+$(SUBDIRS):
+ $(MAKE) -C $@
+
+clean:
+ $(MAKE) -C avr $@
+ $(MAKE) -C z180 $@
+
+
+avr: z180
diff --git a/avr/cmd_boot.c b/avr/cmd_boot.c
index 036a041..fb533c7 100644
--- a/avr/cmd_boot.c
+++ b/avr/cmd_boot.c
@@ -275,28 +275,24 @@ command_ret_t do_go(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc,
}
if (z80_bus_state() & ZST_RUNNING) {
- printf_P(PSTR("CPU already running!\n"));
- return CMD_RET_FAILURE;
+ cmd_error(CMD_RET_FAILURE, ERUNNING, NULL);
}
printf_P(PSTR("Starting application at 0x%04lx ...\n"), addr);
if (addr != 0) {
- uint8_t tmp[3];
+// uint8_t tmp[3];
- z80_bus_cmd(Request);
- z80_read_block (tmp, 0, 3);
+ z80_bus_request_or_exit();
+// z80_read_block (tmp, 0, 3);
z80_write(0, 0xc3);
z80_write(1, addr);
z80_write(2, (addr >> 8));
+ z80_bus_cmd(Release);
+ _delay_ms(100);
z80_bus_cmd(Run);
- _delay_us(10);
- z80_bus_cmd(M_Cycle);
- _delay_us(10);
- z80_bus_cmd(M_Cycle);
- _delay_us(10);
- z80_write_block(tmp, 0, 3);
+// z80_write_block(tmp, 0, 3);
} else {
if (!hold)
z80_bus_cmd(Request);
diff --git a/avr/cmd_cpu.c b/avr/cmd_cpu.c
index e5158fd..64dd721 100644
--- a/avr/cmd_cpu.c
+++ b/avr/cmd_cpu.c
@@ -21,6 +21,11 @@
#include "../z180/cpuinfo.h"
#undef const
+#define DEBUG_CPU 1 /* set to 1 to debug */
+
+#define debug_cpu(fmt, args...) \
+ debug_cond(DEBUG_CPU, fmt, ##args)
+
/*
* delay for <count> ms...
@@ -32,24 +37,14 @@ static void test_delay(uint32_t count)
while (get_timer(ts) <= count);
}
-uint32_t z80_measure_phi(uint_fast8_t cycles)
+static uint32_t z80_measure_phi(uint_fast8_t cycles)
{
uint16_t ref_stop;
uint16_t ref_ovfl;
uint8_t x_ovfl;
- uint8_t eimsk_save,eicrb_save;
uint32_t x_freq;
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Save state and disable INT6 */
- eimsk_save = EIMSK;
- EIMSK &= ~_BV(INT6);
- /* Save state and set INT6 for falling edge */
- eicrb_save = EICRB;
- EICRB = (eicrb_save & ~(0b11 << ISC60)) | (0b10 << ISC60);
- }
-
PRR1 &= ~_BV(PRTIM3);
TCCR3A = 0;
TCCR3B = 0b000<<CS30; /* stop counter */
@@ -101,29 +96,20 @@ uint32_t z80_measure_phi(uint_fast8_t cycles)
x_ovfl++;
}
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Restore INT6 */
- EICRB = eicrb_save;
- if ((eimsk_save & _BV(INT6)) != 0)
- EIMSK |= _BV(INT6);
- /* Reset pending int */
- EIFR = _BV(INTF6);
- }
-
uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
uint32_t x_cnt = TCNT3 + ((uint32_t) x_ovfl << 16);
uint64_t x_tmp = (uint64_t) 100000 * (x_cnt * cycles);
- debug("TCNT3: %6u, ref_cnt: %9lu\n", TCNT3, ref_cnt);
- debug("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));
+ debug_cpu("TCNT3: %6u, ref_cnt: %9lu\n", TCNT3, ref_cnt);
+ debug_cpu("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));
x_tmp = (x_tmp * getenv_ulong(PSTR(ENV_FMON), 10, F_CPU) + (ref_cnt / 2)) / ref_cnt;
- debug("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));
+ debug_cpu("x_tmp: %lu %lu\n", (uint32_t) (x_tmp >> 32), (uint32_t) (x_tmp & 0xffffffff));
/* round to 5 decimal digits */
int_fast8_t sc = 5;
- while (x_tmp >= 100000) {
+ while (sc > 0 || x_tmp >= 100000) {
x_tmp = (x_tmp + 5)/10;
sc--;
}
@@ -132,8 +118,6 @@ uint32_t z80_measure_phi(uint_fast8_t cycles)
x_freq *= 10;
sc++;
}
- x_freq += (uint32_t) sc << 28;
-
/* Stop Timer */
TCCR3B = 0;
@@ -142,258 +126,144 @@ uint32_t z80_measure_phi(uint_fast8_t cycles)
return x_freq;
}
-#if 0
-float z80_measure_phi(uint_fast8_t cycles, uint16_t wait_ms)
-{
- uint16_t ref_stop;
- uint16_t ref_ovfl;
- uint8_t x_ovfl;
- uint8_t eimsk_save,eicrb_save;
- float x_freq;
+static const FLASH uint8_t loop_code[] = {
+/* 0000 */ 0x00, /* nop */
+/* 0001 */ 0xAF, /* xor a */
+/* 0005 */ 0xD3,0x32, /* out (032h),a ;DCNTL */
+/* 0002 */ 0xD3,0x36, /* out (036h),a ;RCR */
+/* */ /* */
+/* 0006 */ 0xD3,0x40, /* out (040H),a ;Ready */
+/* */ /* */
+/* */ /* ;Z80 Z180(0W) Z180(MaxW) */
+/* 0008 */ /* loop: ;-------------------------- */
+/* 0008 */ 0xDB,0x50, /* in a,(050h) ;11 10 +3*3 19 */
+/* 000A */ 0xC3,0x08,0x00 /* jp loop ;10 9 +3*3 18 */
+ /* ;-------------------------- */
+ /* ;21 19 37 */
+};
+command_ret_t do_cpu_freq(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char * const argv[])
+{
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Save state and disable INT6 */
- eimsk_save = EIMSK;
- EIMSK &= ~_BV(INT6);
- /* Save state and set INT6 for falling edge */
- eicrb_save = EICRB;
- EICRB = (eicrb_save & ~(0b11 << ISC60)) | (0b10 << ISC60);
- }
+#define O_SILENT (1<<0)
+#define O_WENV (1<<1)
+#define O_LOAD_LOOP (1<<2)
+#define O_UNLOAD_LOOP (1<<3)
- PRR1 &= ~_BV(PRTIM3);
- TCCR3A = 0;
- TCCR3B = 0b000<<CS30; /* stop counter */
- TCNT3 = 0;
- x_ovfl = 0;
- TIFR3 = _BV(TOV3);
- ref_ovfl = 0;
+ uint_fast8_t options = O_LOAD_LOOP | O_UNLOAD_LOOP;
+ uint_fast8_t lcycles = 19;
+ uint16_t timeout = 1000;
+ uint8_t eimsk_save;
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Reset pending int */
- EIFR = _BV(INTF6);
- /* Wait for falling edge */
- while ((EIFR & _BV(INTF6)) == 0)
- ;
- TCCR3B = 0b110<<CS30; /* Count falling edges on T3 (==INT6) */
- OCR4B = TCNT4;
- TIFR4 = _BV(OCF4B); /* clear compare match flag */
- }
- while (ref_ovfl < 60) {
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- if ((TIFR4 & _BV(OCF4B)) != 0) {
- TIFR4 = _BV(OCF4B);
- ref_ovfl++;
- }
- if ((TIFR3 & _BV(TOV3)) != 0) {
- TIFR3 = _BV(TOV3);
- x_ovfl++;
- }
- }
- }
+ uint8_t mem_save[ARRAY_SIZE(loop_code)];
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- EIFR = _BV(INTF6);
- for (;;) {
- if (EIFR & _BV(INTF6)) {
- TCCR3B = 0b000<<CS30; /* stop counter */
- ref_stop = TCNT4;
- break;
- }
- if ((TIFR4 & _BV(OCF4B)) != 0) {
- TIFR4 = _BV(OCF4B);
- ref_ovfl++;
- }
+ int opt;
+ while ((opt = getopt(argc, argv, PSTR("swnuc:t:"))) != -1) {
+ switch (opt) {
+ case 's':
+ options |= O_SILENT;
+ break;
+ case 'w':
+ options |= O_WENV;
+ break;
+ case 'n':
+ options &= ~O_LOAD_LOOP;
+ break;
+ case 'u':
+ options &= ~O_UNLOAD_LOOP;
+ break;
+ case 'c':
+ lcycles = eval_arg(optarg, NULL);
+ break;
+ case 't':
+ timeout = eval_arg(optarg, NULL);
+ break;
+ default: /* '?' */
+ return CMD_RET_USAGE;
}
}
+ if (argc - optind != 0)
+ return CMD_RET_USAGE;
- if ((TIFR3 & _BV(TOV3)) != 0) {
- TIFR3 = _BV(TOV3);
- x_ovfl++;
+ if (z80_bus_state() & ZST_RUNNING) {
+ if (!(options & O_SILENT))
+ printf_P(PSTR("Frequency measuring failed. CPU allready running!\n"));
+ return CMD_RET_FAILURE;
}
ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Restore INT6 */
- EICRB = eicrb_save;
- if ((eimsk_save & _BV(INT6)) != 0)
- EIMSK |= _BV(INT6);
- /* Reset pending int */
- EIFR = _BV(INTF6);
- }
-
- uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
-
- uint32_t x_cnt = TCNT3 + ((uint32_t) x_ovfl << 16);
- x_freq = x_cnt * cycles;
-
- x_freq = (x_freq * getenv_ulong(PSTR(ENV_FMON), 10, F_CPU)) / ref_cnt;
-
- debug("TCNT3: %6u, ref_cnt: %9lu\n", TCNT3, ref_cnt);
-#if 0
- debug("ref_start: %6u, ref_stop: %6u, ref_ovfl: %4u, ref_cnt: %9lu\n"
- " TCNT3: %6u, x_cnt: %6lu, xfreq: %f\n",
- OCR4B, ref_stop, ref_ovfl, ref_cnt,
- TCNT3, x_cnt, x_freq);
-#endif
-
-
- /* Stop Timer */
- TCCR3B = 0;
- PRR1 |= _BV(PRTIM3);
-
- return x_freq;
-}
-#endif
-
-#if 0
-int32_t z80_measure_phi(uint_fast8_t cycles, uint16_t wait_ms)
-{
- uint16_t ref_stop;
- uint16_t ref_ovfl;
- uint8_t x_ovfl;
- uint32_t x_freq;
- uint8_t eimsk_save,eicrb_save;
-
-
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Save state and disable INT6 */
+ /* Save state and disable INT5/INT6 */
eimsk_save = EIMSK;
EIMSK &= ~_BV(INT6);
- /* Save state and set INT6 for falling edge */
- eicrb_save = EICRB;
- EICRB = (eicrb_save & ~(0b11 << ISC60)) | (0b10 << ISC60);
+ EIMSK &= ~_BV(INT5);
}
- PRR1 &= ~_BV(PRTIM3);
- TCCR3A = 0;
- TCCR3B = 0b000<<CS30; /* stop counter */
- TCNT3 = 0;
- x_ovfl = 0;
- TIFR3 = _BV(TOV3);
- ref_ovfl = 0;
-
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Reset pending int */
- EIFR = _BV(INTF6);
- /* Wait for falling edge */
- while ((EIFR & _BV(INTF6)) == 0)
- ;
- OCR4B = TCNT4;
- TCCR3B = 0b110<<CS30; /* Count falling edges on T3 (==INT6) */
- TIFR4 = _BV(OCF4B); /* clear compare match flag */
- }
- while (ref_ovfl < 60) {
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- if ((TIFR4 & _BV(OCF4B)) != 0) {
- TIFR4 = _BV(OCF4B);
- ref_ovfl++;
- }
- if ((TIFR3 & _BV(TOV3)) != 0) {
- TIFR3 = _BV(TOV3);
- x_ovfl++;
- }
- }
+ z80_bus_cmd(Request);
+ if (options & O_LOAD_LOOP) {
+ z80_read_block(mem_save, 0, ARRAY_SIZE(loop_code));
+ z80_write_block_P(loop_code, 0, ARRAY_SIZE(loop_code));
}
+ EIFR = _BV(INTF5); /* Reset pending int */
+ z80_bus_cmd(Release);
+ z80_bus_cmd(Run);
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- EIFR = _BV(INTF6);
- for (;;) {
- if (EIFR & _BV(INTF6)) {
- ref_stop = TCNT4;
- TCCR3B = 0b000<<CS30; /* stop counter */
- break;
- }
- if ((TIFR4 & _BV(OCF4B)) != 0) {
- TIFR4 = _BV(OCF4B);
- if (ref_ovfl)
- ref_ovfl++;
- }
- }
- }
+ clear_ctrlc(); /* forget any previous Control C */
+ ERRNUM err = 0;
-#if 0
- ATOMIC_BLOCK(ATOMIC_FORCEON) {
- EIFR = _BV(INTF6);
- for (;;) {
- if (EIFR & _BV(INTF6))
- break;
- if (TIFR4 & _BV(OCF4B)) {
- if (EIFR & _BV(INTF6))
- break;
- TIFR4 = _BV(OCF4B);
- if (EIFR & _BV(INTF6))
- break;
- ref_ovfl++;
- if (EIFR & _BV(INTF6))
- break;
- if (ref_ovfl == 0)
- break;
- }
- }
- ref_stop = TCNT4;
- TCCR3B = 0b000<<CS30; /* stop counter */
- if ((TIFR4 & _BV(OCF4B)) != 0) {
- TIFR4 = _BV(OCF4B);
- if (ref_ovfl)
- ref_ovfl++;
+ /* Wait for falling edge */
+ do {
+ /* check for ctrl-c to abort... */
+ if (had_ctrlc() || ctrlc()) {
+ err = EINTR;
+ break;
}
- }
-#endif
- if ((TIFR3 & _BV(TOV3)) != 0) {
- TIFR3 = _BV(TOV3);
- x_ovfl++;
- }
+ } while ((EIFR & _BV(INTF5)) == 0);
- if (ref_ovfl == 0)
- x_freq = 0xFFFFFFFE;
- else
- {
- uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
-
- x_freq = TCNT3 + ((uint32_t) x_ovfl << 16);
- uint32_t x_cnt = x_freq;
- x_freq *= cycles;
-
- x_freq = ((uint64_t) x_freq * getenv_ulong(PSTR(ENV_FMON), 10, F_CPU) + (ref_cnt / 2))/ ref_cnt;
-
- debug("ref_start: %6u, ref_stop: %6u, ref_ovfl: %4u, ref_cnt: %9lu\n"
- " TCNT3: %6u, x_cnt: %6lu, xfreq: %9lu\n",
- OCR4B, ref_stop, ref_ovfl, ref_cnt,
- TCNT3, x_cnt, x_freq);
+ uint32_t cpu_freq = 0;
+ if (!err)
+ cpu_freq = z80_measure_phi(lcycles);
- /* round to 5 decimal digits */
- uint_fast8_t sc = 0;
- while (x_freq >= 100000UL) {
- x_freq = (x_freq + 5)/10;
- ++sc;
- }
- while (sc--)
- x_freq *= 10;
+ z80_bus_cmd(Reset);
+ if (options & O_UNLOAD_LOOP) {
+ z80_bus_cmd(Request);
+ z80_write_block(mem_save, 0, ARRAY_SIZE(loop_code));
+ z80_bus_cmd(Release);
}
-
- /* Stop Timer */
- TCCR3B = 0;
- PRR1 |= _BV(PRTIM3);
-
ATOMIC_BLOCK(ATOMIC_FORCEON) {
- /* Restore INT6 */
-#if 0 /* wtf? */
- eicrb_save = EICRB;
- EICRB = (EICRB & ~(0b11 << ISC60)) | (eicrb_save & (0b11 << ISC60));
-#endif
- EICRB = eicrb_save;
+ /* Restore INT5/INT6 */
+ if ((eimsk_save & _BV(INT5)) != 0)
+ EIMSK |= _BV(INT5);
if ((eimsk_save & _BV(INT6)) != 0)
EIMSK |= _BV(INT6);
/* Reset pending int */
+ EIFR = _BV(INTF5);
EIFR = _BV(INTF6);
}
- return (int32_t) x_freq;
-}
+ Stat &= ~S_MSG_PENDING;
+ Stat &= ~S_CON_PENDING;
+
+ if (err)
+ cmd_error(CMD_RET_FAILURE, err, NULL);
+
+ if (!(options & O_SILENT)) {
+ uint8_t sc = cpu_freq >> 28;
+ printf_P(PSTR("%lu %3u\n"), cpu_freq & 0x0fffffff, sc);
+ }
+#if 0
+ if (options & O_WENV) {
+ if (setenv_ulong(PSTR(ENV_CPU_FREQ), cpu_freq)) {
+ if (!(options & O_SILENT))
+ printf_P(PSTR("'SETENV (%S, %lu)' failed!\n"), PSTR(ENV_CPU_FREQ), cpu_freq);
+ return CMD_RET_FAILURE;
+ }
+ }
#endif
+ return CMD_RET_SUCCESS;
+}
static const FLASH char * const FLASH cpu_strings[] = {
- FSTR("Unknown CPU"),
+ FSTR("Unknown"),
FSTR("8080"),
FSTR("8085"),
FSTR("Z80"),
@@ -407,6 +277,7 @@ command_ret_t do_cpuchk(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int a
{
uint_fast8_t cputype = 0;
ERRNUM err = ESUCCESS;
+ uint8_t eimsk_save;
uint8_t ram_save[cpuinfo_length];
if (z80_bus_state() & ZST_RUNNING) {
@@ -423,26 +294,41 @@ command_ret_t do_cpuchk(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int a
if (argv[1] && (argv[1][0] == 'n'))
goto donot;
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ /* Save state and disable INT5/INT6 */
+ eimsk_save = EIMSK;
+ EIMSK &= ~_BV(INT6);
+ EIMSK &= ~_BV(INT5);
+ }
+ EIFR = _BV(INTF5); /* Reset pending int */
z80_bus_cmd(Run);
clear_ctrlc(); /* forget any previous Control C */
- uint_fast8_t done = 0;
- while (done != 0xFF) {
- _delay_ms(8);
+ do {
/* check for ctrl-c to abort... */
if (had_ctrlc() || ctrlc()) {
err = EINTR;
break;
}
- z80_bus_cmd(Request);
- done = z80_read(3);
- if (done == 0xFF)
- cputype = z80_read(4);
- z80_bus_cmd(Release);
- }
+ } while ((EIFR & _BV(INTF5)) == 0);
z80_bus_cmd(Reset);
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ /* Restore INT5/INT6 */
+ if ((eimsk_save & _BV(INT5)) != 0)
+ EIMSK |= _BV(INT5);
+ if ((eimsk_save & _BV(INT6)) != 0)
+ EIMSK |= _BV(INT6);
+ /* Reset pending int */
+ EIFR = _BV(INTF5);
+ EIFR = _BV(INTF6);
+ }
+ Stat &= ~S_MSG_PENDING;
+ Stat &= ~S_CON_PENDING;
z80_bus_cmd(Request);
-// z80_write_block(ram_save, 0, cpuinfo_length);
+ if (z80_read(3) == 0xFF) {
+ cputype = z80_read(4);
+ }
+ z80_write_block(ram_save, 0, cpuinfo_length);
z80_bus_cmd(Release);
}
@@ -569,134 +455,15 @@ command_ret_t do_busack_test(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED,
return CMD_RET_SUCCESS;
}
-static const FLASH uint8_t loop_code[] = {
-/* 0000 */ 0x00, /* nop */
-/* 0001 */ 0xAF, /* xor a */
-/* 0005 */ 0xD3,0x32, /* out (032h),a ;DCNTL */
-/* 0002 */ 0xD3,0x36, /* out (036h),a ;RCR */
-/* */ /* */
-/* 0006 */ 0xD3,0x40, /* out (040H),a ;Ready */
-/* */ /* */
-/* */ /* ;Z80 Z180(0W) Z180(MaxW) */
-/* 0008 */ /* loop: ;-------------------------- */
-/* 0008 */ 0xDB,0x50, /* in a,(050h) ;11 10 +3*3 19 */
-/* 000A */ 0xC3,0x08,0x00 /* jp loop ;10 9 +3*3 18 */
- /* ;-------------------------- */
- /* ;21 19 37 */
-};
-
-command_ret_t do_cpu_freq(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int argc, char * const argv[])
-{
-
-#define O_SILENT (1<<0)
-#define O_WENV (1<<1)
-#define O_LOAD_LOOP (1<<2)
-#define O_UNLOAD_LOOP (1<<3)
-
- uint_fast8_t options = O_LOAD_LOOP | O_UNLOAD_LOOP;
- uint_fast8_t lcycles = 19;
- uint16_t timeout = 1000;
-
- uint8_t mem_save[ARRAY_SIZE(loop_code)];
-
- int opt;
- while ((opt = getopt(argc, argv, PSTR("swnuc:t:"))) != -1) {
- switch (opt) {
- case 's':
- options |= O_SILENT;
- break;
- case 'w':
- options |= O_WENV;
- break;
- case 'n':
- options &= ~O_LOAD_LOOP;
- break;
- case 'u':
- options &= ~O_UNLOAD_LOOP;
- break;
- case 'c':
- lcycles = eval_arg(optarg, NULL);
- break;
- case 't':
- timeout = eval_arg(optarg, NULL);
- break;
- default: /* '?' */
- return CMD_RET_USAGE;
- }
- }
- if (argc - optind != 0)
- return CMD_RET_USAGE;
-
- if (z80_bus_state() & ZST_RUNNING) {
- if (!(options & O_SILENT))
- printf_P(PSTR("Frequency measuring failed. CPU allready running!\n"));
- return CMD_RET_FAILURE;
- }
-
-
- z80_bus_cmd(Request);
- if (options & O_LOAD_LOOP) {
- z80_read_block(mem_save, 0, ARRAY_SIZE(loop_code));
- z80_write_block_P(loop_code, 0, ARRAY_SIZE(loop_code));
- }
- Stat &= ~S_IO_0X40; /* Reset pending int */
- z80_bus_cmd(Release);
- z80_bus_cmd(Run);
-
- clear_ctrlc(); /* forget any previous Control C */
- ERRNUM err = 0;
-
- /* Wait for falling edge */
- do {
- /* check for ctrl-c to abort... */
- if (had_ctrlc() || ctrlc()) {
- err = EINTR;
- break;
- }
- } while ((Stat & S_IO_0X40) == 0);
-
- uint32_t cpu_freq = 0;
- if (!err)
- cpu_freq = z80_measure_phi(lcycles);
-
- z80_bus_cmd(Reset);
- if (options & O_UNLOAD_LOOP) {
- z80_bus_cmd(Request);
- z80_write_block(mem_save, 0, ARRAY_SIZE(loop_code));
- z80_bus_cmd(Release);
- }
- if (err)
- cmd_error(CMD_RET_FAILURE, err, NULL);
-
- if (!(options & O_SILENT)) {
- printf_P(PSTR("%lu %3u\n"), cpu_freq & 0x0fffffff, cpu_freq >> 28);
-
-// printf_P(PSTR("%f%S\n"), cpu_freq, cpu_freq < 0 ? PSTR("") : PSTR("Hz"));
-// if (cpu_freq != 0)
-// else
-// printf_P(PSTR("No CPU clock or input frequency to low!\n"));
- }
-#if 0
- if (options & O_WENV) {
- if (setenv_ulong(PSTR(ENV_CPU_FREQ), cpu_freq)) {
- if (!(options & O_SILENT))
- printf_P(PSTR("'SETENV (%S, %lu)' failed!\n"), PSTR(ENV_CPU_FREQ), cpu_freq);
- return CMD_RET_FAILURE;
- }
- }
-#endif
- return CMD_RET_SUCCESS;
-}
-
/*
- * command table for fat subcommands
+ * command table for subcommands
*/
cmd_tbl_t cmd_tbl_cpu[] = {
CMD_TBL_ITEM(
- chkcpu, CONFIG_SYS_MAXARGS, CTBL_RPT, do_cpuchk,
- "Check CPU",
+ chkcpu, CONFIG_SYS_MAXARGS, CTBL_RPT|CTBL_SUBCMDAUTO, do_cpuchk,
+ "Check/Identify CPU",
""
),
CMD_TBL_ITEM(
diff --git a/avr/cmd_misc.c b/avr/cmd_misc.c
index ad913e8..63a510c 100644
--- a/avr/cmd_misc.c
+++ b/avr/cmd_misc.c
@@ -104,7 +104,7 @@ command_ret_t do_time(cmd_tbl_t *cmdtp UNUSED, uint_fast8_t flag UNUSED, int arg
sec = (elapsed_ms / 1000) % 60;
ms = elapsed_ms % 1000;
- printf_P(PSTR("\ntime: %lum%u.%03us\n"), min, sec, ms);
+ printf_P(PSTR("\ntime: %lum %u.%03us\n"), min, sec, ms);
return retval;
}
diff --git a/avr/main.c b/avr/main.c
index 6fd29a8..09df64b 100644
--- a/avr/main.c
+++ b/avr/main.c
@@ -85,7 +85,6 @@ void print_reset_reason(void)
ISR(INT5_vect)
{
Stat |= S_MSG_PENDING;
- Stat |= S_IO_0X40;
}
ISR(INT6_vect)
diff --git a/avr/z80-if.c b/avr/z80-if.c
index 9865208..5a4104d 100644
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -402,7 +402,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
Z80_I_RST = 1; /* Toggle RESET --> inactive */
OCR4B = TCNT4;
TIFR4 = _BV(OCF4B); /* Clear compare match flag */
-/*test*/ TIMSK4 &= ~_BV(OCIE4A); /* Disable Output Compare A interrupt */
+// TIMSK4 &= ~_BV(OCIE4A); /* Disable Output Compare A interrupt */
}
TIMSK4 |= _BV(OCIE4B); /* Enable compare match interrupt */
@@ -414,7 +414,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
ovl_cnt = busack_cycles_ovl;
ifr = TIFR4;
TIMSK4 &= ~_BV(OCIE4B); /* Disable compare match interrupt */
-/*test*/ TIMSK4 |= _BV(OCIE4A); /* Enable Output Compare A interrupt */
+// TIMSK4 |= _BV(OCIE4A); /* Enable Output Compare A interrupt */
}
if (Z80_I_BUSACK == 0) {
if ((ifr & _BV(OCF4B)) && !(tcnt & (1<<15)))
diff --git a/include/common.h b/include/common.h
index 4037ac8..16f96bb 100644
--- a/include/common.h
+++ b/include/common.h
@@ -82,7 +82,6 @@ extern volatile uint_least8_t Stat;
#define S_10MS_TO (1<<0)
#define S_MSG_PENDING (1<<1)
-#define S_IO_0X40 (1<<2)
#define S_CON_PENDING (1<<3)
#define S_RESET_POLARITY (1<<4)
diff --git a/z180/cpuinfo.180 b/z180/cpuinfo.180
index 7d25dc2..0ea3e8e 100644
--- a/z180/cpuinfo.180
+++ b/z180/cpuinfo.180
@@ -31,51 +31,19 @@ done: db 0
result: db 0
;-------------------------------------------------------------------------------
-; Read internal register at address in L and IOBASE in H.
-;
-
-reg_in:
- ld a,h
- add a,l
- ld c,a
- ld b,0
- in a,(c)
- ret
-
-;-------------------------------------------------------------------------------
-; Write internal register at address in L and IOBASE in H.
-;
-
-reg_out:
- ld b,a
- ld a,h
- add a,l
- ld c,a
- ld a,b
- ld b,0
- out (c),a
- ret
-
-;-------------------------------------------------------------------------------
; Check if register C exists. D holds mask of bit to test.
-; return nz, if register exists
+; return z, if register exists
chk_reg:
- call reg_in
- cp 0ffh
- ret nz ;
-
+ in a,(c)
+ ld l,a
; check, if register is changeable
-
- xor d ; set bit(s) in register to 0
- call reg_out
- call reg_in ; get it back
- ex af,af'
- ld a,0ffh ; set to register original state
- call reg_out
- ex af,af'
- cpl
- and d
+ xor d ;
+ out (c),a
+ in a,(c) ; get it back
+ xor d
+ out (c),l ; set register to original state
+ cp l
ret
;-------------------------------------------------------------------------------
@@ -142,56 +110,47 @@ chk_z80:
; At least Hitachi HD64180
; Test differences in certain internal registers
; to determine the 180 variant.
- ; First, search the internal register bank.
-
- ld h,00H ; I/O Base
-find_base_loop:
- ld l,icr
- call reg_in
- and 11011111b ; mask I/O Stop bit
- xor h
+
+ ld b,0
+ ld c,icr
+ in a,(c)
cp 01FH
- jr nz,nxt_base
+ jr z,icr_ok
;TODO: additional plausibility checks
- jr z,base_found
-nxt_base:
- ld a,h
- add a,040H
- ld h,a
- jr nc,find_base_loop
- ret ;I/O registers not found
+ ret ; I/O registers not found
; Register (base) found.
-base_found:
+icr_ok:
inc e ; HD64180
- ld l,RCR ; Disable Refresh Controller
- xor a ;
- call reg_out ;
- ld l,omcr ; Check, if CPU has OMCR register
+ out0 (RCR),b ;
+ ld c,omcr ; Check, if CPU has OMCR register
ld d,M_IOC ;
call chk_reg ;
- ret z ; Register does not exist. It's a HD64180
+ ret nz ; Register does not exist. It's a HD64180
inc e ; Z80180
- ld l,cmr ; Check, if CPU has CMR register
+ ld c,cmr ; Check, if CPU has CMR register
ld d,M_LNC ;
call chk_reg ;
- ret z ; register does not exist. It's a Z80180
+ ret nz ; register does not exist. It's a Z80180
inc e ; S180/L180 (class) detected.
-
ret
;-------------------------------------------------------------------------------
start:
ld sp,stack
+ ld hl,done
+ ld (hl),0
+ inc hl
+ ld (hl),0
+ push hl
call check
-
- ld hl,result
+ pop hl
ld (hl),e
dec hl
ld (hl),0ffH
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-02 04:12:49 +0000