[avrcpm.git] / cpm / utils / AVRCLOCK.MAC

VERS	EQU	02\r
	.Z80\r
;	NAME	AVRCLK		; Change this to no more than 6-char\r
				; name for the REL driver module\r
\r
;---------------------------------------------------------------------\r
; Time format (6 bytes packed BCD)\r
; \r
; TIME+0	last 2 digits of year (prefix 19 assumed for 78 to 99, else 20 assumed)\r
; TIME+1	month [1..12]\r
; TIME+2	day [1..31]\r
; TIME+3	hour [0..23]\r
; TIME+4	minute [0..59]\r
; TIME+5	second [0..59]\r
; \r
\r
; This first section contains identification information for the driver\r
; The information is not placed in the clock driver code section, but are\r
; located in a different area located by the _CLKID Named Common directive.\r
\r
	COMMON	/_CLKID/\r
\r
DESCST:	DEFW	0000		; Add label here if a static year byte\r
				; is used by your clock driver.  The\r
				; label should point to the year byte\r
\r
		;123456789012345678901234\r
CLKNAM:	DEFB	'AVRCPM Clock            '	; Exactly 24 chars in name\r
	DEFB	VERS/10+'0','.',VERS MOD 10 +'0',0\r
\r
DESCR:	DEFB	'This is the AVRCPM clock',0\r
\r
\r
;---------------------------------------------------------------------\r
; This section contains any configurable parameters needed for the\r
; clock driver.  They must be structured in the manner shown in order\r
; for the loader to properly match and set the values.\r
; The values in this section are not loaded in the same code section\r
; as the actual driver code, but are located in another base referenced\r
; by the _PARM_ Named Common directive.\r
\r
	COMMON	/_PARM_/\r
\r
PARBAS:	DEFW	0		; # of parameters (Set to 00 if none)\r
	DEFW    0		; Pointer to STRS (Set to 00 if none)\r
\r
;------------------------------------------------------------------\r
; This section should contain the actual Clock Driver code, and all\r
; entries here are located in the CSEG, or Code Segment.\r
\r
	CSEG\r
\r
MHZ     equ	2               ; Base Processor speed\r
CLOCKPORT equ	47h\r
\r
;-----------------------------------------------------------\r
;	    Z S D O S    C L O C K    H E A D E R\r
;-----------------------------------------------------------\r
; Enter: HL points to a 6-byte buffer to Get/Set time\r
; Exit :  A=1 on Success, A=FFH if error\r
;	 HL points to last char in buffer\r
;	E contains original seconds (HL+5)\r
; NOTE: If clock Set is not included, comment these two jumps\r
;	out to save a few bytes.  The loader, SETUPZST, uses\r
;	these two jumps to recognize a full ZSDOS clock and\r
;	modify the interface code.\r
\r
PRGBAS:	JP	GETTIM		; Jump to Read Clock\r
	JP	WRCLK		; Jump to Set Clock\r
\r
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
;		R e a d    T h e    C l o c k\r
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
\r
GETTIM:				; The work of reading the clock\r
				; goes here.  Values needing to be set\r
				; during installation are referenced as:\r
	ld	bc,5\r
	add	hl,bc\r
	push	hl\r
	ld	b,6\r
	ld	c,CLOCKPORT\r
	ld	e,(hl)\r
GETT_l:\r
	in	a,(c)\r
	ld	(hl),a\r
	inc	c\r
	dec	hl\r
	djnz	GETT_l\r
	pop	hl\r
	ld	a,1\r
	ret\r
	\r
\r
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
;		S e t    T h e    C l o c k\r
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
\r
WRCLK:\r
	ld	a,(hl)\r
	cp	78h\r
	ld	a,19h\r
	jr	nc,WRC_1\r
	ld	a,20h\r
WRC_1:\r
	out	(CLOCKPORT+6),a\r
	ld	b,6\r
	ld	c,CLOCKPORT+5\r
WRC_l:\r
	ld	a,(hl)\r
	out	(c),a	\r
	dec	c\r
	inc	hl\r
	djnz	WRC_l\r
	dec	hl\r
	ld	a,1\r
	ret\r
\r
\r
;-------------------------------------------------------------\r
; This code installs configurable items into the clock module\r
; Enter with DE pointing to the physical base address of the\r
;	 relocatable module.  DE MUST BE USED TO SET VALUES IN\r
;	 THE CSEG PORTION OF CODE!\r
; NOTE: Code in this section is not added to the actual clock\r
;	driver, but placed in a different area referenced to\r
;	the common base _POST_.\r
\r
	COMMON	/_POST_/\r
\r
; Values in the _PARM_, _POST_ and _PRE_ sections may be loaded\r
; and saved directly, since their addresses are constant from\r
; linkage through execution.  Setting or reading values in the\r
; CSEG must be indirect based on the value in the DE register\r
; pair.  The following examples show how to access the various\r
; sections.\r
;\r
;	LD	A,(XYR)		; EXAMPLE - Get byte from _PARM_ directly\r
;	LD	HL,YYR		;    "    - Begin offset into CSEG indirectly\r
;	ADD	HL,DE		;    "    - HL now addresses relocated loc'n\r
;	LD	(HL),A		;    "    - ..so value can be stored\r
;\r
; Likewise, 16-bit values must be accessed indirectly, and may use\r
; the BC register pair as transfer storage.\r
;\r
;	LD	BC,(XPORT)	; EXAMPLE - Get word from _PARM_ directly\r
;	LD	HL,YPORT1	;    "    - Begin offset into CSEG indirectly\r
;	ADD	HL,DE		;    "    - HL now addresses relocated loc'n\r
;	LD	(HL),C		;    "    - ..so value can be saved..\r
;	INC	HL		;    "    - ...a byte..\r
;	LD	(HL),B		;    "    - ....at a time..\r
;\r
;	LD	(YPORT2),BC	; EXAMPLE - Values can be stored directly into\r
;				     "    - other sections such as _PRE_\r
\r
	RET		; This RETURN MUST be present even if no other\r
			; code is included in this section\r
\r
\r
;----------------------------------------------------------------\r
; This module is executed just prior to installing the module to\r
;   insure that a valid clock is present\r
; Enter with DE pointing to base of relocated clock code segment\r
;---------------------------------------------------------------\r
; Read clock and wait for seconds to roll - watchdog protected\r
; Enter with: DE pointing to relocated clock read routine\r
;	HL pointing to base of high module\r
\r
	COMMON	/_PRE_/\r
\r
; Optional final setup of the clock module may go here.  Examples of such\r
; code would be installation-dependant items such as physical RAM location\r
; for the driver module.  If any code is added here, the DE register pair\r
; MUST be preserved to properly inter PRECLOCK code (If included).\r
\r
;YPORT2	EQU	$+1		; EXAMPLE - just to show accessing method\r
;	LD	BC,0000		;    "    - ..from _POST_ code.\r
\r
	INCLUDE	PRECLOCK.LIB	; This section of code merely calls the\r
				; clock and waits an arbitrary period of\r
				; time (>> 1 second) to see if the time\r
				; changes.  It returns an error if not.\r
	if 0\r
TSTRD:	JR	TSTRD0	; Jump around address store\r
\r
	DEFW    TSTRD	; Org location of the code\r
TSTRD0:	SCF\r
	LD      A,1\r
	RET\r
	endif\r
\r
\r
\r
	END\r
\1a\r
Commit	Line	Data
d8fa6a36 L	1	VERS EQU 02\r
	2	.Z80\r
	3	; NAME AVRCLK ; Change this to no more than 6-char\r
	4	; name for the REL driver module\r
	5	\r
	6	;---------------------------------------------------------------------\r
	7	; Time format (6 bytes packed BCD)\r
	8	; \r
	9	; TIME+0 last 2 digits of year (prefix 19 assumed for 78 to 99, else 20 assumed)\r
	10	; TIME+1 month [1..12]\r
	11	; TIME+2 day [1..31]\r
	12	; TIME+3 hour [0..23]\r
	13	; TIME+4 minute [0..59]\r
	14	; TIME+5 second [0..59]\r
	15	; \r
	16	\r
	17	; This first section contains identification information for the driver\r
	18	; The information is not placed in the clock driver code section, but are\r
	19	; located in a different area located by the _CLKID Named Common directive.\r
	20	\r
	21	COMMON /_CLKID/\r
	22	\r
	23	DESCST: DEFW 0000 ; Add label here if a static year byte\r
	24	; is used by your clock driver. The\r
	25	; label should point to the year byte\r
	26	\r
	27	;123456789012345678901234\r
	28	CLKNAM: DEFB 'AVRCPM Clock ' ; Exactly 24 chars in name\r
	29	DEFB VERS/10+'0','.',VERS MOD 10 +'0',0\r
	30	\r
	31	DESCR: DEFB 'This is the AVRCPM clock',0\r
	32	\r
	33	\r
	34	;---------------------------------------------------------------------\r
	35	; This section contains any configurable parameters needed for the\r
	36	; clock driver. They must be structured in the manner shown in order\r
	37	; for the loader to properly match and set the values.\r
	38	; The values in this section are not loaded in the same code section\r
	39	; as the actual driver code, but are located in another base referenced\r
	40	; by the _PARM_ Named Common directive.\r
	41	\r
	42	COMMON /_PARM_/\r
	43	\r
	44	PARBAS: DEFW 0 ; # of parameters (Set to 00 if none)\r
	45	DEFW 0 ; Pointer to STRS (Set to 00 if none)\r
	46	\r
	47	;------------------------------------------------------------------\r
	48	; This section should contain the actual Clock Driver code, and all\r
	49	; entries here are located in the CSEG, or Code Segment.\r
	50	\r
	51	CSEG\r
	52	\r
	53	MHZ equ 2 ; Base Processor speed\r
	54	CLOCKPORT equ 47h\r
	55	\r
	56	;-----------------------------------------------------------\r
	57	; Z S D O S C L O C K H E A D E R\r
	58	;-----------------------------------------------------------\r
	59	; Enter: HL points to a 6-byte buffer to Get/Set time\r
	60	; Exit : A=1 on Success, A=FFH if error\r
	61	; HL points to last char in buffer\r
	62	; E contains original seconds (HL+5)\r
	63	; NOTE: If clock Set is not included, comment these two jumps\r
	64	; out to save a few bytes. The loader, SETUPZST, uses\r
65	; these two jumps to recognize a full ZSDOS clock and\r
66	; modify the interface code.\r
67	\r
68	PRGBAS: JP GETTIM ; Jump to Read Clock\r
69	JP WRCLK ; Jump to Set Clock\r
70	\r
71	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
72	; R e a d T h e C l o c k\r
73	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
74	\r
75	GETTIM: ; The work of reading the clock\r
76	; goes here. Values needing to be set\r
77	; during installation are referenced as:\r
78	ld bc,5\r
79	add hl,bc\r
80	push hl\r
81	ld b,6\r
82	ld c,CLOCKPORT\r
83	ld e,(hl)\r
84	GETT_l:\r
85	in a,(c)\r
86	ld (hl),a\r
87	inc c\r
88	dec hl\r
89	djnz GETT_l\r
90	pop hl\r
91	ld a,1\r
92	ret\r
93	\r
94	\r
95	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
96	; S e t T h e C l o c k\r
97	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
98	\r
99	WRCLK:\r
100	ld a,(hl)\r
101	cp 78h\r
102	ld a,19h\r
103	jr nc,WRC_1\r
104	ld a,20h\r
105	WRC_1:\r
106	out (CLOCKPORT+6),a\r
107	ld b,6\r
108	ld c,CLOCKPORT+5\r
109	WRC_l:\r
110	ld a,(hl)\r
111	out (c),a \r
112	dec c\r
113	inc hl\r
114	djnz WRC_l\r
115	dec hl\r
116	ld a,1\r
117	ret\r
118	\r
119	\r
120	;-------------------------------------------------------------\r
121	; This code installs configurable items into the clock module\r
122	; Enter with DE pointing to the physical base address of the\r
123	; relocatable module. DE MUST BE USED TO SET VALUES IN\r
124	; THE CSEG PORTION OF CODE!\r
125	; NOTE: Code in this section is not added to the actual clock\r
126	; driver, but placed in a different area referenced to\r
127	; the common base _POST_.\r
128	\r
129	COMMON /_POST_/\r
130	\r
131	; Values in the _PARM_, _POST_ and _PRE_ sections may be loaded\r
132	; and saved directly, since their addresses are constant from\r
133	; linkage through execution. Setting or reading values in the\r
134	; CSEG must be indirect based on the value in the DE register\r
135	; pair. The following examples show how to access the various\r
136	; sections.\r
137	;\r
138	; LD A,(XYR) ; EXAMPLE - Get byte from _PARM_ directly\r
139	; LD HL,YYR ; " - Begin offset into CSEG indirectly\r
140	; ADD HL,DE ; " - HL now addresses relocated loc'n\r
141	; LD (HL),A ; " - ..so value can be stored\r
142	;\r
143	; Likewise, 16-bit values must be accessed indirectly, and may use\r
144	; the BC register pair as transfer storage.\r
145	;\r
146	; LD BC,(XPORT) ; EXAMPLE - Get word from _PARM_ directly\r
147	; LD HL,YPORT1 ; " - Begin offset into CSEG indirectly\r
148	; ADD HL,DE ; " - HL now addresses relocated loc'n\r
149	; LD (HL),C ; " - ..so value can be saved..\r
150	; INC HL ; " - ...a byte..\r
151	; LD (HL),B ; " - ....at a time..\r
152	;\r
153	; LD (YPORT2),BC ; EXAMPLE - Values can be stored directly into\r
154	; " - other sections such as _PRE_\r
155	\r
156	RET ; This RETURN MUST be present even if no other\r
157	; code is included in this section\r
158	\r
159	\r
160	;----------------------------------------------------------------\r
161	; This module is executed just prior to installing the module to\r
162	; insure that a valid clock is present\r
163	; Enter with DE pointing to base of relocated clock code segment\r
164	;---------------------------------------------------------------\r
165	; Read clock and wait for seconds to roll - watchdog protected\r
166	; Enter with: DE pointing to relocated clock read routine\r
167	; HL pointing to base of high module\r
168	\r
169	COMMON /_PRE_/\r
170	\r
171	; Optional final setup of the clock module may go here. Examples of such\r
172	; code would be installation-dependant items such as physical RAM location\r
173	; for the driver module. If any code is added here, the DE register pair\r
174	; MUST be preserved to properly inter PRECLOCK code (If included).\r
175	\r
176	;YPORT2 EQU $+1 ; EXAMPLE - just to show accessing method\r
177	; LD BC,0000 ; " - ..from _POST_ code.\r
178	\r
179	INCLUDE PRECLOCK.LIB ; This section of code merely calls the\r
180	; clock and waits an arbitrary period of\r
181	; time (>> 1 second) to see if the time\r
182	; changes. It returns an error if not.\r
183	if 0\r
184	TSTRD: JR TSTRD0 ; Jump around address store\r
185	\r
186	DEFW TSTRD ; Org location of the code\r
187	TSTRD0: SCF\r
188	LD A,1\r
189	RET\r
190	endif\r
191	\r
192	\r
193	\r
194	END\r
195	\1a\r