avrcpm/avr/config.inc

   1 ;    Configuration, hardware definition, ...
   2 ;
   3 ;    Copyright (C) 2010 Sprite_tm
   4 ;    Copyright (C) 2010 Leo C.
   5 ;
   6 ;    This file is part of avrcpm.
   7 ;
   8 ;    avrcpm is free software: you can redistribute it and/or modify it
   9 ;    under the terms of the GNU General Public License as published by
  10 ;    the Free Software Foundation, either version 3 of the License, or
  11 ;    (at your option) any later version.
  12 ;
  13 ;    avrcpm is distributed in the hope that it will be useful,
  14 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;    GNU General Public License for more details.
  17 ;
  18 ;    You should have received a copy of the GNU General Public License
  19 ;    along with avrcpm.  If not, see <http://www.gnu.org/licenses/>.
  20 ;
  21 ;    $Id$
  22 ;
  23
  24
  25 #define VMAJOR 2                /* Version number */
  26 #define VMINOR 0
  27
  28 #ifndef DRAM_8BIT
  29   #define DRAM_8BIT 1           /* 1 = 8bit wide DRAM */
  30 #endif
  31 #ifndef F_CPU
  32   #define F_CPU  20000000       /* system clock in Hz; defaults to 20MHz */
  33 #endif
  34 #ifndef BAUD
  35   #define BAUD   38400          /* console baud rate */
  36 #endif
  37
  38 #define K 1024
  39 #define M 1204*K
  40
  41 ;#define RAMSIZE 256*K*4        /* 1 chip 256Kx4 */
  42 #define  RAMSIZE   4*M*4 * 2    /* 2 chips 4Mx4  */
  43
  44 #define RAMDISKCNT 0            /* Number of RAM disks */
  45 #define RAMDISKNR 'I'-'A'       /* Drive "letter" for first RAM disk */
  46
  47 #define PARTID 0x52             /* Partition table id */
  48                                 /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
  49 #define IPLADDR 0x2000          /* Bootloader load address */
  50
  51 #define DRAM_WAITSTATES 1       /* Number of additional clock cycles for dram read access */
  52 #define REFR_RATE   64000       /* dram refresh rate in cycles/s. */
  53                                 /* Most drams need 1/15.6µs. */
  54 #define RXBUFSIZE 128           /* USART recieve buffer size. Must be power of 2 */
  55 #define TXBUFSIZE 128           /* USART transmit buffer size. Must be power of 2 */
  56
  57
  58
  59 #define EM_Z80  0               /* we don't have any z80 instructions yet */
  60
  61 .equ BOOT_DEBUG  = 0
  62 .equ MMC_DEBUG   = 0            /* Increase for more debugging */
  63 .equ INS_DEBUG   = 0
  64 .equ MEMTEST     = 1
  65 .equ BOOTWAIT    = 1
  66 .equ PORT_DEBUG  = 0
  67 .equ DISK_DEBUG  = 0            /* Increase for more debugging */
  68 .equ HOSTRW_DEBUG= 0
  69 .equ MEMFILL     = 1
  70 .equ STACK_DBG   = 0
  71 .equ PRINT_PC    = 0
  72 .equ HEAP_DEBUG  = 1
  73
  74 #define MMC_SPI2X  1            /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
  75
  76 #define MEMFILL_VAL      0xCB   /* Fill ram with cbs, which will trigger an invalid opcode error. */
  77 #define DBG_TRACE_BOTTOM 0x01   /* Page boundaries for INS_DEBUG and PRINT_PC  */
  78 #define DBG_TRACE_TOP    0xdc   /* Trace is off, below bottom page and above top page. */
  79
  80 ;-----------------------------------------------------------------------
  81 ; Port declarations
  82
  83 #if DRAM_8BIT   /* Implies software uart */
  84
  85 ;Port D
  86 .equ RAM_D0     = 0
  87 .equ RAM_D1     = 1
  88 .equ RAM_D2     = 2
  89 .equ RAM_D3     = 3
  90 .equ RAM_D4     = 4
  91 .equ RAM_D5     = 5
  92 .equ RAM_D6     = 6
  93 .equ RAM_D7     = 7
  94 .equ RAM_A0     = 0
  95 .equ RAM_A1     = 1
  96 .equ RAM_A2     = 2
  97 .equ RAM_A3     = 3
  98 .equ RAM_A4     = 4
  99 .equ RAM_A5     = 5
 100 .equ RAM_A6     = 6
 101 .equ RAM_A7     = 7
 102
 103 ;Port B
 104 .equ MMC_MOSI   = 3
 105 .equ MMC_MISO   = 4
 106 .equ MMC_SCK    = 5
 107 .equ RAM_A8     = 3
 108 .equ RAM_A9     = 4
 109 .equ RAM_A10    = 5
 110
 111 .equ RXD        = 0
 112 .equ TXD        = 1
 113 .equ MMC_CS     = 2
 114
 115 .equ P_MMC_CS   = PORTB
 116 .equ P_A8       = PORTB
 117 .equ P_RXD      = PORTB
 118
 119 ;Port C
 120 .equ RAM_RAS    = 0
 121 .equ RAM_CAS    = 1
 122 .equ RAM_OE     = 2
 123 .equ RAM_W      = 3
 124
 125 .equ P_RAS      = PORTC
 126 .equ P_CAS      = PORTC
 127 .equ P_OE       = PORTC
 128 .equ P_W        = PORTC
 129
 130
 131 #else   /* 4 bit RAM, hardware uart */
 132
 133 ; Port D
 134 .equ RXD        = 0
 135 .equ TXD        = 1
 136 .equ RAM_OE     = 2
 137 .equ RAM_A8     = 3
 138 .equ MMC_CS     = 4
 139 .equ RAM_A5     = 5
 140 .equ RAM_A6     = 6
 141 .equ RAM_A7     = 7
 142
 143 .equ P_RXD      = PORTD
 144 .equ P_OE       = PORTD
 145 .equ P_A8       = PORTD
 146 .equ P_MMC_CS   = PORTD
 147 .equ P_AH       = PORTD
 148                      ; RAM_A[7..5]
 149 .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5)
 150 .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK
 151
 152
 153 ;Port B
 154 .equ RAM_A4     = 0
 155 .equ RAM_A3     = 1
 156 .equ RAM_A2     = 2
 157 .equ RAM_A1     = 3
 158 .equ MMC_MOSI   = 3
 159 .equ RAM_A0     = 4
 160 .equ MMC_MISO   = 4
 161 .equ RAM_RAS    = 5
 162 .equ MMC_SCK    = 5
 163
 164 .equ P_RAS      = PORTB
 165 .equ P_AL       = PORTB
 166                         ; RAM_A[4..0]
 167 .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0)
 168 .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK
 169
 170 ;Port C
 171 .equ RAM_D0     = 0
 172 .equ RAM_D1     = 1
 173 .equ RAM_D2     = 2
 174 .equ RAM_D3     = 3
 175 .equ RAM_W      = 4
 176 .equ RAM_CAS    = 5
 177
 178 .equ P_DQ       = PORTC
 179 .equ P_W        = PORTC
 180 .equ P_CAS      = PORTC
 181
 182 .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0)
 183 .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W)
 184
 185 #endif  /* DRAM_8BIT */
 186
 187
 188 ;-----------------------------------------------------------------------
 189 ;Register definitions
 190
 191 .def    _tmp0   = r0
 192 .def    _tmp1   = r1
 193
 194 .def    _RAS0   = r2
 195 .def    _CAS0   = r3
 196 .def    _OE     = r4
 197 .def    _WE     = r5
 198 .def    _255    = r6
 199 .def    _0      = r7
 200 .def    z_a     = r9
 201 ;.def   stx_bitcount  = r9
 202 ;.def   stx_dr        = r10
 203 .def    srx_lastedgel = r10
 204 .def    srx_lastedgeh = r11
 205
 206 .def    insstore= r8    ;
 207 ;.def   insop   = r13   ;
 208 .def    insdecl = r12   ;
 209 .def    insdech = r13   ;
 210 .def    z_spl   = r14
 211 .def    z_sph   = r15   ;
 212 .def    temp    = r16   ;
 213 .def    temp2   = r17   ;
 214 .def    temp3   = r18
 215 .def    temp4   = r19
 216 .def    z_flags = r20   ;
 217                         ;
 218 .def    opl     = r22   ;
 219 .def    oph     = r23   ;
 220 .def    z_pcl   = r24   ;
 221 .def    z_pch   = r25   ;
 222 ; xl            ;r26
 223 ; xh            ;r27
 224 ; yl            ;r28
 225 ; yh            ;r29
 226 ; zl            ;r30    ;
 227 ; zh            ;r31    ;
 228
 229
 230
 231 #if defined __ATmega8__
 232 .equ    flags   = TWBR
 233 .equ    P_PUD   = SFIOR
 234 #else
 235 .equ    flags   = GPIOR0
 236 .equ    P_PUD   = MCUCR
 237 #endif
 238
 239 ; Flags:
 240         .equ    hostact = 7             ;host active flag
 241         .equ    hostwrt = 6             ;host written flag
 242         .equ    rsflag  = 5             ;read sector flag
 243         .equ    readop  = 4             ;1 if read operation
 244         .equ    trace   = 0
 245
 246 ; This is the base z80 port address for clock access
 247 #define TIMERPORT   0x40
 248 #define TIMER_CTL   TIMERPORT
 249 #define TIMER_MSECS TIMERPORT+1
 250 #define TIMER_SECS  TIMER_MSECS+2
 251
 252 #define starttimercmd   1
 253 #define quitTimerCmd    2
 254 #define printTimerCmd   15
 255 #define uptimeCmd       16
 256
 257 #if defined __ATmega8__
 258 .equ    RXTXDR0 = UDR
 259 .equ    UCSR0A  = UCSRA
 260 .equ     UDRE0  = UDRE
 261 .equ    UCSR0B  = UCSRB
 262 .equ     RXCIE0 = RXCIE
 263 .equ     UDRIE0 = UDRIE
 264 .equ     RXEN0  = RXEN
 265 .equ     TXEN0  = TXEN
 266 .equ    UCSR0C  = UCSRC
 267 .equ     UCSZ00 = UCSZ0
 268 .equ     UCSZ01 = UCSZ1
 269 .equ    UBRR0H  = UBRRH
 270 .equ    UBRR0L  = UBRRL
 271 .equ    OCR2A   = OCR2
 272 .equ    OC2Aaddr= OC2addr
 273 .equ    TCCR2A  = TCCR2
 274 .equ    TCCR2B  = TCCR2
 275 .equ    TIMSK1  = TIMSK
 276 .equ    TIMSK2  = TIMSK
 277 .equ    OCIE2A  = OCIE2
 278 .equ    TIFR1   = TIFR
 279 .equ    ICIE1   = TICIE1
 280 #else
 281 .equ    RXTXDR0 = UDR0
 282 #endif
 283
 284 ; vim:set ts=8 noet nowrap
 285
 286