HEXTOBIN = $(OBJCOPY) -I ihex -O binary --gap-fill 0xff
#(call conf-val,config-id,config-file)
-#conf-val = $(shell awk -vID=$(strip $1) '$$0 ~ "^[ \t]*\#define[ \t]+" ID "[ \t]+" {print $$3}' $2 )
-conf-val = $(shell awk -vID=$(strip $1) '$$1$$2 ~ "\#define"ID {print $$3}' $2)
+#conf-val = $(shell $(AWK) -vID=$(strip $1) '$$0 ~ "^[ \t]*\#define[ \t]+" ID "[ \t]+" {print $$3}' $2 )
+conf-val = $(shell $(AWK) -vID=$(strip $1) '$$1$$2 ~ "\#define"ID {print $$3}' $2)
# Programming support using avrdude. Settings and variables.
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: Z80int-jmp.asm 93 2014-01-03 16:32:32Z rapid $
;
#if EM_Z80
do_store_pcrel: ;add displacement to PC
#if EM_Z80
- clr oph
- tst opl ;sign extend
- brpl stpcr1
- com oph
-stpcr1:
+ mov oph,opl ;sign extend
+ lsl oph
+ sbc oph,oph
add z_pcl,opl
adc z_pch,oph
ret
opprxcb_1:
mem_read_s z_pc ;get displacement
adiw z_pcl,1 ;++z_pc
- clr temp2 ;sign extend
- tst temp
- brpl PC+2
- com temp2
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_read_d opl
fetchmxx1:
mem_read_ds opl, z_pc ;get displacement
adiw z_pcl,1
- clr oph ;sign extend
- tst opl
- brpl fetchmxx2
- com oph
-fetchmxx2:
+ mov oph,opl ;sign extend
+ lsl oph
+ sbc oph,oph
add xl,opl ;add displacement
adc xh,oph
mem_read_d opl ;get operand
storemxx1:
mem_read_s z_pc ;get displacement
adiw z_pcl,1
- clr temp2 ;sign extend
- tst temp
- brpl storemxx2
- com temp2
-storemxx2:
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_write_s opl ;store operand
mem_read_s z_pc ;get displacement
adiw z_pcl,1
adiw z_pcl,1
- clr temp2 ;sign extend
- tst temp
- brpl storemxx22
- com temp2
-storemxx22:
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_write_s opl ;store operand
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: config.inc 242 2015-12-11 16:05:52Z rapid $
-#define VMAJOR 3 /* Version number */
-#define VMINOR 2
+#define VMAJOR 3 /* Version number */
+#define VMINOR 5
+#define VERS_STR "3.5"
+
;-----------------------------------------------------------------------
;
; or use the I2C pins for other purposes.
;#define I2C_SUPPORT
+; Support for the SC16IS740 I2C UART chip is included automatically, when
+; I2C support is enabled. Uncomment and set to 0 if you don't want support for
+; the SC16IS740 I2C UART chip.
+;#define I2C_UART_SUPPORT 1
+
; Emulate Z80 cpu if 1, 8080 otherwise.
;
;#define EM_Z80 1
;-----------------------------------------------------------------------
;Debugging aids
-.equ BOOTWAIT = 1
-.equ MEMTEST = 1
-.equ MEMFILL = 1 /* Fill DRAM */
-.equ SRAM_FILL = 1 /* Fill unused SRAM */
-.equ MMC_DEBUG = 0 /* Increase for more debugging */
-.equ MMC_DEBUG_RDW = 0
-.equ DSKSEL_DEBUG = 0
-.equ DISK_DEBUG = 0 /* 1 = BOOT/HOME debug, 2 = +R/W debug */
-.equ HOSTRW_DEBUG = 0
-.equ FAT16_DEBUG = 0
-.equ FAT16_DBG_FAT = 0
-.equ HEAP_DEBUG = 0
-.equ PORT_DEBUG = 0
-.equ INS_DEBUG = 0
-.equ STACK_DBG = 0
-.equ PRINT_PC = 0
-.equ TIMER_DEBUG = 0
+.equ BOOTWAIT = 1
+.equ MEMTEST = 1
+.equ MEMFILL = 1 /* Fill DRAM */
+.equ SRAM_FILL = 1 /* Fill unused SRAM */
+.equ MMC_DEBUG = 0 /* Increase for more debugging */
+.equ MMC_DEBUG_RDW = 0
+.equ DSKSEL_DEBUG = 0
+.equ DISK_DEBUG = 0 /* 1 = BOOT/HOME debug, 2 = +R/W debug */
+.equ HOSTRW_DEBUG = 0
+.equ FAT16_DEBUG = 0
+.equ FAT16_DBG_FAT = 0
+.equ HEAP_DEBUG = 0
+.equ PORT_DEBUG = 0
+.equ INS_DEBUG = 0
+.equ STACK_DBG = 0
+.equ PRINT_PC = 0
+.equ TIMER_DEBUG = 0
+.equ I2C_STATE_DEBUG = 0
+.equ MEMDUMP_DEBUG = 1
;-----------------------------------------------------------------------
; Z80/8080 Virtual Ports
#define printTimerCmd 15
#define uptimeCmd 16
-#define DEBUGPORT 0x4F
+#define MEMDUMPPORT 0x09
+#define DEBUGPORT 0x4F
-#define startTraceCmd 0x01 /* 'OUT (DEBUGPORT),startTraceCmd' starts tracing */
-#define stopTraceCmd 0x00
-#define PrintStackCmd 0x02
+#define startTraceCmd 0x01 /* 'OUT (DEBUGPORT),startTraceCmd' starts tracing */
+#define stopTraceCmd 0x00
+#define PrintStackCmd 0x02
; Virtual I2C Interface
#define I2CSTAT 0x05
#define ADCBGL 0x20 /* Read 1.1V Bandgap, 10 bit */
#define ADCBGH 0x21 /* Read 1.1V Bandgap, 10 bit */
+; ISC16IS740 UART
+#define I2C_UART 0x50 /* ISC16IS740 base port */
; Port-Expander PCF8574
#define PORT 0x80
#define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
/* Most drams need 1/15.6µs. */
#define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
-#define TXBUFSIZE 32 /* USART transmit buffer size. Must be power of 2 */
+.if SRAM_SIZE > 1024
+ .equ TXBUFSIZE = 128 /* USART transmit buffer size. Must be power of 2 */
+.else
+ .equ TXBUFSIZE = 32 /* USART transmit buffer size. Must be power of 2 */
+.endif
+
+.if SRAM_SIZE > 1024
+ .equ FAT16_FATBUF = 1
+.else
+ .equ FAT16_FATBUF = 0
+.endif
+
#define I2C_CLOCK 100000 /* 100kHz */
-#define I2C_BUFSIZE 17 /* largest message size including address byte (SLA) */
+#define I2C_BUFSIZE 66 /* largest message size + slave address (SLA) + subaddress */
#define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
#ifndef ADC_SUPPORT
#define ADC_SUPPORT 1
#endif
+#ifndef I2C_UART_SUPPORT
+ #define I2C_UART_SUPPORT I2C_SUPPORT
+#endif
+#if I2C_UART_SUPPORT
+ #define SC16IS740_ADDR 0x90 /* SC16IS740 I2C address. (8bit, A0=VDD, A1=VDD) */
+ #define SC16IS740_CLOCK 9216000 /* */
+#endif
#ifndef EM_Z80
#define EM_Z80 1 /* Emulate Z80 if true, else 8080 */
#define TESTVERSION 0
#endif
+#define TC_1MS (F_CPU/1000)
+#define TC_1US (F_CPU/1000000)
+
;-----------------------------------------------------------------------
; Port declarations
.equ RAM_CAS = 1
.equ RAM_OE = 2
.equ RAM_W = 3
+.equ SDA = 4
+.equ SCL = 5
.equ P_RAS = PORTC
.equ P_CAS = PORTC
.equ P_OE = PORTC
.equ P_W = PORTC
+.equ P_I2C = PORTC
#else /* 4 bit RAM, hardware uart */
#define CPUSTR "8080"
#endif
#if TESTVERSION
- #define TESTSTR "Test"
+ #define TESTSTR " Test"
#else
#define TESTSTR ""
#endif
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: dsk_fat16.asm 153 2014-11-12 12:59:42Z rapid $
;
; ============================================================================
.equ o_fat_clust_offset= 17
.equ o_fat_clust_ptr = 18
-.if SRAM_SIZE > 1024
+.if FAT16_FATBUF
fat_last_fatsect: .byte 1
.equ o_fat_last_fatsect = 22
fat_buf: .byte 512
-.endif
+.endif /* FAT16_FATBUF */
; ############################################################################
; Start of Code Segment
std y+o_fat_log_clust ,_255
std y+o_fat_log_clust+1,_255
std y+o_fat_last_dsk ,_255
-.if SRAM_SIZE > 1024
+.if FAT16_FATBUF
std y+o_fat_last_fatsect,_255
.endif
lsl zl
rol zh
-.if SRAM_SIZE > 1024
+.if FAT16_FATBUF
; Check, if required fat sector allready in buffer
ldd temp, z+0
ldd temp2,z+1
ldiw y,fat_vars
+
.else
ldd xl,y+o_fat_ptr2fat ;get FAT start
lcall mmcReadWord
movw temp,z
ldiw y,fat_vars
-.endif
+
+.endif /* FAT16_FATBUF */
+
pop xh
pop xl
ldi temp,1
lcall clockput
.endif
- rcall mgr_init_partitions ;disk chanched?
+ rcall mgr_init_partitions ;disk changed?
push temp
.if 0
ldi temp2,0x40
dskdbg1:
ldd temp,y+o_seekdsk
subi temp,-('A')
- rcall uartputc
+ lcall uartputc
printstring ": trk "
ldd temp2,y+o_seektrk+1
ldd temp,y+o_seektrk
breq dsk_hstwr_err
ldiw z,hostbuf
- rcall mmcWriteSect
+ lcall mmcWriteSect
tst temp
brne dsk_hstwr_err
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: i2c.asm 242 2015-12-11 16:05:52Z rapid $
;
#if I2C_SUPPORT
+
/* General TWI Master status codes */
#define TWI_START 0x08 /* START has been transmitted */
#define TWI_REP_START 0x10 /* Repeated START has been transmitted */
;
;----------------------------------------------------------------------
;
-;i2c_result < 0 Error.
-; -1 general/unknown error
-; -2 time out
-; >= 0 No error
-; > 0 status tbd.
+;i2c_result
+;
+; 0b10000000 Busy (Transmission in progress)
+; 0b01000000 Timeout
+; 0b00010000 Read after Write
+; 0b00001000 Start transmitted
+; 0b00000100 Slave acknowledged address
+; 0b00000010 Data byte(s) transmitted/received
+; 0b00000001 Transmission completed
+;
;
;----------------------------------------------------------------------
.byte 1
i2c_result:
.byte 1
-i2c_bufcnt:
+i2c_txcnt:
+ .byte 1
+i2c_rxcnt:
.byte 1
i2c_buf:
.byte I2C_BUFSIZE
.equ oi2ci_idx = 0
.equ oi2c_result = 1
- .equ oi2c_bufcnt = 2
- .equ oi2c_buf = 3
+ .equ oi2c_txcnt = 2
+ .equ oi2c_rxcnt = 3
+ .equ oi2c_buf = 4
;------------------------------------------------------------------
push temp
in temp,sreg
push temp
+ inm8 temp,TWSR
+.if I2C_STATE_DEBUG
+ push temp
+.endif
push temp2
+ push temp3
push zh
push zl
ldiw z,i2c_var
ldd temp2,z+oi2ci_idx
+ ldd temp3,z+oi2c_result
- inm8 temp,TWSR
cpi temp,TWI_START
breq i2ci_START
cpi temp,TWI_REP_START
breq i2ci_MTX_ADR_ACK
cpi temp,TWI_MTX_DATA_ACK
breq i2ci_MTX_DATA_ACK
+ cpi temp,TWI_MTX_DATA_NACK
+ breq i2ci_MTX_DATA_NACK
cpi temp,TWI_MRX_ADR_ACK
breq i2ci_MRX_ADR_ACK
cpi temp,TWI_MRX_DATA_ACK
breq i2ci_MRX_DATA_ACK
cpi temp,TWI_MRX_DATA_NACK
breq i2ci_MRX_DATA_NACK
+
rjmp i2ci_default
-i2ci_START:
-i2ci_REP_START:
- clr temp2 ;reset buffer pointer
-i2ci_MTX_ADR_ACK:
-i2ci_MTX_DATA_ACK:
- ldd temp,z+oi2c_bufcnt
- cp temp2,temp ;all bytes tranmited?
+i2ci_REP_START: ;Repeated START has been transmitted
+ cbr temp3,0b00010000
+i2ci_START: ;START has been transmitted
+ clr temp2 ;reset buffer index
+ ori temp3,0b10001000
+ rjmp i2ci_11
+i2ci_MTX_ADR_ACK: ;SLA+W has been transmitted and ACK received
+ ori temp3,0b00000100
+ rjmp i2ci_11
+i2ci_MTX_DATA_ACK: ;Data byte has been transmitted and ACK received
+ ori temp3,0b00000010
+i2ci_11:
+ ldd temp,z+oi2c_txcnt
+ cp temp2,temp ;all bytes transmited?
brsh i2ci_12 ; yes
add zl,temp2
adc zh,_0
ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
rjmp i2ci_end
+i2ci_MTX_DATA_NACK: ;Data byte has been transmitted and NACK received
i2ci_12:
- std z+oi2c_result,_0 ;done
- rjmp i2ci_default ;stop transceiver
+ ori temp3,0b00000001 ;tx complete
+ sbrs temp3,4 ;Read after Write?
+ rjmp i2ci_default ; no, stop transceiver
-i2ci_MRX_DATA_ACK:
+ lds temp,i2c_buf
+ sbr temp,0x01 ;<SLA+R>
+ sts i2c_buf,temp
+ ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
+ rjmp i2ci_end
+
+i2ci_MRX_ADR_ACK: ;SLA+R has been transmitted and ACK received
+ ori temp3,0b00000100
+ rjmp i2ci_31
+
+i2ci_MRX_DATA_ACK: ;Data byte has been received and ACK transmitted
+ ori temp3,0b00000010
add zl,temp2
adc zh,_0
inc temp2
inm8 temp,TWDR
std z+oi2c_buf,temp
-i2ci_MRX_ADR_ACK:
- lds temp,i2c_bufcnt
+i2ci_31:
+ lds temp,i2c_rxcnt
dec temp
cp temp2,temp
brsh i2ci_32
ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
rjmp i2ci_end
-i2ci_MRX_DATA_NACK:
- std z+oi2c_result,_0 ;result = ok
+i2ci_MRX_DATA_NACK: ;Data byte has been received and NACK transmitted
+ ori temp3,0b00000011 ;rx complete
add zl,temp2
adc zh,_0
+ inc temp2
inm8 temp,TWDR
std z+oi2c_buf,temp
; fall thru
i2ci_default:
- ldi temp,(1<<TWEN)|(1<<TWINT)|(1<<TWSTO)
+ andi temp3,~0b10000000
+ ldi temp,(1<<TWEN)|(0<<TWIE)|(1<<TWINT)|(1<<TWSTO)
i2ci_end:
outm8 TWCR,temp
+ sts i2c_result,temp3
sts i2ci_idx,temp2
pop zl
pop zh
+ pop temp3
pop temp2
+
+.if I2C_STATE_DEBUG
+ ldi temp,'|'
+ sei
+ rcall uartputc
+ pop temp
+ rcall printhex
+.endif
+
pop temp
out sreg,temp
pop temp
;------------------------------------------------------------------
i2c_init:
+ outm8 TWCR,_0 ;Disable TWI, disable TWI interrupt.
+ ;(Reset TWI hardware state machine.)
+ ldi temp,(5 * TC_1US+3)/3 ;1 Delay 5 us
+i2c_iwl: ;
+ dec temp ;1
+ brne i2c_iwl ;2
+
ldi temp,I2C_BR
outm8 TWBR,temp
outm8 TWDR,_255 ;
ldi temp,(1<<TWEN) ;Enable TWI, disable TWI interrupt.
outm8 TWCR,temp
- sts i2c_result,_0
+; sts i2c_result,_0
+
ret
;------------------------------------------------------------------
tst temp
brne i2c_wrl
- ldi temp,-2
- sts i2c_result,temp
+ rcall i2c_init
+
+ ldi temp,0b01000000
+
i2c_wre:
- tst temp
+ lds _tmp0,i2c_result
+ or temp,_tmp0
+ sts i2c_result,temp
ret
;------------------------------------------------------------------
i2c_write:
rcall i2c_waitready
- brmi i2c_we
+ cpi temp,0b01000000
+ brsh i2c_we
push zh
push zl
- push xh
- push xl
-
- ldiw x,i2c_result
- st x+,_255 ;result = not ok
- st x+,temp2 ;store size
- ld temp,z+
- cbr temp,0x01
+ push yh
+ push yl
+
+ ldiw y,i2c_var
+ ldi temp,0b10000000
+ std y+oi2c_result,temp ;result = busy
+ std y+oi2c_txcnt,temp2 ;store size
+ adiw y,oi2c_buf
+ ld temp,z+ ;get SLA
+ cbr temp,0x01 ;
i2c_wl:
- st x+,temp
+ st y+,temp
dec temp2
breq i2c_wle
ld temp,z+
ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
outm8 TWCR,temp
- pop xl
- pop xh
+ pop yl
+ pop yh
pop zl
pop zh
i2c_we:
;
; z: Pointer to data buffer.
; First byte of buffer is slave address
-; temp2: Number of bytes to write including address byte.
+; temp2: Buffer len. (Number of bytes to read + address byte.)
;
-; temp: return (fail = 0, else succsess)
+; temp: return (fail < 0, else succsess)
i2c_read:
-
rcall i2c_waitready
- brmi i2c_re
+ cpi temp,0b01000000
+ brsh i2c_re
push zh
push zl
- push xh
- push xl
- ldiw x,i2c_result
- st x+,_255 ;result = not ok
- st x+,temp2 ;store size
+ push yh
+ push yl
+ ldiw y,i2c_var
+ ldi temp,0b10000000
+ std y+oi2c_result,temp ;result = busy
+ std y+oi2c_rxcnt,temp2 ;store size
ld temp,z
- sbr temp,0x01
- st x,temp
+ sbr temp,0x01 ;<SLA+R>
+ std y+oi2c_buf,temp
; Enable TWI, TWI int and initiate start condition
ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
rcall i2c_waitready
- lds temp,i2c_result
- sbrc temp,7
+ sbrs temp,1 ;at least 1 byte received
rjmp i2c_ex ;
+ ldd temp2,y+oi2ci_idx
+ adiw y,oi2c_buf
i2c_rl:
- ld temp,x+
- st z+,temp
+ ld _tmp0,y+
+ st z+,_tmp0
dec temp2
brne i2c_rl
i2c_ex:
- pop xl
- pop xh
+ pop yl
+ pop yh
pop zl
pop zh
i2c_re:
lds temp,i2c_result
ret
+;------------------------------------------------------------------
+;
+; z: Pointer to the data to write/read.
+; First byte is slave address
+; temp2: Number of bytes to read, including address byte.
+;
+
+i2c_write_read:
+
+ rcall i2c_waitready
+ cpi temp,0b01000000
+ brsh i2c_wr_e
+ push yh
+ push yl
+ push zh
+ push zl
+
+ ldiw y,i2c_var
+ ldi temp,0b10010000
+ std y+oi2c_result,temp ;result = busy
+ ldi temp,2
+ std y+oi2c_txcnt,temp ;store tx size
+ std y+oi2c_rxcnt,temp2 ;store rx size
+ adiw y,oi2c_buf
+
+ mov _tmp0,temp ;save tx count
+ ld temp,z+ ;get SLA
+ cbr temp,0x01 ;
+i2c_wr_wl:
+ st y+,temp
+ dec _tmp0
+ breq i2c_wr_wle
+ ld temp,z+
+ rjmp i2c_wr_wl
+i2c_wr_wle:
+ ; Enable TWI, TWI int and initiate start condition
+ ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
+ outm8 TWCR,temp
+
+ rcall i2c_waitready
+
+ sbrc temp,4 ;
+ rjmp i2c_wr_ex ;
+ sbrs temp,1 ;at least 1 byte received
+ rjmp i2c_wr_ex ;
+ ldiw y,i2c_var
+ ldd temp2,y+oi2ci_idx
+ adiw y,oi2c_buf
+ pop zl
+ pop zh
+ push zh
+ push zl
+i2c_wr_rl:
+ ld _tmp0,y+
+ st z+,_tmp0
+ dec temp2
+ brne i2c_wr_rl
+
+i2c_wr_ex:
+ pop zl
+ pop zh
+ pop yl
+ pop yh
+i2c_wr_e:
+ lds temp,i2c_result
+ ret
+
+
;------------------------------------------------------------------
.dseg
ret
vi2c_param_get:
+ tst temp3
+ brne vi2c_pg2
+
+ lds temp,i2ci_idx
+ rjmp vi2c_pge
+
+vi2c_pg2:
ldiw z,vi2c_blen
add zl,temp3
adc zh,_0
ld temp,z
+vi2c_pge:
ret
vi2c_param_set:
st z,temp
ret
+;------------------------------------------------------------------
+;
+; vi2c_addr: Pointer to the data to write.
+; First byte is slave address
+; vi2c_blen: Number of bytes to write including address byte.
+;
+
+vi2c_write:
+
+ rcall i2c_waitready
+ cpi temp,0b01000000
+ brsh vi2c_wex
+ ldiw z,i2c_var
+ ldi temp,0b10000000
+ std z+oi2c_result,temp ;result = busy
+ lds temp3,vi2c_blen
+ cpi temp3,I2C_BUFSIZE
+ brlo vi2c_w1
+ ldi temp3,I2C_BUFSIZE
+vi2c_w1:
+ std z+oi2c_txcnt,temp3 ;store size
+ adiw z,oi2c_buf
+ ldsw x,vi2c_addr
+ lcall dram_read_pp
+ cbr temp,0x01
+vi2c_wl:
+ st z+,temp
+ dec temp3
+ breq vi2c_wle
+ lcall dram_read_pp
+ rjmp vi2c_wl
+vi2c_wle:
+ ; Enable TWI, TWI int and initiate start condition
+ ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
+ outm8 TWCR,temp
+vi2c_wex:
+ ret
+
;------------------------------------------------------------------
;
; x: Pointer to the data buffer.
; First byte is slave address
-; temp3: Number of bytes to write including address byte.
+; temp3: Buffer len. (Number of bytes to read + address byte.)
;
vi2c_read:
rcall i2c_waitready
- brmi vi2c_rex
+ cpi temp,0b01000000
+ brsh vi2c_rex
ldiw z,i2c_var
- std z+oi2c_result,_255 ;result = not ok
+ ldi temp,0b10000000
+ std z+oi2c_result,temp ;result = busy
lds temp3,vi2c_blen
- std z+oi2c_bufcnt,temp3 ;store size
+ cpi temp3,I2C_BUFSIZE
+ brlo vi2c_r1
+ ldi temp3,I2C_BUFSIZE
+vi2c_r1:
+ std z+oi2c_rxcnt,temp3 ;store size
adiw z,oi2c_buf
ldsw x,vi2c_addr
lcall dram_read_pp
outm8 TWCR,temp
rcall i2c_waitready
-
- lds temp,i2c_result
- sbrc temp,7
- rjmp vi2c_rex ;
+ andi temp,0b00000011
+ breq vi2c_rex ;
vi2c_rl:
ld temp,z+
lcall dram_write_pp
;------------------------------------------------------------------
;
-; x: Pointer to the data to write.
-; First byte is slave address
-; temp2: Number of bytes to write including address byte.
+; vi2c_addr: Pointer to the data to write.
+; First byte is slave address
+; temp2: Number of bytes to write including address byte.
+;
+; vi2c_blen: Number of bytes to read including address byte.
;
-vi2c_write:
+vi2c_write_read:
rcall i2c_waitready
- brmi vi2c_wex
+ cpi temp,0b01000000
+ brsh vi2c_wr_ex
ldiw z,i2c_var
- std z+oi2c_result,_255 ;result = not ok
+ ldi temp,0b10010000
+ std z+oi2c_result,temp ;result = busy
+ std z+oi2c_txcnt,temp2 ;store tx size
lds temp3,vi2c_blen
- std z+oi2c_bufcnt,temp3 ;store size
+ cpi temp3,I2C_BUFSIZE
+ brlo vi2c_wr_w1
+ ldi temp3,I2C_BUFSIZE
+vi2c_wr_w1:
+ std z+oi2c_rxcnt,temp3 ;store rx size
adiw z,oi2c_buf
ldsw x,vi2c_addr
lcall dram_read_pp
cbr temp,0x01
-vi2c_wl:
+vi2c_wr_wl:
st z+,temp
- dec temp3
- breq vi2c_wle
+ dec temp2
+ breq vi2c_wr_wle
lcall dram_read_pp
- rjmp vi2c_wl
-vi2c_wle:
+ rjmp vi2c_wr_wl
+vi2c_wr_wle:
; Enable TWI, TWI int and initiate start condition
ldi temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
outm8 TWCR,temp
-vi2c_wex:
+
+ rcall i2c_waitready
+
+ sbrc temp,4 ;
+ rjmp i2c_wr_ex ;
+ andi temp,0b00000011 ;
+ breq vi2c_rex ;
+ ldiw z,i2c_var
+ ldd temp2,z+oi2ci_idx
+ adiw z,oi2c_buf+1
+ ldsw x,vi2c_addr
+ adiw x,1
+ rjmp vi2c_wr_rl0
+vi2c_wr_rl:
+ ld temp,z+
+ lcall dram_write_pp
+vi2c_wr_rl0:
+ dec temp2
+ brne vi2c_wr_rl
+
+vi2c_wr_ex:
ret
;------------------------------------------------------------------
vi2c_ctrl:
- cpi temp,1
+ cpi temp,1 ;read ?
brne vi2c_c1
rjmp vi2c_read
vi2c_c1:
- cpi temp,2
+ cpi temp,2 ;write?
brne vi2c_c2
rjmp vi2c_write
vi2c_c2:
+ cpi temp,3 ;write and read ?
+ brne vi2c_c3
+ ldi temp2,2 ;write 1 byte (subaddress), then read
+ rjmp vi2c_write_read
+vi2c_c3:
vi2c_ce:
ret
ret
+;------------------------------------------------------------------
+
+#if I2C_UART_SUPPORT
+
+SC16IS740_in:
+ ; make a buffer on stack
+ swap temp3
+ lsr temp3
+ push temp3 ;register address
+ in zh,sph
+ in zl,spl
+ ldi temp,SC16IS740_ADDR ;chip address (8 bit)
+ push temp ;slave address
+ ldi temp2,2
+ rcall i2c_write_read
+ pop temp ;remove slave address from stack
+ pop temp ;return input value
+ ret
+
+SC16IS740_out:
+ ; make a buffer on stack
+ push temp ;output value
+ swap temp3
+ lsr temp3
+ push temp3 ;register address
+ in zh,sph
+ in zl,spl
+ ldi temp,SC16IS740_ADDR ;chip address (8 bit)
+ push temp ;slave address
+ ldi temp2,3
+ rcall i2c_write
+ pop temp ;remove buffer from stack
+ pop temp ;
+ pop temp ;
+ ret
+
+#endif /* I2C_UART_SUPPORT */
+
#endif /* I2C_SUPPORT */
;------------------------------------------------------------------
; vim:set ts=8 noet nowrap
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: init.asm 241 2015-12-10 09:38:25Z rapid $
;
#define REFR_PRE 8 /* timer prescale factor 1/8 */
out PORTD,_255 ;all pins high (enables pullup on input ports)
out PORTB,_255
out PORTC,_255
- out DDRD,_255 ; all outputs
- out DDRB,_255
- out DDRC,_255
- cbi P_RXD-1,RXD ; RXD pin is input
+ out DDRD,_255 ; PD all outputs
+#if I2C_SUPPORT
+ ldi temp,~((1<<SCL)|(1<<SDA))
+ out DDRC,temp
+#endif
+#if DRAM_8BIT
+ ldi temp,~(1<<RXD)
+ out DDRB,temp
+#endif
outm8 TIMSK1,_0
outm8 TIMSK2,_0
; Init timer 1 as 1 ms system clock tick.
- ldi temp, low (F_CPU/1000)
- ldi temp2,high(F_CPU/1000)
+ ldi temp, low (TC_1MS)
+ ldi temp2,high(TC_1MS)
outm8 OCR1BH,temp2
outm8 OCR1BL,temp
ldi temp,(1<<ICNC1)|(1<<CS10) ;Noise cancel, fall. edge, Normal Mode, clk/1
.endif
rcall printstr
- .db 13,13,"CPM on an AVR, v"
- db_version VMAJOR, VMINOR
- printstring " r" SVN_REVSTR " " TESTSTR
+ .db '\r', '\r'
+version_string:
+ makestring "CPM on an AVR, v" VERS_STR " r" SVN_REVSTR TESTSTR
.if MEMTEST
printnewline
rcall dram_read
; ori temp,0x04 ;simulate error
-; andi temp,0xF7
+; andi temp,0xF7 ;another error
mov temp2,xh
eor temp2,xl
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: macros.inc 241 2015-12-10 09:38:25Z rapid $
;
;------------------------------------------------
.endif
.endm
+;------------------------------------------------
+; Make string.
+; makestring "String"
+
+.macro makestring
+ .if strlen(@0) % 2
+ .db @0,0
+ .else
+ .db @0,0,0
+ .endif
+.endm
+
;------------------------------------------------
; Print string.
; printstring "String"
* (http://www.compuphase.com/svnrev.htm).
* You should not modify it manually, as it may be re-generated.
*
- * $Revision: 215$
- * $Date: 2013-04-27$
+ * $Revision: 242M$
+ * $Date: 2015-12-11$
*/
#ifndef SVN_REV_H
#define SVN_REV_H
-#define SVN_REV 215
-#define SVN_REVSTR "215"
-#define SVN_REVDATE "2013-04-27"
-#define SVN_REVSTAMP 20130427L
-#define SVN_REVMODIFIED 0
+#define SVN_REV 242
+#define SVN_REVSTR "242M"
+#define SVN_REVDATE "2015-12-11"
+#define SVN_REVSTAMP 20151211L
+#define SVN_REVMODIFIED 6
#endif /* SVN_REV_H */
cpi temp,TXBUFSIZE ;
brsh sputc_l ;} while (txcount >= TXBUFSIZE)
+ cli
ldi zl,low(txfifo) ;
ldi zh,high(txfifo) ;
lds temp,txidx_w ;
sts txidx_w,temp ; txidx_w = ++txidx_w % TXBUFSIZE
pop temp ;
st z,temp ; txfifo[txidx_w] = char
- cli
+; cli
lds zh,txcount
inc zh
sts txcount,zh
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: timer.asm 153 2014-11-12 12:59:42Z rapid $
;
.dseg
push zh
inm8 zl,OCR1BL
inm8 zh,OCR1BH
- addiw z,F_CPU/1000
+ addiw z,TC_1MS
outm8 OCR1BH,zh
outm8 OCR1BL,zl
rcall i2c_write
ldi temp2,3
rcall i2c_read ;get year (stored in RTC-RAM addr. 10h)
- tst temp
- brmi rtc_get_e ;i2c error
+ andi temp,0x3
+ breq rtc_get_e ;i2c error
ldd temp3,z+1 ;save year
ldd xl, z+2
rcall i2c_write
ldi temp2,6
rcall i2c_read
- tst temp
- brmi rtc_get_e
+ andi temp,0x3
+ breq rtc_get_e ;i2c error
mov temp2,xl ;year century
ldd temp,z+4 ;get year
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: utils.asm 93 2014-01-03 16:32:32Z rapid $
;
.endif
+.if MEMDUMP_DEBUG
;-----------------------------------------------------------------------
; Prints 16 bytes RAM, pointed to by Z in hex.
-#if 0
-
dbg_hexdump_line: ;Address in z
push temp2
push temp
- printnewline
+; printnewline
movw temp,z ;Print address
rcall printhexw
+ printstring ":"
ldi temp2,16 ;16 byte per line
- rcall printspace
dbg_hdl1:
cpi temp2,8
brne PC+2
dbg_hdl2:
ld temp,z+
cpi temp,' '
- brlo dbg_hdpd
+ brlo dbg_hdlpd
cpi temp,0x7F
- brlo dbg_hdp
-dbg_hdpd:
+ brlo dbg_hdlp
+dbg_hdlpd:
ldi temp,'.'
-dbg_hdp:
+dbg_hdlp:
rcall uartputc
dec temp2
brne dbg_hdl2
rcall printspace
pop temp
pop temp2
+ printnewline
ret
-#endif
+
+
+; Prints temp2 bytes RAM, pointed to by Z in hex.
+
+dbg_hexdump: ;Address in z
+ push temp
+ push temp2
+; printnewline
+ movw temp,z ;Print address
+ rcall printhexw
+ printstring ":"
+ pop temp2
+ push temp2
+dbg_hd1:
+ rcall printspace
+ ld temp,z+
+ rcall printhex
+ dec temp2
+ brne dbg_hd1
+ pop temp2
+ sub zl,temp2
+ sbc zh,_0
+ rcall printspace
+ rcall printspace
+dbg_hd2:
+ ld temp,z+
+ cpi temp,' '
+ brlo dbg_hdpd
+ cpi temp,0x7F
+ brlo dbg_hdp
+dbg_hdpd:
+ ldi temp,'.'
+dbg_hdp:
+ rcall uartputc
+ dec temp2
+ brne dbg_hd2
+ pop temp
+ printnewline
+ ret
+
+.endif
;-----------------------------------------------------------------------
; Print a line with the 8080/Z80 registers
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: virt_ports.asm 242 2015-12-11 16:05:52Z rapid $
;
;------------------------ Virtual I2C interface --------------------------
;05 5 out - Control Port: 1 = Start read operation
; 2 = Start write operation
-;05 5 in - Status of last Transfer: 0 = ok, else fail
+; 3 = Write 1 byte subaddress, then read
+;05 5 in - Status of last Transfer
;06 6 in/out - Number of bytes to transfer, including Slave address
;07,08 7,8 in/out - Read/Write address low/high
;
+;------------------------ Debugging --------------------------------------
+;09 out - MEM dump: Number of bytes to print
+;0A,0B in/out - MEM dump: Start address
+;
+;------------------------ Version Information ----------------------------
+;0C out - 1 = Read VMAJOR
+; 2 = Read VMINOR
+; 4 = Read Version String
+;
;------------------------ Disk I/O ---------------------------------------
;0D,0E 13,14 in/out - Set address of Bios Controll Block
;0F 15 in/out - Disk select
;40 64-71 in/out - Timer/Clock control.
;41-46
;
-;47-4D clock - BCD format: ss, mm, hh, DD, MM, YYl, YYh
+;47-4D in/out - clock in BCD format: ss, mm, hh, DD, MM, YYl, YYh
+;
+;------------------------ Debugging --------------------------------------
+;4F out - Debug: start/stop trace, print stack, ...
;
-;4F debug - start/stop trace, print stack, ...
+;------------------------ ISC16IS740 UART --------------------------------
+;50 RHR in Receive Holding
+;50 THR out Transmit Holding
+;51 IER in/out Interrupt Enable
+;52 IIR in Interrupt Identification
+;52 FCR out FIFO Control
+;53 LCR in/out Line Control
+;54 MCR in/out Modem Control
+;55 LSR in Line Status
+;56 MSR in Modem Status
+;57 SPR in/out Scratchpad
+;56 TCR in/out Transmission Control
+;57 TLR in/out Trigger Level
+;58 TXLVL in Transmit FIFO Level
+;59 RXLVL in Receive FIFO Level
+;5F EFCR in/out Extra Features
+;50 DLL in/out divisor latch LSB
+;51 DLH in/out divisor latch MSB
+;52 EFR in/out Enhanced Feature
+;54 XON1 in/out Xon1 word
+;55 XON2 in/out Xon2 word
+;56 XOFF1 in/out Xoff1 word
+;57 XOFF2 in/out Xoff2 word
;
;------------------------ Ports ------------------------------------------
;80-87 in/out - Port-Expander PCF8574 (max. 8 Chips)
.dw clockget
.dw clockput
- .db DEBUGPORT,1
- .dw dbg_stat
- .dw dbg_ctrl
-
#if I2C_SUPPORT
.db I2CCTRL,1
.dw vi2c_stat_get
.dw vi2c_param_get
.dw vi2c_param_set
+#if I2C_UART_SUPPORT
+ .db I2C_UART,16
+ .dw SC16IS740_in
+ .dw SC16IS740_out
+#endif
+
.db PORT,8
.dw pcf8574_in
.dw pcf8574_out
.dw adc_readvcc
.dw vport_out_dummy
#endif
+ .db DEBUGPORT,1
+ .dw dbg_stat
+ .dw dbg_ctrl
+
+.if MEMDUMP_DEBUG
+ .db MEMDUMPPORT,3
+ .dw dbg_dump_rd
+ .dw dbg_dump
+.endif
+ .db 0x0C,1
+ .dw version_get
+ .dw version_ctrl
+
.db 0,0 ; Stop mark
;---------------------------------------------------------------------
ret
+;---------------------------------------------------------------------
+
dbgOut:
printnewline
printstring "Debug: "
.endif
ret
+;---------------------------------------------------------------------
+
+.if MEMDUMP_DEBUG
+
+ .dseg
+
+dbg_dump_addr:
+ .byte 2
+
+
+ .cseg
+
+dbg_dump_rd:
+ cpse temp3,_0
+ rjmp dbg_dump_rdad
+ ldi temp,0
+ ret
+
+dbg_dump_rdad:
+ dec temp3
+ brne dbg_dump_rdad1
+ lds temp,dbg_dump_addr+0
+ ret
+dbg_dump_rdad1:
+ lds temp,dbg_dump_addr+1
+ ret
+
+
+dbg_dump:
+ cpse temp3,_0
+ rjmp dbg_dump_store
+
+ mov temp3,temp
+ ldsw z,dbg_dump_addr
+
+ tst temp3
+ breq dbg_dumpl_1
+dbg_dumpl:
+ cpi temp3,16
+ brlo dbg_dump_u16
+dbg_dumpl_1:
+ lcall dbg_hexdump_line
+ subi temp3,16
+ adiw z,16
+ rjmp dbg_dumpl
+
+dbg_dump_u16:
+ tst temp3
+ breq dbg_dump_e
+ mov temp2,temp3
+ lcall dbg_hexdump
+dbg_dump_e:
+ ret
+
+dbg_dump_store:
+ dec temp3
+ brne dbg_dump_st1
+ sts dbg_dump_addr+0,temp
+ ret
+dbg_dump_st1:
+ sts dbg_dump_addr+1,temp
+ ret
+
+.endif
+
+;---------------------------------------------------------------------
+
+ .dseg
+vers_cmd:
+ .byte 1
+vers_pstr:
+ .byte 2
+
+ .cseg
+version_ctrl:
+ sts vers_cmd,temp
+ cpi temp,4
+ brne vc_e
+
+ ldiw z,version_string*2
+ stsw vers_pstr,z
+vc_e:
+ ret
+
+version_get:
+ lds temp2,vers_cmd
+ ldi temp,0
+ cpi temp2,0
+ breq vc_g_e
+ ldi temp,VMAJOR
+ cpi temp2,1
+ breq vc_g_e
+ ldi temp,VMINOR
+ cpi temp2,2
+ breq vc_g_e
+ ldi temp,0xFF
+ cpi temp2,4
+ brne vc_g_e
+
+ ldsw z,vers_pstr
+ lpm temp,z+
+ tst temp
+ breq vc_g_e
+ stsw vers_pstr,z
+
+vc_g_e:
+ ret
;---------------------------------------------------------------------
--- /dev/null
+
+;----------------------------- ISC16IS740 UART -------------------------------
+I2C_UART_PORT equ 50H
+
+I2C_UART_RHR equ I2C_UART_PORT+00H ;R Receive Holding
+I2C_UART_THR equ I2C_UART_PORT+00H ;W Transmit Holding
+I2C_UART_IER equ I2C_UART_PORT+01H ;R/W Interrupt Enable
+I2C_UART_FCR equ I2C_UART_PORT+02H ;W FIFO Control
+I2C_UART_IIR equ I2C_UART_PORT+02H ;R Interrupt Identification
+I2C_UART_LCR equ I2C_UART_PORT+03H ;R/W Line Control
+I2C_UART_MCR equ I2C_UART_PORT+04H ;R/W Modem Control
+I2C_UART_LSR equ I2C_UART_PORT+05H ;R Line Status
+I2C_UART_MSR equ I2C_UART_PORT+06H ;R Modem Status
+I2C_UART_SPR equ I2C_UART_PORT+07H ;R/W Scratchpad
+I2C_UART_TCR equ I2C_UART_PORT+06H ;R/W Transmission Control
+I2C_UART_TLR equ I2C_UART_PORT+07H ;R/W Trigger Level
+I2C_UART_TXLVL equ I2C_UART_PORT+08H ;R Transmit FIFO Level
+I2C_UART_RXLVL equ I2C_UART_PORT+09H ;R Receive FIFO Level
+I2C_UART_EFCR equ I2C_UART_PORT+0FH ;R/W Extra Features
+I2C_UART_DLL equ I2C_UART_PORT+00H ;R/W divisor latch LSB
+I2C_UART_DLH equ I2C_UART_PORT+01H ;R/W divisor latch MSB
+I2C_UART_EFR equ I2C_UART_PORT+02H ;R/W Enhanced Feature
+I2C_UART_XON1 equ I2C_UART_PORT+04H ;R/W Xon1 word
+I2C_UART_XON2 equ I2C_UART_PORT+05H ;R/W Xon2 word
+I2C_UART_XOFF1 equ I2C_UART_PORT+06H ;R/W Xoff1 word
+I2C_UART_XOFF2 equ I2C_UART_PORT+07H ;R/W Xoff2 word
+
+
+;-----------------------------------------------------------------------------
+; Output character in C
+; Return with character in C and A
+
+i2c_uart_out:
+ IN A,(I2C_UART_LSR)
+ AND 20H
+ JR Z,i2c_uart_out ; wait till ready
+ LD A,C
+ OUT (I2C_UART_THR),A
+ RET
+
+;-----------------------------------------------------------------------------
+; Get character from I2C UART
+; Return character in A
+
+i2c_uart_in:
+ IN A,(I2C_UART_LSR)
+ AND 01H
+ JR Z,i2c_uart_in ; wait till ready
+ IN (I2C_UART_RHR),A
+ RET
projects / avrcpm.git / commitdiff